Dallas Semiconductor DS2251T-64-16, DS2251T-32-16, DS2251T-128-16 Datasheet

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DS2251(T)

128k Soft Microcontroller Module

FEATURES

 8051-compatible microcontroller adapts to its

task

- 32K, 64K, or 128K bytes of nonvolatile

SRAM for program and/or data storage

- In-system programming via on-chip serial

port

- Capable of modifying its own program or

data memory in the end system

- Provides separate Byte-wide bus for

peripherals

- Performs CRC-16 check of NV RAM

memory

 High-reliability operation

- Maintains all nonvolatile resources for

over 10 years in the absence of power

- Power-fail reset

- Early Warning Power-fail Interrupt

- Watchdog Timer

- Lithium backed memory remembers

system state

- Precision reference for power monitor

 Fully 8051-compatible

- 128 bytes scratchpad RAM

- Two timer/counters

- On-chip serial port

- 32 parallel I/O port pins

 Permanently powered real time clock

PIN ASSIGNMENT

721

72-Pin SIMM

DESCRIPTION

The DS2251T 128k Soft Microcontroller Module is an 8051-compatible microcontroller module based on nonvolatile RAM technology. It is designed for systems that need large quantities of nonvolatile memor y. Like other members of the Secure Microcontroller family, it provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can program, then reprogram the microcontroller while in-system. The application software can even change its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc. In addition, by using NV RAM, the DS2251T is ideal for data logging applications. The powerful re al time clock includes interrupts for time stamp and date. It keeps time to one-hundredth of seconds using its onboard 32 kHz crystal.

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DS2251T

The DS2251T provides the benefits of NV RAM without using I/O resources. Between 32 kbytes and 128 kbytes of onboard NV RAM are available. A non-multiplexed Byte-wide address and data bus is used for memory access. This bus, which is available at the connector, can perform all memory access and also provide decoded chip enables for off-board memory mapped peripherals. This leaves the 32 I/O port pins free for application use.

The DS2251T provides high-reliability operation in portable systems or systems with unreliable power. These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power.

A user loads programs into the DS2251T via its on-chip serial Bootstrap loader. This function supervises the loading of software into NV RAM, validates it, then becomes transparent to the user. Software is stored in onboard CMOS SRAM. Using its internal Partitioning, the DS2251T can divide a common RAM into user-selectable program and data segments. This Partition can be selected at program loading time, but can be modified anytime later. The microprocessor will decode memory access to the SRAM, access memory via its Byte-wide bus and write-protect the memory portion designated as program (ROM).

ORDERING INFORMATION

PART NUMBER RAM SIZE

MAX CRYSTAL

SPEED

TIMEKEEPING?

DS2251T-32-16 32 kbytes 16 MHz Yes DS2251T-64-16 64 kbytes 16 MHz Yes DS2251T-128-16 128 kbytes 16 MHz Yes

Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specifications.

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DS2251(T) BLOCK DIAGRAM Figure 1

DS2251T

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PIN ASSIGNMENT

1 P1.0 19 XTAL2 37 P0.2 55 2 P1.1 20 GND 38 P0.1 56 BD0

3 P1.2 21 P2.0 39 P0.0 57 BD1

INTB

DS2251T

4 P1.3 22 P2.1 40 V

58 BD2 5 P1.4 23 P2.2 41 BA0 59 BD3 6 P1.5 24 P2.3 42 BA1 60 BD4 7 P1.6 25 P2.4 43 BA2 61 BD5 8 P1.7 26 P2.5 44 BA3 62 BD6 9 RST 27 P2.6 45 BA4 63 BD7 10 P3.0 RXD 28 P2.7 46 BA5 64

11 P3.1 TXD 29 12 13

P3.2

INT0

P3.3 INT1

30 ALE 48 BA7 66 31

PSEN

PROG

47 BA6 65

49 BA8 67 14 P3.4 T0 32 P0.7 50 BA9 68 15 P3.5 T1 33 P0.6 51 BA10 69 16 17

P3.6 WR P3.7 RD

34 P0.5 52 BA11 70 SQW 35 P0.4 53 BA12 71

R/W

PE3

PE4

INTP INTA

VRST

18 XTAL1 36 P0.3 54 BA13 72 BA15

PIN DESCRIPTION

39-32 P0.0 - P0.7. General purpose I/O Port 0. This port is open-drain and cannot drive a logic 1.

It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pullups.

1-8 P1.0 - P1.7. General purpose I/O Port 1.

21-28

10 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on-

14 P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input. 15 P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.

P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus.

board UART. This pin should NOT be connected directly to a PC COM port. P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on-

board UART. This pin should NOT be connected directly to a PC COM port. P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External

Interrupt 0.

P3.3

INT1. General purpose I/O port pin 3.3. Also serves as the active low External

Interrupt 1.

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PIN DESCRIPTION

DS2251T

P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation.

P3.7 RD. General purpose I/O port pin. Also serves as the re ad strobe for Expanded bus operation.

RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally, can be left unconnected if not used. An RC power-on reset circuit is not needed and is NOT recommended.

PSEN - Program Store Enable. This active l ow si gnal is used to en able an ex ternal prog ram

memory when using the Expanded bus. It is normally an output and should be unconn ected if not used.

ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a ‘373 type transparent latch.

19, 18 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is

the input to an inverting amplifier and XTAL2 is the output.

20 GND - Logic ground. 40 VCC - +5V. 72

BA15 - Monitor test point to reflect the logical value of A15. Not needed for memory access.

54-41 BA13 - 0. Byte-wide Address bus bits 13-0. This bus is combined with the non-multiplexed

data bus (BD7-0) to access onboard NV SRAM and off-board peripherals. Peripheral decoding is performed using PE3 and PE4 . These are on 16k boundaries, so BA14 or BA15 are not needed. Read/write access is controlled by R/ W . BA13-0 connect directly to memory mapped peripherals.

63-56

BD7 - 0. Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the non-multiplexed address bus (BA14-0) to access on-board NV SRAM and off-board peripherals.

W - Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide

bus. It is controlled by the memory map and Partition. The blocks selected as Program (ROM) will be write-protected. This signal is also used for the write enable to off-board peripherals.

PE3 - Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh

when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any type of peripheral function.

PE4 - Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh

when the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any type of peripheral function.

PROG - Invokes the Bootstrap loader on a falling ed ge. This signal should be deboun ced so

that only one edge is detected. If connected to ground, the micro will enter Bootstrap loading on power-up. This signal is pulled up internally.

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PIN DESCRIPTION

DS2251T

VRST - This I/O pin (open-drain with internal pullup) indicates that the power supply (V

has fallen below the V

level and the micro is in a reset state. When this occurs, the

CCMIN

)

DS2251T will drive this pin to a logic 0. Because the micro is lithium backed, this signal is guaranteed even when VCC=0V. Because it is an I/O pin, it will also force a reset if pulled low externally. This allows multiple parts to synchronize their power-down resets.

PF - This output goes to a logic 0 to indicate that the micro has switched to lithium backup.

It corresponds to VCC < VLI. Because the micro is lithium backed, this signal is guaranteed even when VCC=0V.

INTB - INTB from the real time clock. This output may be connected to a micro interrupt

input.

INTP - INTP from the real time clock. This open-drain output requires a pullup and may be

connected to a micro interrupt input.

INTA - INTA from the real time clock. This output may be connected to a micro interrupt

input.

70 SQW - SQW output from the DS1283 Real Time Clock. Can be programmed to output an

1024 Hz square wave.

INSTRUCTION SET

The DS2251T executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS2251T.

A complete description of the instruction set and operation are provided in the User’s Guide section of the Secure Microcontroller Data Book.

MEMORY ORGANIZATION

Figure 2 illustrates the memory map accessed by the DS2251T. The entire 64k of program and 64k of data are available to the B yte-wide bus. This pr eserv es t he I/O ports fo r appli cation use. The user controls the portion of memory that is actually mapped to the Byte-wide bus by selecting the Program Range and Data Range. Any area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 and 2. An alternate configuration allows dynamic Partitioning of a 64k space as shown in Figure 3. Selecting

PES=1 provides access to the real time clock on the DS2251T and enables access as shown in Figure 4. These selections are made using Special Function Registers. The memory map and its controls are covered in detail in the User’s Guide section of the Secure Microcontroller Data Book.

PE3 and PE4 for peripher al

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