Dallas Semiconductor DS2227-70, DS2227-120, DS2227-100 Datasheet

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DS2227

Flexible NV SRAM Stik

FEATURES

 Flexibly organized as 128k x 32, 256k x 16,

or 512k x 8 bits

 Data retention >10 years in the absence of

 Nonvolatile circuitry transparent to and

independent from host system

 Automatic write protection circuitry

safeguards against data loss

 Separate chip enables allow access by byte,

word, or long word

 Fast access times: 70 ns, 100 ns, or 120 ns  Unlimited write cycles  Read cycle time equals write cycle time  Employs popular JEDEC standard 72-position

SIMM connection scheme

 Lithium energy source is electrically

disconnected to retain freshness until power is applied for the first time

PIN ASSIGNMENT

SRAM

721

72-Pin SIP STIK

DESCRIPTION

The DS2227 Flexible NV SRAM Stik is a self-contained 4,194,304-bit nonvolatile static RAM which can be flexibly organized as 128k x 32 bits, 256k x 16 bits, or 512k x 8 bits. The nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. The DS2227 employs the popular JEDEC standard 72-position SIMM connection scheme requiring no additional circuitry.

OPERATION

The DS2227 Flexible NV SRAM Stik is used like any standard static RAM. All nonvolatile circuitry is transparent to the user. The flexibility of the part is achieved by providing separate read, write, and chip

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DS2227

select pins for each of the four banks of onboard memories (see Figure 1). For operation as a 512k x 8 NV SRAM Stik, tie all data lines from each bank together (i.e., all D0s together, all D1s together, etc.). Read enables and write enables are also tied together. For operation as a 256k x 16 NV SRAM Stik, tie the data lines from two banks together. Chip enables, read enables, and write enables from these banks are also tied together. Connection to the DS2227 is made by using an industry-standard, 72-position SIMM socket DS9072-72V (AMP part number 821824-8). These SIMM sockets are also available in perpendicular,

inclined, or parallel mount, depending on the height available. See the DS907x SipStik

connectors

available from Dallas Semiconductor.

READ MODE

The DS2227 executes a read cycle wheneve r WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified b y the 17 address inputs (A0 - A16)

defines which byte of data is to be accessed. Valid data will be available to the eight data I/O pins within t

(access time) after the last address input signal is stable, providing that CE and OE access times ar e

ACC

also satisfied. If OE and CE times are not satisfied, then data access must be measured from the later occurring signal (CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than

address access.

WRITE MODE

The DS2227 is in the write mode whenever both WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active) then WE will disable the outputs to t

from its falling edge.

ODW

DATA RETENTION MODE

The DS2227 provides fully functional capability for VCC greater than 4.5 volts and guarantees write protection for VCC less than 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The DS2227 constantly monitors V SRAM automatically write-protects itself, all inputs become “don’t care” and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects a lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects the external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts.

The DS2227 checks lithium status to warn of potential data loss. Each time that V the DS2227, the battery voltage is checked with a precision comparator. If the battery supply is less than

2.0 volts, the second memory access to the device is inhibited. Battery status can, therefore, be determined by a three-step process. First, a read cycle is performed to any location in memory, in order to save the contents of that location. A subsequent write cycle can then be executed to the same memory location, altering data. If the next read cycle fails to verify the written data, then the battery voltage is less than 2.0V and data is in danger of being corrupted.

The DS2227 also provides battery redundancy. In many applications data integrity is paramount. The DS2227 provides two batteries for each SRAM and an internal isolation switch to select between them. During battery backup, the battery with the highest voltage is selected for use . If one battery fails, the other automatically takes over. The switch between batteries is transparent to the user.

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. Should the supply voltage decay, the NV

power is restored to

DS2227

PIN DESCRIPTION Table 1

PIN SIGNAL NAME PIN SIGNAL NAME

1VCC38 4-D0 2 1-D0 39 4-D1 3 1-D1 40 4-D2 4 1-D2 41 4-D3 5 1-D3 42 4-D4 6 1-D4 43 4-D5 7 1-D5 44 4-D6 8 1-D6 45 4-D7 91-D746NC 10 NC 47

11 12 13

1-CE 1-

1-WE

48 49 50 GND

14 2-D0 51 V 15 2-D1 52 A0 16 2-D2 53 A1 17 2-D3 54 A2 18 2-D4 55 A3 19 2-D5 56 A4 20 2-D6 57 A5 21 2-D7 58 A6 22 NC 59 A7 23

24 25

2-CE 2-OE 2-WE

60 A8 61 A9 62 A10

26 3-D0 63 A11 27 3-D1 64 A12 28 3-D2 65 A13 29 3-D3 66 A14 30 3-D4 67 A15 31 3-D5 68 A16 32 3-D6 69 NC 33 3-D7 70 NC 34 NC 71 NC 35

36 37

3-CE 3-OE 3-WE

72 GND

NOTE: Leave all pins marked as NC unconnected.

4-CE 4-OE 4-

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