Dallas Semiconductor DS21FT40N, DS21FT40 Datasheet

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MULTI-CHIP MODULE FEATURES

• Twelve (12) completely independent

E1 Framers in one small 27 mm x 27 mm

Package

• Each Multi-Chip Module (MCM) Contains

Three DS21Q44 Quad E1 Framer Die

• Each Quad Framer can be concatenated into

a Single 8.192 MHz Backplane Data Stream

• 300–pin MCM 1.27 mm pitch BGA package

(27 mm X 27 mm)

• Low Power 3.3V CMOS with 5V Tolerant

Input & Outputs

FRAMER FEATURES

• All framers are fully independent; transmit

and receive sections of each framer are fully
independent

• Frames to FAS, CAS, CCS, and CRC4

formats

• Each framer contains dual two–frame elastic

store slip buffers that can connect to
asynchronous backplanes up to 8.192 MHz

• 8–bit parallel control port that can be used

directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)

• Easy access to Si and Sa bits

• Extracts and inserts CAS signaling

FUNCTIONAL DIAGRAM

Receive

Framer

Elastic

Store

Transmit

Formatter

Elastic

Store

FRAMER #1

FRAMER #2

FRAMER #3

Control Port

FRAMER #12

ρρρ

ρρρρρρ

ρρρ

• Large counters for bipolar and code

violations, CRC4 code word errors, FAS
word errors, and E-bits

• Programmable output clocks for Fractional

E1, per channel loopback, H0 and H12
applications

• Integral HDLC controller with 64-byte

buffers. Configurable for Sa bits or DS0
operation

• Detects and generates AIS, remote alarm,

and remote multiframe alarms

• IEEE 1149.1 support

DESCRIPTION

The DS21FT40 MCM offers a high density packaging arrangement for the DS21Q44 E1 Enhanced Quad
Framer. Three DS21Q44 silicon die are packaged in a Multi-Chip Module (MCM) with the electrical
connections as shown in Figure 1-1. The DS21FT40 is closely related to the DS21FT44. Most of the
functions of the DS21FT44 are available on the DS21FT40. The differences are listed in Table 1-1.
Table 2-1 lists all of the signals on the MCM.

The DS21Q44 E1 Framer is an enhanced version of the DS21Q43 Quad E1 Framer. Each DS21Q44 die
contains four framers that are configured and read through a common microprocessor-compatible parallel
port. Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit
elastic store. All four framers in the DS21Q44 are totally independent, they do not share a common
framing synchronizer. Also, the transmit and receive sides of each framer are totally independent. The

DS21FT40

Four x Three 12 Channel E1 Frame

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DS21FT40

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dual two-frame elastic stores contained in each of the four framers can be independently enabled and
disabled as required. The device fully meets all of the latest E1 specifications including CCITT/ITU
G.704, G.706, G.962, and I.431 as well as ETS 300 011 and ETS 300 233.

Functional Description

The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as
detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If
needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz
clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.

The transmit side in each framer is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission.

Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In
each 125 us frame, there are 32 8–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and
received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32.
Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or
channel) is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted
first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following
abbreviations will be used:

FAS Frame Alignment Signal
CAS Channel Associated Signaling
MF Multiframe
Si International bits
CRC4 Cyclical Redundancy Check
CCS Common Channel Signaling
Sa Additional bits
E-bit CRC4 Error Bits

DS21FT40

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DS21FT40 Schematic Figure 1-1

RCLK1/2/3/4
RPOS1/2/3/4
RNEG1/2/3/4
RSER1/2/3/4

RSYNC1/2/3/4

RSYSCLK1/2/3/4

TCLK1/2/3/4

TNEG1/2/3/4

TPOS1/2/3/4

TSER1/2/3/4

TSSYNC1/2/3/4

TSYNC1/2/3/4

TSYSCLK1/2/3/4

TLINK0/1/2/3

INT*

FMS

D0 to D7

A0 to A7

RD*

WR*

BTS

MUX

CS*

FS0/FS1

TEST

Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RLCLK
RCHBLK
RCHCLK
RFSYNC
TLCLK
TCHCLK
TCHBLK
RSIG
TSIG
8MCLK
CLKSI
JTRST*
JTMS
JTCLK
JTDI
JTDO

DS21Q44 # 1

RCLK5/6/7/8
RPOS5/6/7/8
RNEG5/6/7/8
RSER5/6/7/8

RSYNC5/6/7/8

RSYSCLK5/6/7/8

TCLK5/6/7/8

TNEG5/6/7/8

TPOS5/6/7/8

TSER5/6/7/8

TSSYNC5/6/7/8

TSYNC5/6/7/8

TSYSCLK5/6/7/8

INT*

D0 to D7

A0 to A7

RD*

WR*

BTS

MUX

CS*

FS0/FS1

TEST

Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RLCLK
RCHBLK
RCHCLK
RFSYNC
TLCLK
TCHCLK
TCHBLK
RSIG
TSIG
8MCLK
CLKSI
JTRST*
JTMS
JTCLK
JTDI
JTDO

DS21Q44 # 2

2

8
8

See Connecting Page

DVDD

DVSS

DVSS

TLINK0/1/2/3

FMS

DVSS

DVSS

DVDD

RMSYNC5/6/7/8

RMSYNC1/2/3/4

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DS21FT40 Schematic Figure 1-1 (continued)

Changes in DS21FT40 compared to DS21FT44 Table 1-1

1. The SYSCLK pins have been separated into TSYSCLK and RSYSCLK pins.

2. RMSYNC pins have been added.

3. FMS tied to Vdd.

4. The following signals are not available:

RSIG / TSIG / 8MCLK / CLKSI / JTRST* / JTMS / JTCLK / JTDI / JTDO

RCLK9/10/11/12
RPOS9/10/11/12
RNEG9/10/11/12
RSER9/10/11/12

RSYNC9/10/11/12

RSYSCLK9/10/11/12

TCLK9/10/11/12

TNEG9/10/11/12

TPOS9/10/11/12

TSER9/10/11/12

TSSYNC9/10/11/12

TSYNC9/10/11/12

TSYSCLK9/10/11/12

TLINK0/1/2/3

INT*

FMS

D0 to D7

A0 to A7

RD*

WR*

BTS

MUX

CS*

FS0/FS1

TEST

Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RLCLK
RCHBLK
RCHCLK
RFSYNC
TLCLK
TCHCLK
TCHBLK
RSIG
TSIG
8MCLK
CLKSI
JTRST*
JTMS
JTCLK
JTDI
JTDO

DS21Q44 # 3

DVDD

DVSS

DVSS

See Connecting Page

RMSYNC9/10/11/12

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DS21FT40 ENHANCED 12-Channel E1 FRAMER Figure 1-2

VSS

VDD

FRAMER #2

FRAMER #3

FRAMER #1

Parallel & Test Control Port

(routed to all blocks)

D0 to D7 /

AD0 to AD7

FS1

BTS

INT*

WR*

(R/W*)

RD*

(DS*)

FS0CS*TEST

ALE

(AS)/

A6

A0 to A5,

A7

MUX

7

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Receive Side Framer

Transmit Side Formatter

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Store

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TSYNC

TCLK

TSER

RMSYNC

TSSYNC
TSYSCLK

RSER
RSYSCLK
RSYNC

Sa Extraction

Timing Control

Elastic

Store

Sync Control

Timing Control

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Signaling

Buffer

Hardware
Signaling
Insertion

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64-Byte Buffer

RPOS
RCLK
RNEG

TPOS

TNEG

HDLC Engine
DS0 Insertion

Power

LOTC DET
&
MUX

Sa Insertion

64-Byte Buffer
HDLC Engine
DS0 Insertion

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FRAMER #12

DS21FT40

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TABLE OF CONTENTS

DESCRIPTION..........................................................................................................................................................................1

1. DS21FT40 PIN DESCRIPTION.......................................................................................................................................8

2. DS21FT44 PIN FUNCTION DESCRIPTION...............................................................................................................16

3. DS21FT40 REGISTER MAP..........................................................................................................................................19

4. PARALLEL PORT..........................................................................................................................................................24

5. CONTROL, ID AND TEST REGISTERS.....................................................................................................................24

6. STATUS AND INFORMATION REGISTERS............................................................................................................33

7. ERROR COUNT REGISTERS......................................................................................................................................39

8. DS0 MONITORING FUNCTION..................................................................................................................................41

9. SIGNALING OPERATION............................................................................................................................................44

9.1 PROCESSOR BASED SIGNALING........................................................................................................................44

9.2 HARDWARE BASED SIGNALING........................................................................................................................ 47

10. PER–CHANNEL CODE GENERATION AND LOOPBACK................................................................................47

10.1 TRANSMIT SIDE CODE GENERATION...............................................................................................................47

10.1.1 Simple Idle Code Insertion and Per–Channel Loopback...................................................................................47

10.1.2 Per–Channel Code Insertion.............................................................................................................................48

10.2 RECEIVE SIDE CODE GENERATION..................................................................................................................49

11. CLOCK BLOCKING REGISTERS ..........................................................................................................................50

12. ELASTIC STORES OPERATION ............................................................................................................................50

12.1 RECEIVE SIDE.........................................................................................................................................................51

12.2 TRANSMIT SIDE.....................................................................................................................................................51

13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION................................................................51

13.1 INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME.....................................................................51

13.2 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME................................................................53

14. HDLC CONTROLLER FOR THE SA BITS OR DS0.............................................................................................55

14.1 G

ENERAL OVERVIEW..................................................................................................................................................55

14.2 HDLC S

TATUS REGISTERS.........................................................................................................................................56

14.3 B

ASIC OPERATION DETAILS........................................................................................................................................57

14.4 HDLC R

EGISTER DESCRIPTION ..................................................................................................................................58

15. INTERLEAVED PCM BUS OPERATION..............................................................................................................64

16. TIMING DIAGRAMS.................................................................................................................................................67

17. OPERATING PARAMETERS...................................................................................................................................75

18. DS21FT40 MECHANICAL DIMENSIONS..............................................................................................................86

DS21FT40

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DOCUMENT REVISION HISTORY

Revision Notes

5-18-99 Initial Release
8-19-99 Concatenated DS21FT40 and DS21Q44 data sheets
8-26-99 Remove RCHBLK pins.
2-17-00 Corrected error in Figure 1-1 (removed RCHBLK pins).

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1. DS21FT40 PIN DESCRIPTION
Pin Description Sorted by Pin Number Table 2-1

Lead Symbols I/O Description

G20 A0 I Address Bus Bit 0 (lsb).
H20 A1 I Address Bus Bit 1.
G19 A2 I Address Bus Bit 2.
H19 A3 I Address Bus Bit 3.
G18 A4 I Address Bus Bit 4.
H18 A5 I Address Bus Bit 5.
G17 A6 I Address Bus Bit 6.
H17 A7 I Address Bus Bit 7 (msb).

W15 BTS I Bus Timing Select. 0 = Intel / 1 = Motorola.

T8 CS1* I Chip Select for Quad Framer 1.
Y4 CS2* I Chip Select for Quad Framer 2.

Y15 CS3* I Chip Select for Quad Framer 3.

L20 D0 I/O Data Bus Bit 0 (lsb).

M20 D1 I/O Data Bus Bit 1.

L19 D2 I/O Data Bus Bit 2.

M19 D3 I/O Data Bus Bit 3.

L18 D4 I/O Data Bus Bit 4.

M18 D5 I/O Data Bus Bit 5.

L17 D6 I/O Data Bus Bit 6.

M17 D7 I/O Data Bus Bit 7 (msb).

C7 DVDD1 – Digital Positive Supply for Framer 1.
E4 DVDD1 – Digital Positive Supply for Framer 1.
D2 DVDD1 – Digital Positive Supply for Framer 1.
K3 DVDD2 – Digital Positive Supply for Framer 2.
U7 DVDD2 – Digital Positive Supply for Framer 2.
P2 DVDD2 – Digital Positive Supply for Framer 2.

V19 DVDD3 – Digital Positive Supply for Framer 3.

T12 DVDD3 – Digital Positive Supply for Framer 3.
L16 DVDD3 – Digital Positive Supply for Framer 3.

E9 DVSS1 – Digital Signal Ground for Framer 1.
A6 DVSS1 – Digital Signal Ground for Framer 1.
D5 DVSS1 – Digital Signal Ground for Framer 1.
U3 DVSS2 – Digital Signal Ground for Framer 2.
K4 DVSS2 – Digital Signal Ground for Framer 2.
U8 DVSS2 – Digital Signal Ground for Framer 2.

U4 DVSS3 – Digital Signal Ground for Framer 3.
R16 DVSS3 – Digital Signal Ground for Framer 3.
Y20 DVSS3 – Digital Signal Ground for Framer 3.
Y14 FS0 I Framer Select 0 for the Parallel Control Port.

W14 FS1 I Framer Select 1 for the Parallel Control Port.

G16 INT* O Interrupt for all four Quad Framers.

P17 MUX I Bus Operation Select. 0 = non-multiplexed bus / 1 =

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Lead Symbols I/O Description

multiplexed bus
A2 RCLK1 I Receive Clock for Framer 1
K1 RCLK2 I Receive Clock for Framer 2.

D10 RCLK3 I Receive Clock for Framer 3.

B9 RCLK4 I Receive Clock for Framer 4.

M3 RCLK5 I Receive Clock for Framer 5.

V1 RCLK6 I Receive Clock for Framer 6.

W6 RCLK7 I Receive Clock for Framer 7.

J3 RCLK8 I Receive Clock for Framer 8.

T9 RCLK9 I Receive Clock for Framer 9.

W10 RCLK10 I Receive Clock for Framer 10.

Y18 RCLK11 I Receive Clock for Framer 11.
N17 RCLK12 I Receive Clock for Framer 12.

E18 RD* I Read Input.

D3 RMSYNC1 O Receive Multiframe Sync from Framer 1
G2 RMSYNC2 O Receive Multiframe Sync from Framer 2
D4 RMSYNC3 O Receive Multiframe Sync from Framer 3
D8 RMSYNC4 O Receive Multiframe Sync from Framer 4
N2 RMSYNC5 O Receive Multiframe Sync from Framer 5
V4 RMSYNC6 O Receive Multiframe Sync from Framer 6
V6 RMSYNC7 O Receive Multiframe Sync from Framer 7
K5 RMSYNC8 O Receive Multiframe Sync from Framer 8

U10 RMSYNC9 O Receive Multiframe Sync from Framer 9
Y11 RMSYNC10 O Receive Multiframe Sync from Framer 10

W19 RMSYNC11 O Receive Multiframe Sync from Framer 11

U20 RMSYNC12 O Receive Multiframe Sync from Framer 12

B2 RNEG1 I Receive Negative Data for Framer 1.
H2 RNEG2 I Receive Negative Data for Framer 2.
D9 RNEG3 I Receive Negative Data for Framer 3.
A9 RNEG4 I Receive Negative Data for Framer 4.

M2 RNEG5 I Receive Negative Data for Framer 5.

V3 RNEG6 I Receive Negative Data for Framer 6.
V7 RNEG7 I Receive Negative Data for Framer 7.
P3 RNEG8 I Receive Negative Data for Framer 8.
U9 RNEG9 I Receive Negative Data for Framer 9.

W11 RNEG10 I Receive Negative Data for Framer 10.
W17 RNEG11 I Receive Negative Data for Framer 11.

T20 RNEG12 I Receive Negative Data for Framer 12.

A1 RPOS1 I Receive Positive Data for Framer 1.
H1 RPOS2 I Receive Positive Data for Framer 2.
H4 RPOS3 I Receive Positive Data for Framer 3.
C9 RPOS4 I Receive Positive Data for Framer 4.

M1 RPOS5 I Receive Positive Data for Framer 5.

W2 RPOS6 I Receive Positive Data for Framer 6.

V5 RPOS7 I Receive Positive Data for Framer 7.

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Lead Symbols I/O Description

P4 RPOS8 I Receive Positive Data for Framer 8.

T10 RPOS9 I Receive Positive Data for Framer 9.
V11 RPOS10 I Receive Positive Data for Framer 10.
Y19 RPOS11 I Receive Positive Data for Framer 11.
R19 RPOS12 I Receive Positive Data for Framer 12.

C1 RSER1 O Receive Serial Data from Framer 1.
H3 RSER2 O Receive Serial Data from Framer 2.
C6 RSER3 O Receive Serial Data from Framer 3.
C8 RSER4 O Receive Serial Data from Framer 4.
P1 RSER5 O Receive Serial Data from Framer 5.

W4 RSER6 O Receive Serial Data from Framer 6.

T7 RSER7 O Receive Serial Data from Framer 7.

N4 RSER8 O Receive Serial Data from Framer 8.
U11 RSER9 O Receive Serial Data from Framer 9.
Y12 RSER10 O Receive Serial Data from Framer 10.
V16 RSER11 O Receive Serial Data from Framer 11.

T16 RSER12 O Receive Serial Data from Framer 12.

B1 RSYNC1 I/O Receive Frame/Multiframe Sync for Framer 1.

G1 RSYNC2 I/O Receive Frame/Multiframe Sync for Framer 2.

D6 RSYNC3 I/O Receive Frame/Multiframe Sync for Framer 3.

A7 RSYNC4 I/O Receive Frame/Multiframe Sync for Framer 4.

N3 RSYNC5 I/O Receive Frame/Multiframe Sync for Framer 5.

Y2 RSYNC6 I/O Receive Frame/Multiframe Sync for Framer 6.

U5 RSYNC7 I/O Receive Frame/Multiframe Sync for Framer 7.

J4 RSYNC8 I/O Receive Frame/Multiframe Sync for Framer 8.

T11 RSYNC9 I/O Receive Frame/Multiframe Sync for Framer 9.
V13 RSYNC10 I/O Receive Frame/Multiframe Sync for Framer 10.
V15 RSYNC11 I/O Receive Frame/Multiframe Sync for Framer 11.

P18 RSYNC12 I/O Receive Frame/Multiframe Sync for Framer 12.

B5 RSYSCLK1 I Receive System Clock for Framer 1.
E2 RSYSCLK2 I Receive System Clock for Framer 2.
E5 RSYSCLK3 I Receive System Clock for Framer 3.
B8 RSYSCLK4 I Receive System Clock for Framer 4.

M4 RSYSCLK5 I Receive System Clock for Framer 5.

T2 RSYSCLK6 I Receive System Clock for Framer 6.
Y5 RSYSCLK7 I Receive System Clock for Framer 7.

W3 RSYSCLK8 I Receive System Clock for Framer 8.

T4 RSYSCLK9 I Receive System Clock for Framer 9.

Y9 RSYSCLK10 I Receive System Clock for Framer 10.
U12 RSYSCLK11 I Receive System Clock for Framer 11.
R17 RSYSCLK12 I Receive System Clock for Framer 12.

D1 TCLK1 I Transmit Clock for Framer 1.

H5 TCLK2 I Transmit Clock for Framer 2.

C5 TCLK3 I Transmit Clock for Framer 3.

A5 TCLK4 I Transmit Clock for Framer 4.

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Lead Symbols I/O Description

R1 TCLK5 I Transmit Clock for Framer 5.

Y3 TCLK6 I Transmit Clock for Framer 6.

T6 TCLK7 I Transmit Clock for Framer 7.

K2 TCLK8 I Transmit Clock for Framer 8.
U13 TCLK9 I Transmit Clock for Framer 9.
Y13 TCLK10 I Transmit Clock for Framer 10.

T18 TCLK11 I Transmit Clock for Framer 11.
P16 TCLK12 I Transmit Clock for Framer 12.

A13 TEST I Tri-State. 0 = do not tri-state / 1 = tri-state all outputs & I/O

signals

C3 TNEG1 O Transmit Negative Data from Framer 1.

J1 TNEG2 O Transmit Negative Data from Framer 2.

F5 TNEG3 O Transmit Negative Data from Framer 3.
A10 TNEG4 O Transmit Negative Data from Framer 4.

L1 TNEG5 O Transmit Negative Data from Framer 5.

V2 TNEG6 O Transmit Negative Data from Framer 6.

V8 TNEG7 O Transmit Negative Data from Framer 7.

P5 TNEG8 O Transmit Negative Data from Framer 8.
U14 TNEG9 O Transmit Negative Data from Framer 9.
V12 TNEG10 O Transmit Negative Data from Framer 10.

W18 TNEG11 O Transmit Negative Data from Framer 11.

T19 TNEG12 O Transmit Negative Data from Framer 12.

B3 TPOS1 O Transmit Positive Data from Framer 1.

J2 TPOS2 O Transmit Positive Data from Framer 2.
J5 TPOS3 O Transmit Positive Data from Framer 3.

B10 TPOS4 O Transmit Positive Data from Framer 4.

L2 TPOS5 O Transmit Positive Data from Framer 5.

W1 TPOS6 O Transmit Positive Data from Framer 6.
W7 TPOS7 O Transmit Positive Data from Framer 7.

R3 TPOS8 O Transmit Positive Data from Framer 8.

T14 TPOS9 O Transmit Positive Data from Framer 9.
Y10 TPOS10 O Transmit Positive Data from Framer 10.
V18 TPOS11 O Transmit Positive Data from Framer 11.
V20 TPOS12 O Transmit Positive Data from Framer 12.

B4 TSER1 I Transmit Serial Data for Framer 1.
E1 TSER2 I Transmit Serial Data for Framer 2.
F3 TSER3 I Transmit Serial Data for Framer 3.
D7 TSER4 I Transmit Serial Data for Framer 4.
L5 TSER5 I Transmit Serial Data for Framer 5.
T1 TSER6 I Transmit Serial Data for Framer 6.
Y6 TSER7 I Transmit Serial Data for Framer 7.
T3 TSER8 I Transmit Serial Data for Framer 8.

M16 TSER9 I Transmit Serial Data for Framer 9.

W9 TSER10 I Transmit Serial Data for Framer 10.

W16 TSER11 I Transmit Serial Data for Framer 11.

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Lead Symbols I/O Description

W20 TSER12 I Transmit Serial Data for Framer 12.

A3 TSSYNC1 I Transmit System Sync for Framer 1.
F2 TSSYNC2 I Transmit System Sync for Framer 2.
G5 TSSYNC3 I Transmit System Sync for Framer 3.
E8 TSSYNC4 I Transmit System Sync for Framer 4.
L4 TSSYNC5 I Transmit System Sync for Framer 5.
U1 TSSYNC6 I Transmit System Sync for Framer 6.
Y7 TSSYNC7 I Transmit System Sync for Framer 7.

R4 TSSYNC8 I Transmit System Sync for Framer 8.
T15 TSSYNC9 I Transmit System Sync for Framer 9.
W8 TSSYNC10 I Transmit System Sync for Framer 10.

Y17 TSSYNC11 I Transmit System Sync for Framer 11.
U19 TSSYNC12 I Transmit System Sync for Framer 12.

E3 TSYNC1 I/O Transmit Sync for Framer 1.

F4 TSYNC2 I/O Transmit Sync for Framer 2.

E7 TSYNC3 I/O Transmit Sync for Framer 3.

A4 TSYNC4 I/O Transmit Sync for Framer 4.

R2 TSYNC5 I/O Transmit Sync for Framer 5.
W5 TSYNC6 I/O Transmit Sync for Framer 6.

T5 TSYNC7 I/O Transmit Sync for Framer 7.

M5 TSYNC8 I/O Transmit Sync for Framer 8.

T13 TSYNC9 I/O Transmit Sync for Framer 9.

W13 TSYNC10 I/O Transmit Sync for Framer 10.

U16 TSYNC11 I/O Transmit Sync for Framer 11.
N16 TSYNC12 I/O Transmit Sync for Framer 12.

C4 TSYSCLK1 I Transmit System Clock for Framer 1.

F1 TSYSCLK2 I Transmit System Clock for Framer 2.

G4 TSYSCLK3 I Transmit System Clock for Framer 3.

C10 TSYSCLK4 I Transmit System Clock for Framer 4.

L3 TSYSCLK5 I Transmit System Clock for Framer 5.

U2 TSYSCLK6 I Transmit System Clock for Framer 6.

V9 TSYSCLK7 I Transmit System Clock for Framer 7.

R5 TSYSCLK8 I Transmit System Clock for Framer 8.

U15 TSYSCLK9 I Transmit System Clock for Framer 9.
V10 TSYSCLK10 I Transmit System Clock for Framer 10.
U18 TSYSCLK11 I Transmit System Clock for Framer 11.
R18 TSYSCLK12 I Transmit System Clock for Framer 12.
Y16 WR* I Write Input.
A11 NC – No Connect
A12 NC – No Connect
A14 NC – No Connect
A15 NC – No Connect
A16 NC – No Connect
A17 NC – No Connect
A18 NC – No Connect

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Lead Symbols I/O Description

A19 NC – No Connect
A20 NC – No Connect

A8 NC – No Connect

B11 NC – No Connect
B12 NC – No Connect
B13 NC – No Connect
B14 NC – No Connect
B15 NC – No Connect
B16 NC – No Connect
B17 NC – No Connect
B18 NC – No Connect
B19 NC – No Connect
B20 NC – No Connect

B6 NC – No Connect

B7 NC – No Connect

C11 NC – No Connect
C12 NC – No Connect
C13 NC – No Connect
C14 NC – No Connect
C15 NC – No Connect
C16 NC – No Connect
C17 NC – No Connect
C18 NC – No Connect
C19 NC – No Connect

C2 NC – No Connect

C20 NC – No Connect
D11 NC – No Connect
D12 NC – No Connect
D13 NC – No Connect
D14 NC – No Connect
D15 NC – No Connect
D16 NC – No Connect
D17 NC – No Connect
D18 NC – No Connect
D19 NC – No Connect
D20 NC – No Connect

E10 NC – No Connect
E11 NC – No Connect
E12 NC – No Connect
E13 NC – No Connect
E14 NC – No Connect
E15 NC – No Connect
E16 NC – No Connect
E17 NC – No Connect
E19 NC – No Connect

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Lead Symbols I/O Description

E20 NC – No Connect

E6 NC – No Connect
F16 NC – No Connect
F17 NC – No Connect
F18 NC – No Connect
F19 NC – No Connect
F20 NC – No Connect

G3 NC – No Connect

H16 NC – No Connect

J16 NC – No Connect
J17 NC – No Connect
J18 NC – No Connect
J19 NC – No Connect

J20 NC – No Connect
K16 NC – No Connect
K17 NC – No Connect
K18 NC – No Connect
K19 NC – No Connect
K20 NC – No Connect

N1 NC – No Connect
N18 NC – No Connect
N19 NC – No Connect
N20 NC – No Connect

N5 NC – No Connect

P19 NC – No Connect
P20 NC – No Connect

R20 NC – No Connect

T17 NC – No Connect

U17 NC – No Connect

U6 NC – No Connect
V14 NC – No Connect
V17 NC – No Connect

W12 NC – No Connect

Y1 NC – No Connect

Y8 NC – No Connect

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DS21FT40 PCB Land Pattern Figure 2-1

The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same
pattern that would be seen as viewed through the MCM from the top.

1234567891011121314151617181920

A

rpos1rclk1ts

sync1

tsync4tclk4dvss1rsync4nc rneg4tneg4nc nc test ns ns nc nc nc nc nc

B

rsync1rneg1tpos1tser1rsys

clk

1

nc nc rsys

clk

4

rclk4tpos4nc nc nc nc nc nc nc nc nc nc

C

rser1nc tneg1tsys

clk

1

tclk3rser3dvdd1rser4 rpos4tsys

clk

4

nc nc nc nc ns nc nc nc nc nc

D

tclk1dvdd1rm

sync

1

rm

sync

3

dvss1rsync3tser4rm

sync4

rneg3rclk3nc nc nc nc nc nc nc nc nc nc

E

tser2rsys

clk

2

tsync1dvdd1rsys

clk

3

nc tsync3ts

sync

4

dvss1nc nc nc nc nc nc nc nc rd* nc nc

F

tsys

clk

2

ts

sync

2

tser3tsync2tneg

3

nc nc nc nc nc

G

rsync2rm

sync

2

nc tsys

clk

3

ts

sync

3

int* A6 A4 A2 A0

H

rpos2rneg2rser2rpos3tclk

2

nc A7 A5 A3 A1

J

tneg2tpos2rclk8rsync8tpos

3

nc nc nc nc nc

K

rclk2tclk8dvdd2dvss2rm

sync

8

nc nc nc nc nc

L

tneg5tpos5tsys

clk

5

ts

sync

5

tser

5

dvdd3D6 D4 D2 D0

M

rpos5rneg5rclk5rsys

clk

5

tsync

8

tser9D7 D5 D3 D1

N

nc rm

sync

5

rsync5rser8nc tsync12rclk12nc nc nc

P

rser5dvdd2rneg8rpos8tneg

8

tclk12mux rsync12nc nc

R

tclk5tsync5tpos8ts

sync

8

tsys

clk

8

dvss3rsys

clk

12

tsys
clk
12

rpos12nc

T

tser6rsys

clk

6

tser8rsys

clk

9

tsync7tclk7rser7cs1* rclk9rpos9rsync9dvdd3tsync9tpos9ts

sync

9

rser12nc tclk11tneg12rneg

12

U

ts

sync

6

tsys

clk

6

dvss2dvss3rsync7nc dvdd2dvss2rneg9rm

sync

9

rser9rsys

clk

11

tclk9tneg9tsys

clk

9

tsync11nc tsys

clk
11

ts

sync

12

rm

sync

12

V

rclk6tneg6rneg6rm

sync

6

rpos7rm

sync

7

rneg7tneg7tsys

clk

7

tsys

clk
10

rpos10tneg10rsync10nc rsync11rser11nc tpos11dvdd3tpos

12

W

tpos6rpos6rsys

clk

8

rser6tsync6rclk7tpos7ts

sync

10

tser10rclk10rneg10nc tsync10fs1 bts tser11rneg11tneg11rm

sync

11

tser

12

Y

nc rsync6tclk6cs2* rsys

clk

7

tser7ts

sync

7

nc rsys

clk

10

tpos10rm

sync

10

rser10tclk10fs0 cs3* wr* ts

sync

11

rclk11rpos11dvss

3

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2. DS21FT44 PIN FUNCTION DESCRIPTION
TRANSMIT SIDE PINS

Signal Name: TCLK
Signal Description: Transmit Clock
Signal Type: Input
A 2.048 MHz primary clock. Used to clock data through the transmit side formatter.

Signal Name: TSER
Signal Description: Transmit Serial Data
Signal Type: Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.

Signal Name: TSYSCLK
Signal Description: Transmit System Clock
Signal Type: Input

1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.
Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up
to 8.192 MHz.

Signal Name: TSYNC
Signal Description: Transmit Sync
Signal Type: Input /Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. This pin can
also be programmed to output either a frame or multiframe pulse. Always synchronous with TCLK.

Signal Name: TSSYNC
Signal Description: Transmit System Sync
Signal Type: Input
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit side elastic store. Always synchronous with TSYSCLK.

Signal Name: TPOS
Signal Description: Transmit Positive Data Output
Signal Type: Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (TCR1.7) control bit.

Signal Name: TNEG
Signal Description: Transmit Negative Data Output
Signal Type: Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter.

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RECEIVE SIDE PINS

Signal Name: RCLK
Signal Description: Receive Clock Input
Signal Type: Input

2.048 MHz clock that is used to clock data through the receive side framer.

Signal Name: RSER
Signal Description: Receive Serial Data
Signal Type: Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.

Signal Name: RSYNC
Signal Description: Receive Sync
Signal Type: Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC
multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.

Signal Name: RMSYNC
Signal Description: Receive Multiframe Sync
Signal Type: Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If
the receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK.

Signal Name: RSYSCLK
Signal Description: Receive System Clock
Signal Type: Input

1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied
low in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz.

Signal Name: RPOS
Signal Description: Receive Positive Data Input
Signal Type: Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.

Signal Name: RNEG
Signal Description: Receive Negative Data Input
Signal Type: Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.

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PARALLEL CONTROL PORT PINS

Signal Name: INT*
Signal Description: Interrupt
Signal Type: Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the FDL Status Register. Active low, open drain output.

Signal Name: MUX
Signal Description: Bus Operation
Signal Type: Input
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.

Signal Name: D0 TO D7 / AD0 TO AD7
Signal Description: Data Bus or Address/Data Bus
Signal Type: Input /Output
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as a 8–bit multiplexed address / data bus.

Signal Name: A0 TO A5, A7
Signal Description: Address Bus
Signal Type: Input
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.

Signal Name: ALE (AS) / A6
Signal Description: Address Latch Enable (Address Strobe) or A6
Signal Type: Input
In non–multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive–going edge.

Signal Name: BTS
Signal Description: Bus Type Select
Signal Type: Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().

Signal Name: RD* (DS)
Signal Description: Read Input (Data Strobe)
Signal Type: Input
RD* is an active low signal and DS is an active high signal.

Signal Name: FS0 AND FS1
Signal Description: Framer Selects
Signal Type: Input
Selects which of the four framers is to be accessed for a specific DS21Q44 die.

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Signal Name: CS1* TO CS3*
Signal Description: Chip Select
Signal Type: Input
Must be low to read or write to a specific DS21Q44 die. These are active low signals.

Signal Name: WR* (R/W*)
Signal Description: Write Input (Read/Write)
Signal Type: Input
WR* is an active low signal.

TEST ACCESS PORT PINS

Signal Name: TEST
Signal Description: 3–State Control
Signal Type: Input
Set high to 3–state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board level testing.

SUPPLY PINS

Signal Name: VDD
Signal Description: Positive Supply
Signal Type: Supply

2.97 to 3.63 volts.

Signal Name: VSS
Signal Description: Signal Ground
Signal Type: Supply

0.0 volts.

3. DS21FT40 REGISTER MAP
Register Map for Each Quad Framer Sorted by Address Table 3-1

ADDRESS R/W REGISTER NAME REGISTER

ABBREVIATION

00 R BPV or Code Violation Count 1 VCR1
01 R BPV or Code Violation Count 2 VCR2
02 R CRC4 Error Count 1 / FAS Error Count 1 CRCCR1
03 R CRC4 Error Count 2 CRCCR2
04 R E-Bit Count 1 / FAS Error Count 2 EBCR1
05 R E-Bit Count 2 EBCR2
06 R/W Status 1 SR1
07 R/W Status 2 SR2
08 R/W Receive Information RIR

09 R/W Test 2 TEST2 (set to 00h)
0A – Not used (set to 00H)
0B – Not used (set to 00H)
0C – Not used (set to 00H)

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ADDRESS R/W REGISTER NAME REGISTER

ABBREVIATION

0D – Not used (set to 00H)
0E – Not used (set to 00H)

0F R Device ID IDR

10 R/W Receive Control 1 RCR1

11 R/W Receive Control 2 RCR2

12 R/W Transmit Control 1 TCR1

13 R/W Transmit Control 2 TCR2

14 R/W Common Control 1 CCR1

15 R/W Test 1 TEST1 (set to 00h)

16 R/W Interrupt Mask 1 IMR1

17 R/W Interrupt Mask 2 IMR2

18 – Not used (set to 00H)

19 – Not used (set to 00H)
1A R/W Common Control 2 CCR2
1B R/W Common Control 3 CCR3
1C R/W Transmit Sa Bit Control TSaCR
1D R/W Common Control 6 CCR6
1E R Synchronizer Status SSR

1F R Receive Non-Align Frame RNAF

20 R/W Transmit Align Frame TAF

21 R/W Transmit Non-Align Frame TNAF

22 R/W Transmit Channel Blocking 1

(Not applicable to DS21FT40 – write to
00H.)

TCBR1

23 R/W Transmit Channel Blocking 2

(Not applicable to DS21FT40 – write to
00H.)

TCBR2

24 R/W Transmit Channel Blocking 3

(Not applicable to DS21FT40 – write to
00H.)

TCBR3

25 R/W Transmit Channel Blocking 4

(Not applicable to DS21FT40 – write to
00H.)

TCBR4

26 R/W Transmit Idle 1 TIR1

27 R/W Transmit Idle 2 TIR2

28 R/W Transmit Idle 3 TIR3

29 R/W Transmit Idle 4 TIR4
2A R/W Transmit Idle Definition TIDR
2B R/W Receive Channel Blocking 1 RCBR1
2C R/W Receive Channel Blocking 2 RCBR2
2D R/W Receive Channel Blocking 3 RCBR3
2E R/W Receive Channel Blocking 4 RCBR4

2F R Receive Align Frame RAF

30 R Receive Signaling 1 RS1

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ADDRESS R/W REGISTER NAME REGISTER

ABBREVIATION

31 R Receive Signaling 2 RS2

32 R Receive Signaling 3 RS3

33 R Receive Signaling 4 RS4

34 R Receive Signaling 5 RS5

35 R Receive Signaling 6 RS6

36 R Receive Signaling 7 RS7

37 R Receive Signaling 8 RS8

38 R Receive Signaling 9 RS9

39 R Receive Signaling 10 RS10
3A R Receive Signaling 11 RS11
3B R Receive Signaling 12 RS12
3C R Receive Signaling 13 RS13
3D R Receive Signaling 14 RS14
3E R Receive Signaling 15 RS15

3F R Receive Signaling 16 RS16

40 R/W Transmit Signaling 1 TS1

41 R/W Transmit Signaling 2 TS2

42 R/W Transmit Signaling 3 TS3

43 R/W Transmit Signaling 4 TS4

44 R/W Transmit Signaling 5 TS5

45 R/W Transmit Signaling 6 TS6

46 R/W Transmit Signaling 7 TS7

47 R/W Transmit Signaling 8 TS8

48 R/W Transmit Signaling 9 TS9

49 R/W Transmit Signaling 10 TS10
4A R/W Transmit Signaling 11 TS11
4B R/W Transmit Signaling 12 TS12
4C R/W Transmit Signaling 13 TS13
4D R/W Transmit Signaling 14 TS14
4E R/W Transmit Signaling 15 TS15

4F R/W Transmit Signaling 16 TS16

50 R/W Transmit Si Bits Align Frame TSiAF

51 R/W Transmit Si Bits Non-Align Frame TSiNAF

52 R/W Transmit Remote Alarm Bits TRA

53 R/W Transmit Sa4 Bits TSa4

54 R/W Transmit Sa5 Bits TSa5

55 R/W Transmit Sa6 Bits TSa6

56 R/W Transmit Sa7 Bits TSa7

57 R/W Transmit Sa8 Bits TSa8

58 R Receive Si bits Align Frame RSiAF

59 R Receive Si bits Non-Align Frame RSiNAF
5A R Receive Remote Alarm Bits RRA
5B R Receive Sa4 Bits RSa4
5C R Receive Sa5 Bits RSa5

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ADDRESS R/W REGISTER NAME REGISTER

ABBREVIATION

5D R Receive Sa6 Bits RSa6
5E R Receive Sa7 Bits RSa7

5F R Receive Sa8 Bits RSa8

60 R/W Transmit Channel 1 TC1

61 R/W Transmit Channel 2 TC2

62 R/W Transmit Channel 3 TC3

63 R/W Transmit Channel 4 TC4

64 R/W Transmit Channel 5 TC5

65 R/W Transmit Channel 6 TC6

66 R/W Transmit Channel 7 TC7

67 R/W Transmit Channel 8 TC8

68 R/W Transmit Channel 9 TC9

69 R/W Transmit Channel 10 TC10
6A R/W Transmit Channel 11 TC11
6B R/W Transmit Channel 12 TC12
6C R/W Transmit Channel 13 TC13
6D R/W Transmit Channel 14 TC14
6E R/W Transmit Channel 15 TC15

6F R/W Transmit Channel 16 TC16

70 R/W Transmit Channel 17 TC17

71 R/W Transmit Channel 18 TC18

72 R/W Transmit Channel 19 TC19

73 R/W Transmit Channel 20 TC20

74 R/W Transmit Channel 21 TC21

75 R/W Transmit Channel 22 TC22

76 R/W Transmit Channel 23 TC23

77 R/W Transmit Channel 24 TC24

78 R/W Transmit Channel 25 TC25

79 R/W Transmit Channel 26 TC26
7A R/W Transmit Channel 27 TC27
7B R/W Transmit Channel 28 TC28
7C R/W Transmit Channel 29 TC29
7D R/W Transmit Channel 30 TC30
7E R/W Transmit Channel 31 TC31

7F R/W Transmit Channel 32 TC32

80 R/W Receive Channel 1 RC1

81 R/W Receive Channel 2 RC2

82 R/W Receive Channel 3 RC3

83 R/W Receive Channel 4 RC4

84 R/W Receive Channel 5 RC5

85 R/W Receive Channel 6 RC6

86 R/W Receive Channel 7 RC7

87 R/W Receive Channel 8 RC8

88 R/W Receive Channel 9 RC9

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ADDRESS R/W REGISTER NAME REGISTER

ABBREVIATION

89 R/W Receive Channel 10 RC10
8A R/W Receive Channel 11 RC11
8B R/W Receive Channel 12 RC12
8C R/W Receive Channel 13 RC13
8D R/W Receive Channel 14 RC14
8E R/W Receive Channel 15 RC15

8F R/W Receive Channel 16 RC16

90 R/W Receive Channel 17 RC17

91 R/W Receive Channel 18 RC18

92 R/W Receive Channel 19 RC19

93 R/W Receive Channel 20 RC20

94 R/W Receive Channel 21 RC21

95 R/W Receive Channel 22 RC22

96 R/W Receive Channel 23 RC23

97 R/W Receive Channel 24 RC24

98 R/W Receive Channel 25 RC25

99 R/W Receive Channel 26 RC26
9A R/W Receive Channel 27 RC27
9B R/W Receive Channel 28 RC28
9C R/W Receive Channel 29 RC29
9D R/W Receive Channel 30 RC30
9E R/W Receive Channel 31 RC31

9F R/W Receive Channel 32 RC32
A0 R/W Transmit Channel Control 1 TCC1
A1 R/W Transmit Channel Control 2 TCC2
A2 R/W Transmit Channel Control 3 TCC3
A3 R/W Transmit Channel Control 4 TCC4
A4 R/W Receive Channel Control 1 RCC1
A5 R/W Receive Channel Control 2 RCC2
A6 R/W Receive Channel Control 3 RCC3
A7 R/W Receive Channel Control 4 RCC4
A8 R/W Common Control 4 CCR4
A9 R Transmit DS0 Monitor TDS0M

AA R/W Common Control 5 CCR5
AB R Receive DS0 Monitor RDS0M
AC R/W Test 3 TEST3 (set to 00H)
AD – Not used (set to 00H)
AE – Not used (set to 00H)
AF – Not used (set to 00H)

B0 R/W HDLC Control Register HCR
B1 R/W HDLC Status Register HSR
B2 R/W HDLC Interrupt Mask Register HIMR
B3 R/W Receive HDLC Information Register RHIR
B4 R/W Receive HDLC FIFO Register RHFR

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ADDRESS R/W REGISTER NAME REGISTER

ABBREVIATION

B5 R/W Interleave Bus Operation Register IBO
B6 R/W Transmit HDLC Information Register THIR
B7 R/W Transmit HDLC FIFO Register THFR
B8 R/W Receive HDLC DS0 Control Register 1 RDC1
B9 R/W Receive HDLC DS0 Control Register 2 RDC2

BA R/W Transmit HDLC DS0 Control Register 1 TDC1
BB R/W Transmit HDLC DS0 Control Register 2 TDC2
BC – Not used (set to 00H)
BD – Not used (set to 00H)
BE – Not used (set to 00H)

BF – Not used (set to 00H)

NOTES:

1. Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all

zeros) on power– up initialization to insure proper operation.

2. Register banks CxH, DxH, ExH, and FxH are not accessible.

4. PARALLEL PORT

The DS21FT40 is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS21FT40 can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 17 for more details.

5. CONTROL, ID AND TEST REGISTERS

The operation of each framer within the DS21FT40 is configured via a set of ten control registers.
Typically, the control registers are only accessed when the system is first powered up. Once a channel in
the DS21FT40 has been initialized, the control registers will only need to be accessed when there is a
change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and six Common Control Registers (CCR1 to CCR6).
Each of the ten registers are described in this section.

There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a one indicating that the DS21Q44 die is present. The lower 4 bits of the IDR are used to display
the die revision of the chip.

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Power–Up Sequence

The DS21FT40 does not automatically clear its register space on power–up. After the supplies are stable,
each of the four framer’s register space should be configured for operation by writing to all of the internal
registers. This includes setting the Test and all unused registers to 00Hex.

This can be accomplished using a two-pass approach on each quad framer within the DS21FT40.

1. Clear each quad framer’s register space by writing 00H to addresses 00H through 0BFH.

2. Program required registers to achieve desired operating mode.

Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero
to a one (this step can be skipped if the elastic stores are disabled).

IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)

(MSB) (LSB)

T1E1 0 0 0 ID3 ID2 ID1 ID0

SYMBOLS POSITION NAME AND DESCRIPTION

T1E1 IDR.7 T1 or E1 Chip Determination Bit.

0=T1 chip
1=E1 chip

ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents

the chip revision.
ID2 IDR.1 Chip Revision Bit 2.
ID1 IDR.2 Chip Revision Bit 1.
ID0 IDR.0 Chip Revision Bit 0. LSB of a decimal code that represents

the chip revision.

RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)

(MSB) (LSB)

RSMF RSM RSIO – – FRC SYNCE RESYNC

SYMBOLS POSITION NAME AND DESCRIPTION

RSMF RCR1.7 RSYNC Multiframe Function. Only used if the RSYNC pin

is programmed in the multiframe mode (RCR1.6=1).

0 = RSYNC outputs CAS multiframe boundaries

1 = RSYNC outputs CRC4 multiframe boundaries

RSM RCR1.6 RSYNC Mode Select.

0 = frame mode (see the timing in Section 18)

1 = multiframe mode (see the timing in Section 18)

RSIO RCR1.5 RSYNC I/O Select. (note: this bit must be set to zero when

RCR2.1=0).

0 = RSYNC is an output (depends on RCR1.6)

1 = RSYNC is an input (only valid if elastic store enabled)

– RCR1.4 Not Assigned. Should be set to zero when written.
– RCR1.3 Not Assigned. Should be set to zero when written.

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SYMBOLS POSITION NAME AND DESCRIPTION

FRC RCR1.2 Frame Resync Criteria.

0 = resync if FAS received in error 3 consecutive times

1 = resync if FAS or bit 2 of non–FAS is received in error 3

consecutive times

SYNCE RCR1.1 Sync Enable.

0 = auto resync enabled

1 = auto resync disabled

RESYNC RCR1.0 Resync. When toggled from low to high, a resync is initiated.

Must be cleared and set again for a subsequent resync.

SYNC/RESYNC CRITERIA Table 5–1

FRAME OR

MULTIFRAME

LEVEL

SYNC CRITERIA RESYNC CRITERIA ITU SPEC.

FAS FAS present in frame N and

N + 2, and FAS not present
in frame N + 1

Three consecutive incorrect
FAS received

Alternate (RCR1.2=1) the
above criteria is met or
three consecutive incorrect
bit 2 of non–FAS received

G.706

4.1.1

4.1.2

CRC4 Two valid MF alignment

words found within 8 ms

915 or more CRC4 code
words out of 1000 received
in error

G.706

4.2 and 4.3.2

CAS Valid MF alignment word

found and previous timeslot
16 contains code other than
all zeros

Two consecutive MF
alignment words received
in error

G.732 5.2

RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S RBCS RESE –

SYMBOLS POSITION NAME AND DESCRIPTION

Sa8S RCR2.7 Sa8 Bit Select. Not applicable for DS21FT40.
Sa7S RCR2.6 Sa7 Bit Select. Not applicable for DS21FT40.
Sa6S RCR2.5 Sa6 Bit Select. Not applicable for DS21FT40.
Sa5S RCR2.4 Sa5 Bit Select. Not applicable for DS21FT40.
Sa4S RCR2.3 Sa4 Bit Select. Not applicable for DS21FT40.

DS21FT40

27 of 87

SYMBOLS POSITION NAME AND DESCRIPTION

RBCS RCR2.2 Receive Side Backplane Clock Select.

0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz

RESE RCR2.1 Receive Side Elastic Store Enable.

0 = elastic store is bypassed
1 = elastic store is enabled

– RCR2.0 Not Assigned. Should be set to zero when written.

TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)

(MSB) (L SB)

ODF TFPT T16S TUA1 TSiS TSA1 TSM TSIO

SYMBOLS POSITION NAME AND DESCRIPTION

ODF TCR1.7 Output Data Format.

0 = bipolar data at TPOS and TNEG

1 = NRZ data at TPOS; TNEG=0

TFPT TCR1.6 Transmit Timeslot 0 Pass Through.

0 = FAS bits/Sa bits/Remote Alarm sourced internally from

the TAF and TNAF registers

1 = FAS bits/Sa bits/Remote Alarm sourced from TSER

T16S TCR1.5 Transmit Timeslot 16 Data Select.

0 = sample timeslot 16 at TSER pin

1 = source timeslot 16 from TS0 to TS15 registers

TUA1 TCR1.4 Transmit Unframed All Ones.

0 = transmit data normally

1 = transmit an unframed all one’s code at TPOS and TNEG

TSiS TCR1.3 Transmit International Bit Select.

0 = sample Si bits at TSER pin

1 = source Si bits from TAF and TNAF registers (in this

mode, TCR1.6 must be set to 0)

TSA1 TCR1.2 Transmit Signaling All Ones.

0 = normal operation

1 = force timeslot 16 in every frame to all ones

TSM CR1.1 TSYNC Mode Select.

0 = frame mode (see the timing in Section 16)

1 = CAS and CRC4 multiframe mode (see the timing in

Section 16)

TSIO TCR1.0 TSYNC I/O Select.

0 = TSYNC is an input

1 = TSYNC is an output

NOTE:

See Figure 16–15 for more details about how the Transmit Control Registers affect the operation of the
DS21FT40.