Dallas Semiconductor DS2186SN, DS2186S, DS2186N, DS2186 Datasheet
DS2186
Transmit Line Interface
DS2186
022798 1/11
FEATURES
• Line interface for T1 (1.544 MHz) and CEPT (2.048
MHz) primary rate networks
• On–chip transmit LBO (line build out) and line drivers
eliminate external components
• Programmable output pulse shape supports short–
and long–loop applications
• Supports bipolar and unipolar input data formats
• Transparent B8ZS and HDB3 zero code suppression
modes
• Compatible with DS2180A T1 and DS2181A CEPT
Transceivers DS2141A T1 and DS2143 E1 Controllers
• Companion to the DS2187 Receive Line Interface
and DS2188 T1/CEPT Jitter Attenuator
• Single 5V supply; low–power CMOS technology
PIN ASSIGNMENT
LF
V
DD
V
SS
LF
20–PIN DIP (300 MIL)
TAIS
ZCSEN
TCLKSEL
LEN0
LEN1
LEN2
TTIP
TRING
LCLK
LPOS
LNEG
TCLK
TPOS
TNEG
LB
MTIP
MRING
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
ZCSEN
20–PIN SOIC (300 Mil)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LCLK
LPOS
LNEG
TCLK
TPOS
TNEG
LB
MTIP
MRING
TAIS
TCLKSEL
LEN0
LEN1
LEN2
VDD
TTIP
TRING
VSS
DESCRIPTION
The DS2186 T1/CEPT Transmit Line Interface Chip interfaces user equipment to North American (T1–1.544
MHz) and European (CEPT–2.048 MHz) primary rate
communications networks. The device is compatible
with all types of twisted pair and coax cable found in
such networks.
Key on–chip components include: programmable wave
shaping circuitry, line drivers, remote loopback, and
zero suppression logic. A line–coupling transformer is
the only external component required.
Short loop (DSX–1, 0 to 655 feet) and long loop (CSU; 0
dB, –7.5 dB and –15 dB) pulse templates found in T1
applications are supported. Appropriate CCITT recommendations are met in the CEPT mode.
Application areas include DACS, CSU, CPE, channel
banks, and PABX–to–computer interfaces such as DMI
and CPI. The DS2186 supports ISDN–PRI (Primary
Rate Interface) specifications.
RST
INT
CS
RAIS
LF
VDD
ZCSEN
LEN0
LEN1
LEN2
TCLKSEL
TAIS
TTIP
TRING
VSS
LCLK
LNEG
LPOS
TCLK
TPOS
TNEG
LB
MTIP
MRING
DS2186
DS2187
AVDD
LCAP
NC
ZCSEN
RCLKSEL
RTIP
RRING
LOCK
AVSS
DVDD
AIS
BPV
RCL
RPOS
RNEG
RCLK
DVSS
DS2180A/DS2181A
SYSTEM CONTROLLER (DS5000)
SYSTEM BACKPLANE
1.35:1
1:2
RPOS
RNEG
RCLK
TCLK
TPOS
TNEG
TSER
RSER
SCLK
SDO
SDI
RECEIVE
PAIR
TRANSMIT
PAIR
10 µF
0.47 µF
NONPOLARIZED
DS2186
022798 2/11
DS2186 BLOCK DIAGRAM Figure 1
ZERO CODE
SUPPRESSION
CIRCUITRY
WAVESHAPPING
CIRCUITRY
LINE
DRIVERS
INPUT
DATA
MUX
LINE DRIVER
MONITOR
LEN0 LEN1 LEN2ZCSEN
TTIP
TRING
MTIP
MRING
LF
VDD
VSS
LNEG
LPOS
LCLK
TNEG
TPOS
TCLK
LB
TAIS
TCLKSEL
SYSTEM LEVEL INTERCONNECT Figure 2
DS2186
022798 3/11
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
1 TAIS I Transmit Alarm Indication Signal. When high, output data is
forced to all ones at the TCLK (LB=0) or LCLK (LB=1) rate.
2 ZCSEN I Zero Code Suppression Enable. When high, B8ZS or HDB3
encoder enabled.
3 TCLKSEL I Transmit Clock Select. Tie to VSS for 1.544 MHz (T1) applica-
tions, to V
DD
for 2.048 MHz (CEPT) applications.
4
5
6
LEN0
LEN1
LEN2
I Length Select 0, 1 and 2. State determines output T1 waveform
shape and characteristics.
7 V
DD
– Positive Supply. 5.0 volts.
8
9
TTIP,
TRING
O Transmit Tip and Ring. Line driver outputs; connect to transmit
line transformer.
10 V
SS
– Signal Ground. 0.0 volts.
11 LF O Line Fault. Open collector active low output. Held low during an
output driver fault and/or failure; tri–stated otherwise.
12
13
MRING,
MTIP
I Monitor Tip and Ring. Normally connected to TTIP and TRING.
Sense inputs for line fault detection circuitry.
14 LB I Loopback. When high, input data is sampled at LPOS and LNEG
on falling edges of LCLK; when low, input data is sampled at TPOS
and TNEG on falling TCLK.
15
16
TNEG,
TPOS
I Transmit Data. Sampled on falling edges of TCLK when LB=0.
17 TCLK I T ransmit Clock. 1.544 MHz or 2.048 MHz primary data clock.
18
19
LNEG,
LPOS
I Loopback Data. Sampled on falling edges of LCLK when LB=1.
20 LCLK I Loopback Clock. 1.544 MHz or 2.048 MHz loopback data clock.
INPUT DATA MODES
Input data is sampled on the falling edge of TCLK or
LCLK and can be bipolar (dual rail) or unipolar (single
rail, NRZ). TPOS, TNEG and TCLK are the data and
clock inputs when LB=0, LPOS, LNEG and LCLK when
LB=1. TPOS and TNEG (LPOS and LNEG) must be tied
together in NRZ applications.
ZERO CODE SUPPRESSION MODES
Transmitted data is treated transparently (no zero code
suppression) when ZCSEN=0. HDB3 code words replace any all–zero nibble when ZCSEN=1 and
TCLKSEL=1. B8ZS code words replace any incoming
all–zero byte when ZCSEN=1 and TCLKSEL=0.
ALARM INDICATION SIGNAL
When TAIS is set, an all ones code is continuously
transmitted at the TCLK rate (LB=0) or the LCLK rate
(LB=1).
WAVE SHAPING
The device supports T1 short loop (DSX–1; 0 to 655
feet), T1 long loop (CSU; 0 dB, –7.5 dB and –15 dB) and
CEPT (CCITT G.703) pulse template requirements.
On–chip laser trimmed delay lines clocked by either
TCLK or LCLK control a precision digital–to–analog
converter to build the desired waveforms, which are
buffered differentially by the line drivers.
DS2186
022798 4/11
The shape of the “pre–emphasized” T1 waveform is
controlled by inputs LEN0, LEN1, and LEN2
(TCLKSEL=0). These control inputs allow the user to
select the appropriate output pulse shape to meet
DSX–1 or CSU templates over a wide variety of cable
types and lengths. Those cable types include ABAM,
PIC, and PULP.
The CEPT mode is enabled when TCLKSEL=1. Only
one output pulse shape is available in the CEPT mode;
inputs LEN0, LEN1 and LEN2 can be any state except
all zeros.
The line coupling transformer also contributes to the
pulse shape seen at the cross–connect point. Transformers for both T1 and CEPT applications must be
1:1.35.
The wave shaping circuitry does not contribute significantly to output jitter (less than 0.01 UIpp broadband).
Output jitter will be dominated by the jitter on TCLK or
LCLK. TCLK and LCLK need only be accurate in frequency, not duty cycle.
LINE DRIVERS
The on–chip differential line drivers interface directly to
the output transformer. To optimize device performance, length of the TTIP and TRING traces should be
minimized and isolated from neighboring interconnect.
FAULT PROTECTION
The line drivers are fault–protected and will withstand a
shorted transformer secondary (or primary) without
damage. Inputs MTIP and MRING are normally tied to
TTIP and TRING to provide fault monitoring capability.
Output LF
will transition low if 192 TCLK cycles occur
without a one occurring at MTIP or MRING. LF will tri–
state on the next one occurrence or two TCLK periods
later, whichever is greater.
The threshold of MTIP and MRING varies with the line
type selected at LEN0, LEN1 and LEN2. This insures
detection of the lowest level zero to one transition (–15
dB buildout) as it occurs on TTIP and TRING.
T1 LINE LENGTH SELECTION Table 2
LEN2 LEN1 LEN0 OPTION SELECTED APPLICATION
0 0 0 Test mode Do not use
0 0 1 –7.5 dB buildout T1 CSU
0 1 0 –15 dB buildout T1 CSU
0 1 1 0 dB buildout,
0 – 133 feet
T1 CSU, DSX–1 Cross connect
1 0 0 133 – 266 feet DSX–1 Cross connect
1 0 1 266 – 399 feet DSX–1 Cross connect
1 1 0 399 – 533 feet DSX–1 Cross connect
1 1 1 533 – 655 feet DSX–1 Cross connect
NOTE:
1. The LEN0, LEN1 and LEN2 inputs control T1 output waveshapes when TCLKSEL=0. The G.703 (CEPT) template
is selected when TCLKSEL=1 and LEN0, LEN1, and LEN2 are at any state except all zeros.
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