Dallas Semiconductor DS2182AQN, DS2182AQ, DS2182AN, DS2182A Datasheet
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FEATURES
§ Performs framing and monitoring functions
Supports Superframe and Extended Superframe formats
§ Four onboard error counters
– 16-bit bipolar violation
– 8-bit CRC
– 8-bit OOF
– 8-bit frame bit error
§ Indication of the following
– yellow and blue alarms
– incoming B8ZS code words
– 8 and 16 zero strings
– change of frame alignment
– loss of sync
– carrier loss
§ Simple serial interface used for config-
uration, control and status monitoring
§ Burst mode allows quick access to counters
for status updates
§ Automatic counter reset feature
§ Single 5V supply; low-power CMOS tech-
nology
§ Available in 28-pin DIP and 28-pin PLCC
§ The DS2182A is upward-compatible from
the original DS2182
The updated DS2182A includes the following
changes from the original DS2182:
§ Ability to count excessive zeros
§ Severely Errored Framing Event indication
§ Updated AIS detection
§ Updated RCL detection
§ AIS and RCL alarm clear indications
PIN ASSIGNMENT
DESCRIPTION
The DS2182A T1 Line Monitor Chip is a monolithic CMOS device designed to monitor real-time
performance on T1 lines. The DS2182A frames to the data on the line, counts errors, and supplies
detailed information about the status and condition of the line. Large on-board counters allow the
accumulation of errors for extended periods, which permits a single CPU to monitor a number of T1
lines. Output clocks that are synchronized to the incoming data stream are provided for easy extraction of
S-Bits, FDL bits, signaling bits, and channel data. The DS2182A meets the requirements of ANSI
T1.231.
DS2182A
T1 Line Monitor
www.dalsemi.com
INT 1 28 VDD
SDI 2 27 RLOS
SDO 3 26 RFER
CS 4 25 RBV
SCLK 5 24 RCL
NC 6 23 RNEG
RYEL 7 22 RPOS
RLINK 8 21 RST
RLCLK 9 20 TEST
RCLK 10 19 RSIGSEL
RCHCLK 11 18 RSIGFR
RSER 12 17 RABCD
NC 13 16 RMSYNC
VSS 14 15 RFSYNC
28-Pin DIP (600-mil)
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DS2182A BLOCK DIAGRAM Figure 1
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PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
6 NC - No Connect. No internal connection. This pin can be tied to either
VSS or VDD, or it can be floated.
7 RYEL O Receive Yellow Alarm. Transitions high when yellow alarm
detected; goes low when alarm clears.
8 RLINK O
Receive Link Data. Updated with extracted FDL data one RCLK
before start of odd frames (193E) and held until next update.
Updated with extracted S-bit data one RCLK before start of even
frames (193S) and held until next update.
9 RLCLK O Receive Link Clock. 4 kHz demand clock for RLINK.
10 RCLK I Receive Clock. 1.544 MHz primary clock.
11 RCHCLK O Receive Channel Clock. 192 kHz clock; identifies time slot
(channel) boundaries.
12 RSER O Receive Serial Data. Received NRZ serial data; updated on rising
edges of RCLK.
13 NC -
No Connect. No internal connection. This pin can be tied to either
V
SS
or VDD, or it can be floated.
15 RFSYNC O
Receive Frame Sync. Extracted 8 kHz clock, one RCLK wide; Fbit position in each frame.
16 RMSYNC O Receive Multiframe Sync. Extracted multiframe sync; positive-
going edge indicates start of multiframe; 50% duty cycle.
17 RABCD O Receive ABCD Signaling. Extracted signaling data output; valid
for each channel in signaling frames. In non-signaling frames,
RABCD outputs the LSB of each channel word.
18 ESIGFR O Receive Signaling Frame. High during signaling frames; low
during non-signaling frames (and during resync).
19 RSIGSEL O Receive Signaling Select. In 193E framing, a .667 kHz clock that
identifies signaling frames A and C; a 1.33 kHz clock in 193S.
21
RST
I
Reset. A high-low transition clears all internal registers and resets
counters. A high-low-high transition initiates a resync.
22
23
RPOS
RNEG
I
Receive Bipolar Data Inputs. Sampled on falling of RCLK. Tie
together to receive NRZ data and disable bipolar violation
monitoring circuitry.
24 RCL O Receive Carrier Loss. High if 192 consecutive 0s appear at RPOS
and RNEG; goes low upon seeing 12.5% one’s density.
25 RBV O Receive Bipolar Violation. High during accused bit time at RSER.
If bipolar violation detected, low otherwise.
26 RFER O Receive Frame Error. High during F-bit time when FT or FS
errors occur (193S), or when FPS or CRC errors occur (193E). Low
during resync.
27 RLOS O
Receive Loss of Sync. Indicates sync status; high when internal
resync is in progress, low otherwise.
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PIN DESCRIPTION Table 2
PIN SYMBOL TYPE DESCRIPTION
1
INT
O
Receive Alarm Interrupt. Flags host controller during alarm conditions.
Active low; open drain output.
2 SDI I Serial Data In. Data for onboard registers. Sampled on rising edge of SCLK.
3 SDO O
Serial Data Out. Control and status information from onboard registers.
Updated on falling edge of SCLK; tri-stated during serial port write or
when CS is high.
4
CS
I Chip Select. Must be low to read or write the serial port.
5 SCLK I Serial Data Clock. Used to read or write the serial port registers.
POWER AND TEST PIN DESCRIPTION Table 3
PIN SYMBOL TYPE DESCRIPTION
14 V
SS
- Signal Ground. 0.0 volts.
20 TEST I Test Mode. Tie to VSS for normal operation.
28 V
DD
- Positive Supply. 5.0 volts.
REGISTER SUMMARY Table 4
REGISTER ADDRESS DESCRIPTION/FUNCTION
BVCR2 0000 Bipolar Violation Count Register 2. LSW of a 16-bit presettable counter that
records individual bipolar violations.
BVCR1 0001
Bipolar Violation Count Register 1. MSW of a 16-bit presettable counter that
records individual bipolar violations.
CRCCR 0010 CRC Error Count Register. 8-bit presettable counter that records CRC6 errored
words in the 193E frame mode.
OOFCR 0011
OOF Count Register. 8-bit presettable counter that records OOF events. OOF
events are defined by RCR1.5 and RCR1.6.
FECR 0100 Frame Error Count Register. 8-bit presettable counter that records individual
bit errors in the framing pattern.
RSR1 0101 Receive Status Register 1. Reports alarm conditions.
RIMR1 0110 Receive Interrupt Mask Register 1. Allows masking of individual alarm-
generated interrupts from RSR1.
RSR2 0111 Receive Status Register 2. Reports alarm conditions.
RIMR2 1000
Receive Interrupt Mask Register 2. Allows masking of individual alarmgenerated interrupts from RSR2.
RCR1 1001 Receive Control Register 1. Programs device operating characteristics.
RCR2 1010 Receive Control Register 2. Programs device operating characteristics.
SERIAL PORT INTERFACE
The port pins of the DS2182A serve as a microprocessor/ microcontroller-compatible serial port. Eleven
on-board registers allow the user to update operational characteristics and monitor device status via a host
controller, minimizing hardware interfaces. The port on the DS2182A can be read from or written to at
any time. Serial port reads and writes are independent of T1 line timing signals RCLK, RPOS, and
RNEG. However, RCLK is needed in order to clear RSR1 and RSR2 after reads.
ADDRESS/COMMAND
Reading or writing the control, configuration or status registers requires writing one address/command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
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register read or write. The following 4 bits identify the register address. The next 2 bits are reserved and
must be set to 0 for proper operation. The last bit of the address/ command word enables burst mode
when set; the burst mode causes all registers to be consecutively read or written to. Data is read and
written to the DS2182A LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held to the next falling edge.
All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into
the addressed register on the rising edge of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and can be tied to SDI in applications where the host
processor has a bi-directional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively written to or read by the host processor.
A burst read is used to poll all registers; RSR1 and RSR2 contents will be unaffected. This feature
minimizes device initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is
set and the address is 0000. A burst is terminated by a low-high transition on CS .
ACB: ADDRESS COMMAND BYTE Figure 2
MSB LSB
BM - - ADD3 ADD2 ADD1 ADD0
R/W
SYMBOL POSITION NAME AND DESCRIPTION
BM ACB.7
Burst Mode.
If set (and register address is 0000) burst read or
write is enabled.
- ACB.6 Reserved, must be 0 for operation.
- ACB.5 Reserved, must be 0 for operation.
ADD3 ACB.4 MSB of register address.
ADD0 ACB.1 LSB of register address.
R/W ACB.0
Read/Write Select.
0 = write addressed register
1 = read addressed register
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SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI is sampled on rising edge of SCLK.
2. SDO is updated on falling edge of SCLK.
OPERATION OF THE COUNTERS
All four of the counters in the DS2182A can be preset by the user to establish an event count interrupt
threshold. The counters count up from the preset value until they reach saturation. At saturation, each
additional event occurrence sets the appropriate bit in RSR2 and generates an interrupt if enabled by
RIMR2.
The DS2182A contains an auto counter reset feature in the burst read mode. If RCR1.4 is set, then the
user can burst read the four counters (five registers), and all four counters will be automatically reset to 0
after the read takes place. Since the burst mode can be terminated at any time by taking CS high, the user
has the option of reading all of the registers or only the counters. If RCR1.4 is set, then any read of the
registers, burst mode or not, will clear the count in all four counters. If the user wishes to read the port
and not clear the counters, then RCR1.4 must be cleared first.
The counter registers can be read or written to at any time with the serial port, which operates totally
asynchronously with the monitoring of the T1 line. Reading a register will not affect the count as long as
RCR1.4 is cleared. The dual buffer architecture of the DS2182A insures that no error events will be
missed while the serial port is being accessed for reads.
BVCR1: BIPOLAR VIOLATION COUNT REGISTER 1;
BVCR2: BIPOLAR VIOLATION COUNTER REGISTER 2 Figure 4
MSB LSB
BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0
SYMBOL POSITION NAME AND DESCRIPTION
BV7 BVCR.7 MSB of bipolar violation count
BV0 BVCR.0 LSB of bipolar violation count
Bipolar Violation Count Register 1 (BVCR1) is the most significant word and BVCR2 is the least
significant word of a presettable 16-bit counter that records individual bipolar violations. If the B8ZS
mode is enabled (RCR2.2 = 1), then B8ZS code words are not counted. The BVCR can also be
programmed to count excessive zeros by setting the RCR2.5 bit. In this mode, the BVCR will count
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occurrences of 8 consecutive zeros when B8ZS is enabled or 16 consecutive zeros when B8Z5 is
disabled. This counter increments at all times and is not disabled by a loss of sync condition (RLOS = 1).
The counter saturates at 65,535 and generates an interrupt for each occurrence after saturation if RIMR2.0
is set.
NOTE:
1. In order to properly preset the Bipolar Violation Count Register, BVCR2 must be written to before
BVCR1 is written to.
CRCCR: CRC COUNT REGISTER 2 Figure 5
MSB LSB
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0
SYMBOL POSITION NAME AND DESCRIPTION
CRC7 CRCCR.7 MSB of CRC6 word error count
CRC0 CRCCR.0 LSB of CRC6 word error count
The CRC Count Register (CRCCR) is an 8-bit presettable counter that records word errors in the Cyclic
Redundancy Check (CRC). This 8-bit binary counter saturates at 255 and generates an interrupt for each
occurrence after saturation if RIMR2.1 is set. The count in this register is only valid in the 193E framing
mode (RCR2.4 = 1) and is reset and disabled in the 193S framing mode (RCR2.4 = 0). The count is
disabled during a loss of sync condition (RLOS = 1).
OOFCR: OOF COUNT REGISTER Figure 6
MSB LSB
OOF7 OOF6 OOF5 OOF4 OOF3 OOF2 OOF1 OOF0
SYMBOL POSITION NAME AND DESCRIPTION
OOF7 OOFCR.7 MSB of OOF event count
OFF0 OOFCR.0 LSB of OOF of event count
The OOF Count Register (OOFCR) is an 8-bit presettable counter that records Out Of Frame (OOF)
events. OOF events are defined by RCR1.5 and RCR1.6. This 8-bit counter saturates at 255 and
generates an interrupt for each occurrence after saturation if RIMR2.2 is set. The count is disabled during
a loss of sync condition (RLOS = 1).
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FECR: FRAME ERROR COUNT REGISTER Figure 7
MSB LSB
FE7 FE6 FE5 FE4 FE3 FE2 FE1 FE0
SYMBOL POSITION NAME AND DESCRIPTION
FE7 FECR.7 MSB of frame error count
FFE0 FECR.0 LSB of frame error count
The Frame Error Count Register (FECR) is an 8-bit pre-settable counter that records individual frame bit
errors. In the 193E mode (RCR2.4 = 1), the FECR records bit errors in the FPS framing pattern
(001011). In the 193S mode (RCR2.4 = 0), the FECR records bit errors in both the FT (101010) and FS
(001110) framing patterns if RCR1.3 is set. If RCR1.3 is cleared, then the FECR only records bit errors in
the FT pattern. This 8-bit counter saturates at 255 and generates an interrupt for each occurrence after
saturation if RIMR2.3 is set. The count is disabled during a loss of sync condition (RLOS = 1).
RSR1: RECEIVE STATUS REGISTER 1 Figure 8
MSB LSB
8ZD 16ZD RCL RYEL RLOS B8ZSD RBL COFA
SYMBOL POSITION NAME AND DESCRIPTION
8ZD RSR1.7 8 Zero Detect. Set when a string of eight consecutive 0s has
been received at RPOS and RNEG.
16ZD RSR1.6 16 Zero Detect. Set when a string of 16 consecutive 0s has
been received at RPOS and RNEG.
RCL RSR1.5 Receive Carrier Loss. Set when a string of 192 consecutive 0s has
been received at RPOS and RNEG. Cleared when 14 or more ones
out of 112 possible bit positions are received.
RYEL RSR1.4
Receive Yellow Alarm.
Set when yellow alarm is detected. The
format of yellow alarm is determined by RCR2.3 and RCR2.4.
RLOS RSR1.3 Receive Loss of Sync. Set when resync is in progress.
B8ZSD RSR1.2
B8ZS Code Word Detect.
Set when a B8ZS code word is
received at RPOS and RNEG independent of whether the B8ZS
mode is enabled or not (RCR2.2).
RBL RSR1.1
Receive Blue Alarm.
Set when over a 3 ms window, 5 or less
zeros are received. Cleared when over a 3 ms window, 6 or more
zeros are received.
COFA RSR1.0
Change of Frame Alignment.
Set when the last resync resulted in
a change of frame or multiframe alignment.
NOTE:
1. Alarm 8ZD and 16ZD are cleared on the next occurrence of a 1 at RPOS and RNEG.
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