Dallas Semiconductor DS2181AQN, DS2181AQ, DS2181AN, DS2181A Datasheet
1 of 32 112099
FEATURES
Single chip primary rate transceiver meets
CCITT standards G.704, G.706 and G.732
Supports new CRC4-based framing
standards and CAS and CCS signaling
standards
Simple serial interface used for device
configuration and control in processor mode
Hardware mode requires no host processor;
intended for stand-alone applications
Comprehensive, on-chip alarm generation,
alarm detection, and error logging logic
Shares footprint with DS2180A T1
Transceiver
Comparison to DS2175 T1/CEPT Elastic
Store, DS2186 Transmit Line Interface,
DS2187 Receive Line Interface, and DS2188
Jitter Attenuator
5V supply; low-power CMOS technology
PIN ASSIGNMENT
DS2181A
CEPT Primary Rate Transceive
r
www.dalsemi.com
TMSYNC 1 40 VDD
TFSYNC 2 39 RLOS
TCLK 3 38 RFER
TCHCLK 4 37 RBV
TSER 5 36 RCL
TMO 6 35 RNEG
TXD 7 34 RPOS
TSTS 8 33 RST
TSD 9 32 TEST
TIND 10 31 RCSYNC
TAF 11 30 RSTS
TPOS 12 29 RSD
TNEG 13 28 RMSYNC
INT 14 27 RFSYNC
SDI 15 26 RSER
SDO 16 25 RCHCLK
CS 17 24 RCLK
SCLK 18 23 RAF
SPS 19 22 RDMA
VSS 20 21 RRA
40-Pin DIP (600-mil
)
TCHCL
K
RFSA
TCL
K
RMSA
TMSYNC
TFSYNC
VDD
RLOS
RFE
R
RBV
RCL
TSE
R
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
TNE
G
INT
SD
I
RNE
G
RPOS
RST
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
RSE
R
RCHCL
K
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
CS
SDO
SCL
K
SPS
RR
A
VSS
RDMA
RCTO
RAF
RCL
K
RCSA
1920212322
242526
27
54312
444342
41
44-PIN PLCC
DS2181A
2 of 32
DESCRIPTION
The DS2181A is designed for use in CEPT networks and supports all logical requirements of CC ITT Red
Book Recommendations G.704, G.706 and G.732. The transmit side generates framing patterns and
CRC4 codes, formats outgoing channel and signaling data, and produces network alarm codes when
enabled. The receive side decodes the incoming data and establishes frame, CAS multiframe, and CRC4
multiframe alignments. Once synchronized, the device extracts channel, signaling, and alarm data.
A serial port allows access to 14 on-chip control and status registers in the processor mode. In this mode,
a host processor controls features such as error logging, per-channel code manipulation, and alteration of
the receive synchronizer algorithm.
The hardware mode is intended for preliminary system prototyping and/or retrofitting into existing
systems. This mode requires no host processor and disables special features available in the processor
mode.
DS2180A BLOCK DIAGRAM Figure 1
DS2181A
3 of 32
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN SYMBOL TYPE DESCRIPTION
1 TMSYNC I Transmit Multiframe Sync. Low-high transition establishes start of
CAS and/or CRC4 multiframe. Can be tied low, allowing internal
multiframe counter to run free.
2 TFSYNC I Transmit Frame Sync. Low-high transition every frame period
establishes frame boundaries. Can be tied low, allowing TMSYNC to
establish frame boundaries.
3TCLK ITransmit Clock. 2.048 MHz primary clock.
4TCHCLK O Transmit Channel Clock. 256 kHz clock which identifies timeslot
boundaries. Useful for parallel-to-serial conversion of channel data.
5TSER ITransmit Serial Data. NRZ data input, sampled on falling edges of
TCLK.
6TMO OTransmit Multiframe Out. Output of multiframe counter; high
during frame 0, low otherwise.
7TXD ITransmit Extra Data. Sampled on falling edge of TCLK during bit
times 5, 7, and 8 of timeslot 16 in frame 0 when CAS signaling is
enabled.
8TSTS OTransmit Signaling Timeslot. High during timeslot 16 of every
frame, low otherwise.
9TSD ITransmit Signaling Data. CAS signaling data input; sampled on
falling edges of TCLK for insertion into outgoing timeslot 16 when
enabled.
10 TIND I Transmit International and National Data. Sampled on falling
edge of TCLK during bit 1 time of timeslot 0 every frame
(international) and/or during bit times 4 through 8 of timeslot 0 during
non-align frames (national) when enabled.
11 TAF O Transmit Alignment Frame. High during frames containing the
frame alignment signal, low otherwise.
12
13
TPOS
TNEG
O Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
SYCHRONIZER STATUS PIN (44-PIN PLCC ONLY) Table 2A
PIN SYMBOL TYPE DESCRIPTION
3RMSA OReceive Multiframe Search Active. This pin will transition high
when the synchronizer searching for the CAS multiframe alignment
word is active.
6RFSA OReceive Frame Search Active. This pin will transition high when the
synchronizer searching for the FAS is active.
25 RCTO O Receive CRC4 Time Out. This pin will transition high when the
RCTO counter reaches its maximum count of 32. The pin will return
low when either the DS2181AQ reaches CRC4 multiframe
synchronization, or if CRC4 is disabled via CRC.2, or if the device is
issued a hardware reset via the RST pin.
28 RCSA O Receive CRC4 Search Active. This pin will transition high when the
synchronizer searching for the CRC4 multiframe alignment word is
active.
DS2181A
4 of 32
NOTES:
1. These output status pins are only available on the DS2181AQ.
2. If the TEST pin is tied low and CCR.1=0, then these pins will be tri–stated.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 2B
PIN SYMBOL TYPE DESCRIPTION
21 RRA O
Receive Remote Alarm. Transitions high when alarm detected;
returns low when alarm cleared.
22 RMDA O
Receive Distant Multiframe Alarm. Transitions high when alarm
detected; returns low when alarm cleared.
23 RAF O
Receive Alignment Frame. High during frames cont aining the fram e
alignment signal, low otherwise.
24 RCLK I
Receive Clock. 2.048 MHz primary clock.
25 RCHCLK O
Receive Channel Clock. 256 kHz clock, identifies timeslot
boundaries; useful for serial-to-parallel conversion of channel data.
26 RSER O
Receive Channel Clock. 256 kHz clock, identifies timeslot
boundaries; useful for serial-to-parallel conversion of channel data.
27 RFSYNC O
Receive Frame Sync. Trailing edge indicates start of frame.
28 RMSYNC O
Receive Multiframe Sync. Low-high transition indicates start of
CAS multiframe; held high during frame 0.
29 RSD O
Receive Signaling Data. Extracted timeslot 16 data; updated on
rising edge of RCLK.
30 RSTS O
Receive Signaling Timeslot. High during timeslot 16 of every frame,
low otherwise.
31 RCSYNC O
Receive CRC4 Sync. Low-high transition indicates start of CRC4
multiframe; held high during CRC4 frames 0 through 7 and held low
during frames 8 through 15.
33
RST
I
Reset. Must be asserted during device power-up and when chan ging
to/from the hardware mode.
34
35
RPOS
RNEG
I
Receive Bipolar Data. Sampled on falling edges of RCLK. Tie
together to receive NRZ data and disable BPV monitor circuitry.
36 RCL O
Receive Carrier Loss. Low-high transition indicates loss of carrier.
37 RBV O
Receive Bipolar Violation. Pulses high during detected bipolar
violations.
38 RFER O
Receive Frame Error. Pulses high when frame alignment, CAS
multiframe alignment or CRC4 words received in error.
39 RLOS O
Receive Loss of Sync. Indicates synchronizer status; high when
frame, CAS and/or CRC4 multiframe search underway, low
otherwise.
DS2181A
5 of 32
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN SYMBOL TYPE DESCRIPTION
14
INT
O
Receive Alarm Interrupt. Flags host controller during alarm
conditions. Active low; open drain output.
15 SDI I
Serial Data In. Data for on-chip control registers; sampled on rising
edge of SCLK.
16 SDO O
Serial Data Out. Control and status data from on-chip registers.
Updated on falling edge of SCLK; tri-stated during port write or when
CS is high.
17
CS
I
Chip Select. Must be low to write or read the serial port.
18 SCLK I
Serial Data Clock. Used to write or read the serial port registers.
19 SPS I
Serial Port Select. Tie to VDD to select the serial port. Tie to VSS to
select the hardware mode.
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN SYMBOL TYPE DESCRIPTION
20 V
SS
-
Signal Ground. 0.0 volts.
32 TEST I
Test Mode. Tie to VSS to select the old DS2181 sync algorithm and to
tri–state the synchronizer status pins on the DS2181AQ. Tie to V
DD
to select the new DS2181A sync algorithm and activate the
synchronizer status pins on the DS2181AQ.
40 V
DD
-
Positive Supply. 5.0 volts.
DS2181A
6 of 32
REGISTER SUMMARY Table 5
REGISTERADDRE
SS
T/R
1
DESCRIPTION/FUNCTION
RIMR 0000 R
Receive Interrupt Mask Register. Allows masking of alarm
generated interrupts.
RSR 0001 R
2
Receive Status Register. Reports all receive alarm conditions.
BVCR 0010 R
Bipolar Violation Count Register. 8-bit presettable counter
which records individual bipolar violations.
CECR 0011 R
CRC4 Error Count Register. 8-bit presettable counter which
records individual errors.
FECR 0100 R
Frame Error Count Register. 8-bit presettable counter which
logs individual errors in the received frame alignment signal.
RCR 0101 R
Receive Control Register. Establishes receive side operating
characteristics.
CCR 0110 T/R
Common Control Register. Establishes additional operating
characteristics for transmit and receive sides.
TCR 0111 T
Transmit Control Register. Establishes transmit side operation
characteristics.
TIR1
TIR2
TIR3
TIR4
1000
1001
1010
1011
T Transmit Idle Registers. Designates which outgoing timeslots are
to be substituted with idle code.
TINR 1100 T Transmit International and National Register. When enabled via
the TCR, contents inserted into the outgoing national and/or
international bit positions.
TXR 1101 T Transmit Extra Register. When enabled via the TCR, contents
inserted into the out going extra bit positions.
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations must be programmed to 0.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2181A serve as a microprocessor/ micro controller-compatible serial port.
Fourteen on-chip registers allow the user to update operational characteristics and monitor device status
via a host controller, minimizing hardware interfaces.
Port read/write timing is unrelated to the chip transmit and receive timing, allowing asynchronous reads
and/ or writes by the host. The timing set is identical to that of 8051-type microcontrollers operating in
serial port mode 0. For proper operation of the port and the transmit and receive registers, the user should
provide TCLK and RCLK as well as SCLK.
DS2181A
7 of 32
ADDRESS/COMMAND
An address/command byte write must precede any read or write of the port registers. The first bit written
(LSB) of the address/command byte specifies read or write. The following nibble identifies register
address. The next 2 bits are reserved and must be set to 0 for proper operation. The last bit of the
address/command word enables the burst mode when set; the burst mode all ows consecutive reading or
writing of all register data. Data is written to and read from the port LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Data is sampled on the rising edge of SCLK.
Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are
terminated and SDO tri-stated when CS returns to high.
CLOCKS
To access the serial port registers both TC LK and RCLK are required along with the SCLK. The TCLK
and RCLK are used to internally access the transmit and receive registers, respectively. The CCR is
considered a receive register for this purpose.
DATA I/O
Following the eight SCLK cycles that input the address/ command byte, data at SDI is strobed into the
addressed register on the next eight SCLK cycles (register write) or data is presented at SDO on the next
eight SCLK cycles (register read). SDO is tri-stated during writes and may be tied to SDI in applications
where the host processor has bi-directional I/O capability.
BURST MODE
The burst mode allows all on-chip registers to be consecutively read or written by the host processor. This
feature minimizes device initialization time on system power-up or reset. Burst mode is initiated when
ACB.7 is set and the address nibble is 0000. All registers must be read or written during the burst mode.
If CS transitions high before the burst is complete, data validity is not guaranteed.
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB) (LSB)
BM - - ADD3 ADD2 ADD1 AD0 R/W
SYMBOL POSITION NAME AND DESCRIPTION
BM ACB.7 Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.
- ACB.6 Reserved, must be 0 for proper operation.
- ACB.5 Reserved, must be 0 for proper operation.
ADD3 ACB.4 MSB of register address.
ADD2 ACB.3
ADD1 ACB.2
ADD0 ACB.1 LSB of register address.
R/W
ACB.0
Read/Write Select.
0 = write addressed register.
1 = read addressed register.
DS2181A
8 of 32
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
TCR: TRANSMIT CONTROL REGISTER Figure 4
(MSB) (LSB)
TUA1 TSS TSM INBS NBS XBS TSA1 ODM
SYMBOL POSITION NAME AND DESCRIPTION
TUA1 TCR.7
Transmit Unframed All 1’s.
0 = Normal operation.
1 = Replace outgoing data at TPOS and TNEG with unframed all
1’s code.
TSS TCR.6
Transmit Signaling Select
1
0 = Signaling data embedded in the serial bit stream is sampled at
TSER during timeslot 16.
1 = Signaling data is channel associated and sampled at TSD as
shown in Table 6.
TSM TCR.5
Transmit Signaling Mode
1
0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
INBS TCR.4
International Bit Select
0 = Sample international bit at TIND.
1 = Outgoing international bit = TINR.7.
NBS TCR.3
National Bit Select
0 = Sample national bits at TIND.
1 = Source outgoing national bits from TINR.4 through TINR.0.
XBS TCR.2
Extra Bit Select
0 = Sample extra bits at TXD.
1 = Source extra bits from TXR.0 through TXR.1 and TXR.3.
TSA1 TCR.1
Transmit Signaling All 1’s
0 = Normal operation.
1 = Force contents of timeslot 16 in all frames to all 1’s.
ODM TCR.0
Output Data Mode
0 = TPOS and TNEG outputs are 100% duty cycle.
1 = TPOS and TNEG outputs are 50% duty cycle.
DS2181A
9 of 32
NOTE:
1. When the common channel signaling mode is enabled (TCR.5 = 1), the TSD input is disabled
internally; all timeslot 16 data is sampled at TSER.
CCR: COMMON CONTROL REGISTER Figure 5
(MSB) (LSB)
- TAFP THDE RHDE TCE RCE SAS LLB
SYMBOL POSITION NAME AND DESCRIPTION
- CCR.7 Reserved; must be 0 for proper operation.
TAFP CCR.6
Transmit Align Frame Position
1
When clear, the CAS multiframe begins with a frame containing
the frame alignment signal. When set, the CAS multiframe begins
with a frame not containing the frame alignment signal.
THDE CCR.5
Transmit HDB3 Enable
0 = Outgoing data at TPOS and TNEG is AMI coded.
1 = Outgoing data at TPOS and TNEG is HDB3 coded.
RHDE CCR.4
Receive HDB3 Enable
0 = Incoming data at RPOS and RNEG is AMI coded.
1 = Incoming data is RPOS and RNEG is HDB3 coded.
TCE CCR.3
Transmit CRC4 Enable
When set, outgoing international bit positions in frames 0 through
12 and 14 are replaced by CRC4 multiframe alignment and
checksum words.
RCE CCR.2
Receive CRC4 Enable
0 = Disable CRC4 multiframe synchronizer.
1 = Enable CRC4 synchronizer; search for CRC4 multiframe
alignment once frame alignment complete.
SAS CCR.1
Sync Algorithm Select
0 = Use old DS2181 sync algorithm
1 = Use new DS2181A sync algorithm
LLB CCR.0
Local Loopback
0 = Normal operation.
1 = Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG,
and RCLK.
NOTES:
1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3 = 1); its state does not
affect CCS framing (RCR.5 = 1).
2. CCR is considered a receive register and operates from RCLK and SCLK.
DS2181A
10 of 32
RCR: RECEIVE CONTROL REGISTER Figure 6
(MSB) (LSB)
- - RSM CMSC CMRC FRC SYNCE RESYNC
SYMBOL POSITION NAME AND DESCRIPTION
- RCR.7 Reserved; must be 0 for proper operation.
- RCR.6 Reserved; must be 0 for proper operation.
RSM RCR.5
Received Signaling Mode
0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
CMSC RCR.4
CAS Multiframe Sync Criteria
0 = Declare sync when fixed sync criteria met.
1 = Declare sync when fixed criteria are met and two additional
consecutive valid multiframe alignment signals are detected.
CMRC RCR.3
CAS Multiframe Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if two consecutive timeslot
16 words have values of 0 in the first four MSB positions
(0000xxxx).
FRC RCR.2
Frame Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if bit 2 in timeslot 0 of nonalign frames is received in error on three consecutive occasions.
SYNCE RCR.1
Sync Enable
If clear, the synchronizer will automatically begin resync if error
criteria are met. If high, no auto resync occurs.
RESYNC RCR.0
Resync
When toggled low to high, the receive synchronizer will initiate
immediately. The bit must be cleared, then set again for
subsequent resyncs.
CEPT FRAME STRUCTURE
The CEPT frame is made up of 32 8-bit channels (time-slots) numbered from 0 to 31. The frame
alignment signal in bit positions 2 through 8 of timeslot 0 of every other frame is independent of the
various multiframe modes described below. Outputs TAF and RAF indicate frames which contain the
alignment signal. Timeslot 0 of frames not containing the frame ali gnment signal is used for alarm and
national data. See the separate DS2181A CEPT Transceiver Application Note for more details.
CAS SIGNALLING
CEPT networks support Channel Associated Signaling (CAS) or Common Channel Signaling (CCS).
These signaling modes are independently selectable for transmit and receive sides.
CAS (selected when TCR.5 = 0 and/or when RCR.5 = 0) is a bit-oriented signaling technique which
utilizes a 16-frame multiframe. The multiframe alignment signal (0-hex), extra and alarm bits occupy
timeslot 16 of frame 0. Timeslot 16 of the remaining 15 frames is reserved for channel signaling data.
Four signaling bits (A, B, C and D) are transmitted once per multiframe as shown in Figure 7. Input
TMSYNC establishes the transmitted CAS multiframe position. Signaling data can be sourced from input
TSD (TCR.6 = 1) or multiplexed into TSER (TCR.6 = 0).
Loading...