Dallas Semiconductor DS2180AQN, DS2180AQ, DS2180AN, DS2180A Datasheet
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FEATURES
Single chip DS1 rate transceiver
Supports common framing standards
– 12 frames/superframe “193S”
– 24 frames/superframe “193E”
Three zero suppression modes
– B7 stuffing
– B8ZS
– Transparent
Simple serial interface used for config-
uration, control and status monitoring in
“processor” mode
=“Hardware” mode requires no host
processor; intended for stand-alone applications
Selectable 0, 2, 4, 16 state robbed bit
signaling modes
Allows mix of “clear” and “non-clear” DS0
channels on same DS1 link
Alarm generation and detection
Receive error detection and counting for
transmission performance monitoring
5V supply, low-power CMOS technology
Surface-mount package available, designated
DS2180AQ
Industrial temperature range of -40°C to
+85°C available, designated DS2180AN or
DS2180AQN
Compatible to DS2186 Transmit Line
Interface, DS2187 Receive Line Interface,
DS2188 Jitter Attenuator, DS2175 T1/CEPT
Elastic Store, DS2290 T1 Isolation Stik, and
DS2291 T1 Long Loop Stik
PIN ASSIGNMENT
DS2180A
T1 Transceive
r
www.dalsemi.com
TMSYNC 1 40 VDD
TFSYNC 2 39 RLOS
TCLK 3 38 RFER
TCHCLK 4 37 RBV
TSER 5 36 RCL
TMO 6 35 RNEG
TSIGSEL 7 34 RPOS
TSIGFR 8 33 RST
TABCD 9 32 TEST
TLINK 10 31 RSIGSEL
TLCLK 11 30 RSIGFR
TPOS 12 29 RABCD
TNEG 13 28 RMSYNC
INT 14 27 RFSYNC
SDI 15 26 RSER
SDO 16 25 RCHCLK
CS 17 24 RCLK
SCLK 18 23 RLCLK
SPS 19 22 RLINK
VSS 20 21 RYEL
40-Pin DIP (600-mil
)
TCHCL
K
N
C
TCL
K
N
C
TMSYNC
TFSYNC
VDD
RLOS
RFE
R
RBV
RCL
TSE
R
TMO
TSIGSE
L
TSIGF
R
TABCD
TLIN
K
TLCL
K
TPOS
TNE
G
INT
SD
I
RNE
G
RPOS
RST
TEST
RSIGSE
L
RSIGF
R
RABCD
RMSYNC
RFSYNC
RSE
R
RCHCL
K
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
CS
SDO
SCL
K
SPS
RYEL
VSS
RLIN
K
NC
RLCL
K
RCL
K
NC
1920212322
242526
27
54312
444342
41
DS1386/DS1386P
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DESCRIPTION
The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-car rier
transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12
frames/superframe). The 193E framing mode supports the extended superframe format (24
frames/superframe). Clear channel capability is provided by selection of appropriate zero suppression
and signaling modes.
Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriate
framing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides
output clocks useful for data conditioning and decoding. The receive s ynchronizer establishes frame and
multi-frame boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and
transmission errors, and provides output clocks useful for data conditioning and decoding.
The control block is shared between transmit and receive sides. This block determines the frame, zero
suppression, alarm and signaling formats. User access to the control block is by one of two modes.
In the processor mode, pins 14 through 18 are a micro-processor/ microcontroller-compatible serial port
which can be used for device configuration, control and status monitoring.
In the hardware mode, no offboard processor is required. Pins 14 through 18 are reconfi gured into “hard wired” select pins. Features such as selection “clear” DS0 channels, insertion of idle code and alteration
of sync algorithm are unavailable in the hardware mode.
DS2180A BLOCK DIAGRAM Figure 1
DS2180A
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TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN SYMBOL TYPE DESCRIPTION
1 TMSYNC I
Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to
reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
2 TFSYNC I Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed
every frame to reinforce internal frame counter or tied low (allowing TMSYNC to
establish frame and multiframe alignment).
3TCLK ITransmit Clock. 1.544 MHz primary clock.
4 TCHCLK O Transmit Channel Clock. 192 kHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
5TSER ITransmit Serial Data. NRZ data input, sample on falling edge of TCLK.
6TMO OTransmit Multiframe Out. Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
7TSIGSEL O
Transmit Signaling Select. .667 kHz clock which identifies signaling frame A and
C in 193E framing. 1.33 kHz clock in 193S.
8TSIGFR OTransmit Signaling Frame. High during signali ng frames, low otherwise.
9TABCD I
Transmit ABCD Signaling. When enabled via TCR.4, sampled during channel
LSB time in signaling frames on falling edge of TCLK.
10 TLINK I Tra nsmit Link Data . Sampled during the F-bit time (falling edge of TCLK) of odd
frames for insertion into the outgoing data stream (193E-FDL insertion). Sampled
during the F-bit time of even frames for insertion into the outgoing data (193SExternal S-Bit insertion).
11 TLCLK O Transmit Link Clock. 4 kHz demand clock for TLINK input.
12
13
TPOS
TNEG
O Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
PIN SYMBOL TYPE DESCRIPTION
14
INT
1
O
Receive Alarm Interrupt. Flags host controller during alarm conditions. Active
low, open drain output.
15 SDI
1
I Serial Data In. Data for onboard registers. Sampled on rising edge of SCLK.
16 SDO
1
O
Serial Data Out. Control and status i nformation fro m onboard register s. Updated
on falling edge of SCLK, tri-stated during serial port write or when
CS is high.
17
CS
1
I Chip Select. Must be low to write or read the serial port registers.
18 SCLK
1
I Serial Data Clock. Used to write or read the serial port registers.
19 SPS I Serial Port Select. Tie to VDD to select serial port. Tie to VSS to select hardware
mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description."
DS2180A
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POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN SYMBOL TYPE DESCRIPTION
20 V
SS
- Signal Ground. 0.0 volts.
32 TEST I Test Mode. Tie to VSS for normal operation.
40 V
DD
- Positive Supply. 5.0 volts.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN SYMBOL TYPE DESCRIPTION
21 RYEL 0 Receive Yellow Alarm. Transitions high when yellow alarm detected, goes low
when alarm clears.
22 RLINK 0 Receive Link Data. Updated with extracted FDL data one RCLK before start of
odd frames (193E) and held until next update. Updated with extracted S-bit data one
RCLK before start of even frames (193S) and held until next update.
23 RLCLK 0 Receive Link Clock. 4 kHz demand clock for RLINK.
24 RCLK I Receive Clock. 1.544 MHz primary clock.
25 RCHCLK O Receive Channel Clock. 192 kHz clock identifies time slot (channel) boundaries.
26 RSER O Receive Serial Data. Received NRZ serial data, updated on rising edges of RCLK.
27 RFSYNC O Receive Frame Sync. Extracted 8 kHz clock, one RCLK wide, indicates F-Bit
position in each frame.
28 RMSYNC O
Receive Multiframe Sync. Extracted multiframe sync; edge indicates start of
multiframe, 50% duty cycle.
29 RABCD O Receive ABCD Signaling. Extracted signaling data output, valid for each channel
time in signaling frames. In non-signaling frames, RABCD outputs the LSB of each
channel word.
30 RSIGFR O
Receive Signaling Frame. High during signaling frames, low during resync and
non-signaling frames.
31 RSIGSEL O Receive Signaling Select. In 193E framing a .667 kHz clock which identifies
signaling frames A and C. A 1.33 kHz clock in 193S.
33 RST I
Reset. A high-low transition clears all internal registers and resets receive side
counters. A high-low-high transition will initiate a receive resync.
34
35
RPOS
RNEG
I
Receive Bipolar Data Inputs. Samples on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
36 RCL O Receive Carrier Loss. High if 32 consecutive 0's appear at RPOS and RNEG; goes
low after next 1.
37 RBV O
Receive Bipolar Violation. High during accused bit time at RSER if bipolar
violation detected, low otherwise.
38 RFER O Receive Frame Error. High during F-Bit time when FT or FS errors occur (193S)
or when FPS or CRC errors occur (193E). Low during resync.
39 RLOS O
Receive Loss of Sync. Indicates sync status; high when internal resync is in
progress, low otherwise.
DS2180A
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REGISTER SUMMARY Table 5
REGISTER ADDRESS T/R
1
DESCRIPTION/FUNCTION
RSR 0000 R
2
Receive Status Register. Reports all receive alarm conditions.
RIMR 0001 R Receive Interrupt Mask Register. Allows masking of individual alarm-
generated interrupts.
BVCR 0010 R
Bipolar Violation Count Register. 8-bit presettable counter which records
individual bipolar violations.
ECR 0011 R Error Count Register. Two independent 4-bit counters which record OOF
occurrences and individual frame bit or CRC errors.
CCR
3
0100 T/R
Common Control Register. Selects device operating characteristics common
to receive and transmit sides.
RCR
3
0101 R
Receive Control Register. Programs device operating characteristics
unique to the receive side.
TCR
3
0110 T Transmit Control Register. Selects additional transmit side modes.
TIR1
TIR2
TIR3
0111
1000
1001
T
T
T
Transmit Idle Registers. Designate which outgoing channels are to be
substituted with idle code.
TTR1
TTR2
TTR3
1010
1011
1100
T
T
T
Transmit Transparent Registers. Designate which outgoing channels are to be
treated transparently. (No robbed bit signaling or bit 7 zero insertion.)
RMR1
RMR2
RMR3
1101
1110
1111
R
R
R
Receive Mark Registers. Designate which incoming channels are to be replaced
with idle or digital milliwatt codes (under control of RCR).
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations in the control registers should be programmed to 0 to maintain compatibility
with future transceiver products.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port.
Sixteen onboard registers allow the user to update operational characteristics and monitor device status
via host controller, minimizing hardware interfaces. Port read/write timing is unrelated to the system
transmit and receive timing, allowing asynchronous reads and/or writes by the host.
ADDRESS/COMMAND
Reading or writing the control, configuration or status registers requires writing one address command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4-bit nibble identifies register address. The next two bits are
reserved and must be set to 0 for proper operation. The last bit of the address/ command word enables
burst mode when set; the burst mode causes all registers to be consecutively written or read. Data is
written to and read from the transceiver LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held on the next falling edge.
DS2180A
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All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/ command byte to write, a data byte is strobed into
the addressed register on the rising edges of the next eight SCLK c ycles. Following an address/comm and
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and may be tied to SDI in applications where the
host processor has a bi-directional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively read and written by the host processor. A
burst read is used to poll all registers; RSR contents will be unaffected. This feature minimizes device
initialization time on power-up or system reset. Burst mode is initiated when ACB.7 is set and the address
nibble is 0000. Burst is terminated by a low-high transition on CS.
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB) (LSB)
BM - - ADD3 ADD2 ADD1 AD0
R/W
SYMBOL POSITION N AME AND DESCRIPTION
BM ACB.7 Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.
- ACB.6 Reserved, must be 0 for proper operation.
- ACB.5 Reserved, must be 0 for proper operation.
ADD3 ACB.4 MSB of register address.
ADD0 ACB.1 LSB of register address.
R/W
ACB.0
Read/Write Select.
0 = write addressed register.
1 = read addressed register.
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
DS2180A
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ACB: ADDRESS COMMAND BYTE Figure 4
(MSB) (LSB)
- FRSR2 EYELMD FM SYELMD B8ZS B7 LPBK
SYMBOL POSITION N AME AND DESCRIPTION
- CCR.7 Reserved, must be 0 for proper operation.
FRSR2 CCR.6
Function of REC Status Register 2.
0 = Detected B8ZS code words reported at RSR.2.
1 = COFA (Change-of-Frame Alignment) reported at RSR.2 when
last resync resulted in change of frame or multiframe alignment.
EYELMD CCR.5
193E Yellow Mode Select.
0 = Yellow alarm is a repeating pattern set of 00 hex and FF hex.
1 = Yellow alarm is a 0 in the bit 2 position of all channels.
FM CCR.4
Frame Mode Select.
0 = D4 (193S, 12 frames/superframe).
1 = Extended (193E, 24 frames/superframe).
SYELMD CCR.3 193S Yellow Mode Select. Determines yellow alarm type to be
transmitted and detected while in 193S framing. If set, yellow
alarms are a 1 in the S-bit position of frame 12; if cleared, yellow
alarm is a 0 in bit 2 of all channels. Does not affect 193E yellow
alarm operation.
B8ZS
CCR.2
Bipolar eight zero substitution.
0 = No B8ZS.
1 = B8ZS enabled.
(Note: This bit must be set to 0 when CCR.1=1)
B7 CCR.1
Bit seven zero suppression. If CCR.1=1, channels with an all zero
content will be transmitted with bit 7 forced to 1. If CCR.1=0, no
bit 7 stuffing occurs.
(Note: This bit must be set to 0 when CCR.2=1)
LPBK
CCR.0 Loopback. When set, the device internally loops output transmit
data into the incoming receive data buffers and TCLK is internally
substituted for RCLK.
LOOPBACK (Refer to Figure 4)
Enabling loopback will typically induce an out-of-frame (OOF) condition. If appropriate bits are set in
the receive control register, the receiver will resync to the looped transmit frame alignment. During the
looped condition, the transmit outputs (TPOS, TNEG) will transmit unframed all 1's. All operating modes
(B8ZS, alarm, signaling, etc.) except for blue alarm transmission are available in loopback.
BIT SEVEN STUFFING
Existing systems meet 1's density requirements by forcing bit 7 of all zero channels to 1. Bit 7 stuffing is
globally enabled by asserting bit CCR.1 and may be disabled on an individual channel basis by setting
appropriate bits in TTR1–TTR3. Bit 7 stuffing and B8ZS modes should not be enabled simultaneously.
Enabling both results in LOS.
DS2180A
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B8ZS
The DS2180A supports existing and emerging zero suppression formats. Selection of B8ZS coding
maintains system 1’s density requirements without disturbing data integrity as required in emerging clear
channel applications. B8ZS coding replaces eight consecutive outgoing 0's with a B8ZS code word. Any
received B8ZS code word is replaced with all 0’s. B8ZS and bit 7 stuffing modes should not be enabled
simultaneously. Enabling both results in LOS.
TCR: TRANSMIT CONTROL REGISTER Figure 5
(MSB) (LSB)
ODF TFPT TCP RBSE TIS 193SI TBL TYEL
SYMBOL POSITION N AME AND DESCRIPTION
ODF TCR.7
Output Data Format.
0 = Bipolar data at TPOS and TNEG.
1 = NRZ data at TPOS; TNEG=0.
TFPT TCR.6
Transmit Framing Pass-through.
0 = FT/FPS sourced internally.
1 = FT/FPS sampled at TSER during F-bit time.
TCP TCR.5
Transmit CRC Pass-through.
0 = Transmit CRC code internally generated.
1 = TSER sampled at CRC F-bit time for external CRC insertion.
RBSE TCR.4
Robbed Bit Signaling Enable.
1 = Signaling inserted in all channels during signaling frames.
0 = No signaling inserted. (The TTR registers allow the user to
disable signaling insertion on selected DS0 channels.)
TIS TCR.3
Transmit Idle Code Select. Determines idle code format to be
inserted into channels marked by the TIR registers.
0 = Insert 7F (Hex) into marked channels.
1 = Insert FF (Hex) into marked channels.
193SI
TCR.2
193S S-bit Insertion. Determines source of transmitted S-bit.
0 = Internal S-bit generator.
1 = External (sampled at TLINK input).
TBL TCR.1
Transmit Blue Alarm.
0 = Disabled.
1 = Enabled.
TYEL
TCR.0
TYEL TCR.0 Transmit Yellow Alarm.
0 = Disabled.
1 = Enabled.
TR ANSMIT BLUE ALARM
The blue alarm (also known as the AIS, Alarm Indication Signal) is an unframed, all 1’s sequence
enabled by asserting TCR.1. Blue alarm overrides all other transmit data patterns and is disabled by
clearing TCR.1. Use of the TIR registers allows a framed, all 1’s alarm transmission if required by the
network.
TRANSMIT YELLOW ALARM
In 193E framing, a yellow alarm is a repeating pattern set of FF(Hex) and 00 (Hex ) on the 4 kHz facility
data link (FDL). In 193S framing the yellow alarm format is dependent on the state of bit CCR.3. In all
modes, yellow alarm is enabled by asserting TCR.0 and disabled by clearing TCR.0.
DS2180A
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TRANSMIT SIGNALING
When enabled (via TCR.4) channel signaling is inserted in frames 6 and 12 (193S) or in frames 6, 12, 18
and 24 (193E) in the 8th bit position of every channel word. Signaling data is sampled at TABCD on the
falling edge of TCLK during bit 8 of each input word during signaling frames. Logical combination of
clocks TMO, TSIGFR and TSIGSEL allows external multiplexing of separate serial links for A, B or A,
B, C, D signaling sources.
TTR1–TTR3: TRANSMIT TRANSPARENCY REGISTERS Figure 6
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TIR1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TIR2
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TIR3
SYMBOL POSITION N AME AND DESCRIPTION
CH24 TTR3.7
CH1 TTR1.0
Transmit Transparent Registers. Each of these bit positions
represents a DS0 channel in the outgoing frame. When set, the
corresponding channel is transparent.
TIR1–TIR3: TRANSMIT IDLE REGISTERS Figure 7
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TIR1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TIR2
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TIR3
SYMBOL POSITION N AME AND DESCRIPTION
CH24 TIR3.7
CH1 TIR1.0
Transmit Idle Registers. Each of these bit positions represents a
DS0 channel in the outgoing frame. When set, the corresponding
channel will output an idle code format determined by TCR.2.
TR ANSMIT CHAN NEL TRANSPARENCY
Individual DS0 channels in the T1 frame may be programmed clear (no inserted robbed bit signaling and
no bit 7 zero suppression) by setting the appropriate bits in the transmit transparency registers. Channel
transparency is required in mixed voice/data or data-only environments such as ISDN, where data
integrity must be maintained.
TRANSMIT IDLE CODE INSERTION
Individual outgoing channels in the frame can be programmed with idle code by asserting the appropriate
bits in the transmit idle registers. One of two idle code formats, 7F (Hex) and FF (Hex) may be selected
by the user via TCR.3. If enabled, robbed bit signaling data is inserted into the idle channel, unless the
appropriate TTR bit is set for that channel. This feature eliminates external hardware currently required to
intercept and stuff unoccupied channels in the DS1 bit stream.
DS2180A
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TRANSMIT INSERTION HIERARCHY Figure 8
DS2180A
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193S TRANSMIT MULTIFRAME TIMING Figure 9
NOTES:
1. Transmit frame and multiframe timing may be established in one of four ways:
a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish
multiframe boundaries, allowing internal counters to determine frame timing.
b. TFSYNC may be pulsed every 125 microseconds; pulsing TMSYNC once establishes multiframe
boundaries.
c. TMSYNC and TFSYNC may be continuously pulsed to establish and reinforce frame and
superframe timing.
d. If TMSYNC is tied low and TFSYNC is pulsed at frame boundaries, the transmitter will establish
an arbitrary multiframe boundary as indicated by TMO.
2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in
frames indicated.
3. When external S-bit insertion is enabled, TLINK will be sampled during the F-bit time of even frames
and inserted into the outgoing data stream.
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