Dallas Semiconductor DS2155LN, DS2155L, DS2155GN, DS2155G Datasheet
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GENERAL DESCRIPTION
The DS2155 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The DS2155 is composed of
a line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled by
an 8-bit parallel port configured for Intel or Motorola
bus operations. The DS2155 is pin and software
compatible with the DS2156.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75!
coax and 120! twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
APPLICATIONS
T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
T1/E1/J1
NETWORK
T1/E1/J1 Single-Chip Transceiver
DS2155
FEATURES
§ Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality
§ Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
§ Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping
§ CMI Coder/Decoder for Optical I/F
§ Crystal-Less Jitter Attenuator
§ Fully Independent Transmit and Receive
Functionality
§ Dual HDLC Controllers
§ Programmable BERT Generator and Detector
§ Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75"/100"/120" T1 and E1 Interfaces
§ Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued on page 2.
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS2155L 0°C to +70°C
DS2155LN -40°C to +85°C 100 LQFP
DS2155G 0°C to +70°C
DS2155GN -40°C to +85°C 10mm CSBGA
DS2155
T1/E1/J1
BACKPLANE
SCT
TDM
100 LQFP
10mm CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
be simultaneously available through various sales channels. For information about device errata, click here:www.maxim-ic.com/errata.
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1. TABLE OF CONTENTS
1. TABLE OF CONTENTS..................................................................................................................................2
1.1 T
1.2 T
ABLE OF FIGURES ........................................................................................................................................6
ABLE OF TABLES..........................................................................................................................................7
2. DATA SHEET REVISION HISTORY ...........................................................................................................8
3. MAIN FEATURES .........................................................................................................................................10
3.1 F
3.2 B
UNCTIONAL DESCRIPTION .........................................................................................................................13
LOCK DIAGRAM.........................................................................................................................................15
4. PIN FUNCTION DESCRIPTION.................................................................................................................19
4.1 T
4.2 R
4.3 P
4.4 E
4.5 U
4.6 JTAG T
4.7 L
4.8 S
4.9 L
4.10 10
RANSMIT SIDE ...........................................................................................................................................19
ECEIVE SIDE ..............................................................................................................................................22
ARALLEL CONTROL PORT PINS .................................................................................................................26
XTENDED SYSTEM INFORMATION BUS......................................................................................................27
SER OUTPUT PORT PINS ............................................................................................................................28
EST ACCESS PORT PINS...................................................................................................................29
INE INTERFACE PINS..................................................................................................................................30
UPPLY PINS ................................................................................................................................................31
AND G PACKAGE PINOUT .........................................................................................................................32
MM CSBGA PIN CONFIGURATION ......................................................................................................34
5. PARALLEL PORT .........................................................................................................................................35
5.1 R
EGISTER MAP ............................................................................................................................................35
6. PROGRAMMING MODEL ..........................................................................................................................41
6.1 P
OWER-UP SEQUENCE.................................................................................................................................42
6.1.1 Master Mode Register.........................................................................................................................42
NTERRUPT HANDLING ................................................................................................................................43
6.2 I
6.3 S
6.4 I
6.5 I
TATUS REGISTERS......................................................................................................................................43
NFORMATION REGISTERS ...........................................................................................................................44
NTERRUPT INFORMATION REGISTERS ........................................................................................................44
7. SPECIAL PER-CHANNEL REGISTER OPERATION.............................................................................45
8. CLOCK MAP ..................................................................................................................................................47
9. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..................................................48
9.1 T1 C
9.2 T1 T
9.3 AIS-CI
9.4 T1 R
ONTROL REGISTERS.............................................................................................................................48
RANSMIT TRANSPARENCY ...................................................................................................................53
AND RAI-CI GENERATION AND DETECTION ..................................................................................53
ECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION .....................................................................54
10. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS............................................57
10.1 E1 C
10.2 A
10.3 E1 I
ONTROL REGISTERS.........................................................................................................................57
UTOMATIC ALARM GENERATION .........................................................................................................61
NFORMATION REGISTERS .................................................................................................................62
11. COMMON CONTROL AND STATUS REGISTERS ..........................................................................64
11.1 T1/E1 S
TATUS REGISTERS ......................................................................................................................65
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12. I/O PIN CONFIGURATION OPTIONS.................................................................................................71
13. LOOPBACK CONFIGURATION ..........................................................................................................73
13.1 P
ER-CHANNEL LOOPBACK ......................................................................................................................75
14. ERROR COUNT REGISTERS ...............................................................................................................77
14.1 L
INE-CODE VIOLATION COUNT REGISTER (LCVCR).............................................................................78
14.1.1 T1 Operation.......................................................................................................................................78
14.1.2 E1 Operation.......................................................................................................................................78
14.2 P
ATH CODE VIOLATION COUNT REGISTER (PCVCR) ............................................................................80
14.2.1 T1 Operation.......................................................................................................................................80
14.2.2 E1 Operation.......................................................................................................................................80
14.3 F
RAMES OUT-OF-SYNC COUNT REGISTER (FOSCR)..............................................................................81
14.3.1 T1 Operation.......................................................................................................................................81
14.3.2 E1 Operation.......................................................................................................................................81
14.4 E-B
IT COUNTER (EBCR).........................................................................................................................82
15. DS0 MONITORING FUNCTION ...........................................................................................................83
16. SIGNALING OPERATION .....................................................................................................................85
16.1 R
ECEIVE SIGNALING ...............................................................................................................................85
16.1.1 Processor-Based Signaling.................................................................................................................85
16.1.2 Hardware-Based Receive Signaling ...................................................................................................86
16.2 T
RANSMIT SIGNALING.............................................................................................................................91
16.2.1 Processor-Based Mode.......................................................................................................................91
16.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode..........................................................95
16.2.3 Software Signaling Insertion-Enable Registers, T1 Mode..................................................................97
16.2.4 Hardware-Based Mode.......................................................................................................................97
17. PER-CHANNEL IDLE CODE GENERATION ....................................................................................98
17.1 I
DLE-CODE PROGRAMMING EXAMPLES..................................................................................................99
18. CHANNEL BLOCKING REGISTERS ................................................................................................103
19. ELASTIC STORES OPERATION........................................................................................................106
19.1 R
ECEIVE SIDE ........................................................................................................................................109
19.1.1 T1 Mode ............................................................................................................................................109
19.1.2 E1 Mode............................................................................................................................................109
19.2 T
RANSMIT SIDE .....................................................................................................................................109
19.2.1 T1 Mode ............................................................................................................................................110
19.2.2 E1 Mode............................................................................................................................................110
19.3 E
19.4 M
LASTIC STORES INITIALIZATION .........................................................................................................110
INIMUM DELAY MODE .......................................................................................................................110
20. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)...................................................111
21. T1 BIT-ORIENTED CODE (BOC) CONTROLLER..........................................................................112
21.1 T
RANSMIT BOC.....................................................................................................................................112
Transmit a BOC ..............................................................................................................................................112
21.2 R
ECEIVE BOC .......................................................................................................................................112
Receive a BOC ................................................................................................................................................112
22. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) ......................115
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22.1 M
22.2 M
22.3 M
ETHOD 1: HARDWARE SCHEME .........................................................................................................115
ETHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ..............................................115
ETHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ........................................118
23. HDLC CONTROLLERS ........................................................................................................................128
23.1 B
23.2 HDLC C
ASIC OPERATION DETAILS ..................................................................................................................128
ONFIGURATION........................................................................................................................128
23.2.1 FIFO Control....................................................................................................................................132
23.3 HDLC M
APPING....................................................................................................................................133
23.3.1 Receive..............................................................................................................................................133
23.3.2 Transmit............................................................................................................................................135
23.3.3 FIFO Information .............................................................................................................................140
23.3.4 Receive Packet-Bytes Available........................................................................................................140
23.3.5 HDLC FIFOs ....................................................................................................................................141
23.4 R
23.5 L
ECEIVE HDLC CODE EXAMPLE..........................................................................................................142
EGACY FDL SUPPORT (T1 MODE)......................................................................................................142
23.5.1 Overview...........................................................................................................................................142
23.5.2 Receive Section .................................................................................................................................142
23.5.3 Transmit Section ...............................................................................................................................144
23.6 D4/SLC-96 O
PERATION ........................................................................................................................144
24. LINE INTERFACE UNIT (LIU) ...........................................................................................................145
24.1 LIU O
24.2 R
PERATION ....................................................................................................................................145
ECEIVER ..............................................................................................................................................145
24.2.1 Receive Level Indicator and Threshold Interrupt.............................................................................146
24.2.2 Receive G.703 Synchronization Signal (E1 Mode)...........................................................................146
24.2.3 Monitor Mode ...................................................................................................................................146
24.3 T
RANSMITTER .......................................................................................................................................147
24.3.1 Transmit Short-Circuit Detector/Limiter..........................................................................................147
24.3.2 Transmit Open-Circuit Detector.......................................................................................................147
24.3.3 Transmit BPV Error Insertion ..........................................................................................................147
24.3.4 Transmit G.703 Synchronization Signal (E1 Mode).........................................................................147
24.4 MCLK P
24.5 J
ITTER ATTENUATOR.............................................................................................................................148
24.6 CMI (C
24.7 LIU C
24.8 R
24.9 C
ECOMMENDED CIRCUITS.....................................................................................................................158
OMPONENT SPECIFICATIONS...............................................................................................................160
RESCALER ...............................................................................................................................148
ODE MARK INVERSION) OPTION...............................................................................................148
ONTROL REGISTERS ....................................................................................................................149
25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................165
26. BERT FUNCTION ..................................................................................................................................172
26.1 S
26.2 M
26.3 BERT R
26.4 BERT R
26.5 BERT B
26.6 BERT E
TATUS ..................................................................................................................................................172
APPING ...............................................................................................................................................172
EGISTER DESCRIPTIONS ...........................................................................................................174
EPETITIVE PATTERN SET..........................................................................................................178
IT COUNTER .............................................................................................................................179
RROR COUNTER .......................................................................................................................180
27. PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................................182
27.1 N
UMBER-OF-ERRORS REGISTERS..........................................................................................................184
27.1.1 Number-of-Errors Left Register........................................................................................................185
28. INTERLEAVED PCM BUS OPERATION (IBO)...............................................................................186
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28.1 C
28.2 F
HANNEL INTERLEAVE .........................................................................................................................186
RAME INTERLEAVE..............................................................................................................................186
29. EXTENDED SYSTEM INFORMATION BUS (ESIB) .......................................................................189
30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ........................................................193
31. FRACTIONAL T1/E1 SUPPORT .........................................................................................................193
32. USER-PROGRAMMABLE OUTPUT PINS........................................................................................195
33. TRANSMIT FLOW CHARTS...............................................................................................................196
34. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................................201
34.1 D
34.2 I
34.3 T
34.4 B
34.5 B
34.6 I
ESCRIPTION .........................................................................................................................................201
NSTRUCTION REGISTER ........................................................................................................................204
EST REGISTERS....................................................................................................................................206
OUNDARY SCAN REGISTER.................................................................................................................206
YPASS REGISTER.................................................................................................................................206
DENTIFICATION REGISTER ...................................................................................................................206
35. FUNCTIONAL TIMING DIAGRAMS.................................................................................................210
35.1 T1 M
35.2 E1 M
ODE ...............................................................................................................................................210
ODE ...............................................................................................................................................215
36. OPERATING PARAMETERS ..............................................................................................................224
37. AC TIMING PARAMETERS AND DIAGRAMS ...............................................................................226
37.1 M
37.2 N
37.3 R
37.4 B
37.5 T
ULTIPLEXED BUS AC CHARACTERISTICS ..........................................................................................226
ONMULTIPLEXED BUS AC CHARACTERISTICS ...................................................................................229
ECEIVE-SIDE AC CHARACTERISTICS ..................................................................................................232
ACKPLANE CLOCK TIMING: AC CHARACTERISTICS .........................................................................235
RANSMIT AC CHARACTERISTICS ........................................................................................................236
38. MECHANICAL DESCRIPTION ..........................................................................................................239
38.1 LQFP (L) P
38.2 CSBGA (G) P
ACKAGE .............................................................................................................................239
ACKAGE ..........................................................................................................................240
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1.1 Table of Figures
Figure 3-1. Block Diagram.........................................................................................................................................15
Figure 3-2. Receive and Transmit LIU.......................................................................................................................16
Figure 3-3. Receive and Transmit Framer/HDLC......................................................................................................17
Figure 3-4. Backplane Interface .................................................................................................................................18
Figure 4-1. 10mm CSBGA Pin Configuration...........................................................................................................34
Figure 6-1. Programming Sequence ...........................................................................................................................41
Figure 8-1. Clock Map................................................................................................................................................47
Figure 16-1. Simplified Diagram of Receive Signaling Path .....................................................................................85
Figure 16-2. Simplified Diagram of Transmit Signaling Path....................................................................................91
Figure 20-1. CRC-4 Recalculate Method .................................................................................................................111
Figure 24-1. Typical Monitor Application ...............................................................................................................146
Figure 24-2. CMI Coding.........................................................................................................................................148
Figure 24-3. Basic Interface .....................................................................................................................................158
Figure 24-4. Protected Interface Using Internal Receive Termination.....................................................................159
Figure 24-5. E1 Transmit Pulse Template................................................................................................................161
Figure 24-6. T1 Transmit Pulse Template................................................................................................................161
Figure 24-7. Jitter Tolerance ....................................................................................................................................162
Figure 24-8. Jitter Tolerance (E1 Mode) ..................................................................................................................162
Figure 24-9. Jitter Attenuation (T1 Mode) ...............................................................................................................163
Figure 24-10. Jitter Attenuation (E1 Mode) .............................................................................................................163
Figure 24-11. Optional Crystal Connections............................................................................................................164
Figure 26-1. Simplified Diagram of BERT in Network Direction...........................................................................173
Figure 26-2. Simplified Diagram of BERT in Backplane Direction........................................................................173
Figure 28-1. IBO Example .......................................................................................................................................188
Figure 29-1. ESIB Group of Four DS2155s.............................................................................................................189
Figure 33-1 T1 Transmit Flow Chart.......................................................................................................................196
Figure 33-2 E1 Transmit Flow Chart.......................................................................................................................198
Figure 34-1. JTAG Functional Block Diagram ........................................................................................................201
Figure 34-2. TAP Controller State Diagram.............................................................................................................204
Figure 35-1. Receive-Side D4 Timing......................................................................................................................210
Figure 35-2. Receive-Side ESF Timing....................................................................................................................210
Figure 35-3. Receive-Side Boundary Timing (Elastic Store Disabled)....................................................................211
Figure 35-4. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...................................................211
Figure 35-5. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...................................................212
Figure 35-6. Transmit-Side D4 Timing....................................................................................................................212
Figure 35-7. Transmit-Side ESF Timing..................................................................................................................213
Figure 35-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)..........................................................213
Figure 35-9. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled).................................................214
Figure 35-10. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...............................................214
Figure 35-11. Receive-Side Timing .........................................................................................................................215
Figure 35-12. Receive-Side Boundary Timing (with Elastic Store Disabled)..........................................................215
Figure 35-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic Store Enabled) .........................216
Figure 35-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic Store Enabled) .........................216
Figure 35-15. Receive IBO Channel Interleave Mode Timing ................................................................................217
Figure 35-16. Receive IBO Frame Interleave Mode Timing....................................................................................218
Figure 35-17. G.802 Timing, E1 Mode Only...........................................................................................................219
Figure 35-18. Transmit-Side Timing........................................................................................................................219
Figure 35-19. Transmit-Side Boundary Timing (Elastic Store Disabled)................................................................220
Figure 35-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled).......................220
Figure 35-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled)........................221
Figure 35-22. Transmit IBO Channel Interleave Mode Timing...............................................................................222
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Figure 35-23. Transmit IBO Frame Interleave Mode Timing..................................................................................223
Figure 37-1. Intel Multiplexed Bus Read Timing (BTS = 0/MUX = 1)...................................................................227
Figure 37-2. Intel Multiplexed Bus Write Timing (BTS = 0/MUX = 1)..................................................................227
Figure 37-3. Motorola Multiplexed Bus Timing (BTS = 1/MUX = 1) ....................................................................228
Figure 37-4. Intel Nonmultiplexed Bus Read Timing (BTS = 0/MUX = 0) ............................................................230
Figure 37-5. Intel Nonmultiplexed Bus Write Timing (BTS = 0/MUX = 0) ...........................................................230
Figure 37-6. Motorola Nonmultiplexed Bus Read Timing (BTS = 1/MUX = 0).....................................................231
Figure 37-7. Motorola Nonmultiplexed Bus Write Timing (BTS = 1/MUX = 0)....................................................231
Figure 37-8. Receive-Side Timing ...........................................................................................................................233
Figure 37-9. Receive-Side Timing, Elastic Store Enabled .......................................................................................234
Figure 37-10. Receive Line Interface Timing ..........................................................................................................234
Figure 37-11 Receive Timing Delay RCLK to BPCLK..........................................................................................235
Figure 37-12. Transmit-Side Timing........................................................................................................................237
Figure 37-13. Transmit-Side Timing, Elastic Store Enabled....................................................................................238
Figure 37-14. Transmit Line Interface Timing.........................................................................................................238
1.2 Table of Tables
Table 4-A. Pin Description Sorted by Pin Number ....................................................................................................32
Table 5-A. Register Map Sorted by Address..............................................................................................................35
Table 9-A. T1 Alarm Criteria.....................................................................................................................................56
Table 10-A. E1 Sync/Resync Criteria ........................................................................................................................58
Table 10-B. E1 Alarm Criteria ...................................................................................................................................63
Table 14-A. T1 Line Code Violation Counting Options ............................................................................................78
Table 14-B. E1 Line-Code Violation Counting Options ............................................................................................78
Table 14-C. T1 Path Code Violation Counting Arrangements...................................................................................80
Table 14-D. T1 Frames Out-of-Sync Counting Arrangements ..................................................................................81
Table 16-A. Time Slot Numbering Schemes..............................................................................................................92
Table 17-A. Idle-Code Array Address Mapping........................................................................................................98
Table 17-B. GRIC and GTIC Functions...................................................................................................................100
Table 19-A. Elastic Store Delay After Initialization ................................................................................................110
Table 23-A. HDLC Controller Registers..................................................................................................................129
Table 24-A. Transformer Specifications ..................................................................................................................160
Table 27-A. Transmit Error-Insertion Setup Sequence ............................................................................................182
Table 27-B. Error Insertion Examples......................................................................................................................184
Table 34-A. Instruction Codes for IEEE 1149.1 Architecture .................................................................................205
Table 34-B. ID Code Structure.................................................................................................................................206
Table 34-C. Device ID Codes...................................................................................................................................206
Table 34-D. Boundary Scan Control Bits.................................................................................................................207
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2. DATA SHEET REVISION HISTORY
10-9-03 Add revision history table: The previous version of the DS2155 data sheet (12-06-02) did
not incorporate a revision history table and did not describe new features added to B1
revision of the DS2155.
Add CSBGA package information to Ordering Information table on front page
Add CSBGA package thermal characteristics to Operating Parameters section
Add Transmit Line Build Out Control register (TLBC) description
Add Transmit Line Build Out Control register (TLBC) to Port Map
Add Transmit Line Build Out Control register (TLBC) description to LIU TRANSMIT
Correct Device ID in Device Identification Register
Correct Device ID in JTAG ID Code table
Correct minimum value for t
Correct minimum value for t
Corrections to AC CHARACTERISTICS: TRANSMIT SIDE timing table.
Corrections to AC CHARACTERISTICS: RECEIVE SIDE timing table.
Correct Transmit Signaling Registers (E1 Mode, CCS Format) table in Transmit Signaling
The definition of the EGL bit in the LIC1 register has been corrected for both T1 and E1
THE FOLLOWING WERE INADVERTENTLY REMOVED FROM THE
PREVIOUS VERSION OF THE DS2155 DATA SHEET
section
THE FOLLOWING ARE CORRECTIONS TO ERRORS IN THE PREVIOUS
VERSION OF THE DS2155 DATA SHEET
in AC CHARACTERISTICS: MULTIPLEXED
DHW
PARALLEL PORT table. t
PARALLEL PORT table. t
was changed from 5ns to 0ns
DHW
in AC CHARACTERISTICS: MULTIPLEXED
DDR
was changed from unstated to 20ns
DDR
1. tCP, tCH, tCL, tLP, tLH, tLL, and tSP typical values have been restated to reflect various IBO
modes.
2. tCH, t
3. tSP, t
4. t
LL
minimum values have been changed from 75ns to 22ns.
D3
, t
CL, tLH
minimum values have been changed from 75ns to 20ns.
LL
minimum values have been changed from 50ns to 20ns.
1. tCP, tCH, tCL, tLP, tLH, tLL, and tSP typical values have been restated to reflect various IBO
modes.
2. t
, t
CH
3. tSH, t
4. t
SH
5. t
D3, tD4
minimum values have been changed from 75ns to 20ns.
CL,
minimum values have been changed from 50ns to 20ns.
SL
, t
typical values have been added.
SL
minimum values have been changed from 50ns to 22ns.
section
mode.
T1 Mode: EGL = 1 was changed from 15dB to –15dB
E1 Mode: EGL = 0 was changed from –10dB to –12dB
THE FOLLOWING ARE FORMAT CHANGES AND ADDED OR REMOVED
TEXT, TABLES OR DIAGRAMS
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Replace X* format for showing active low signals with X
Remove redundant statements about “multiport configurations” in Interrupt Handling section
Remove BASIC NETWORK CONNECTIONS figure in LINE INTERFACE UNIT section
Add “Simplified Diagram of BERT in Network Direction” figure to BERT section
Add “Simplified Diagram of BERT in Backplane Direction” figure to BERT section
Add Receive Signaling Registers (E1 Mode, CCS Format) table to Receive Signaling section
Add GRIC and GTIC function table to IAAR register
Changed Table of contents to include table of figures and table of tables.
Add note for FASRC bit.
Add T1 and E1 Transmit Flow Chart.
Added RCLK to BPCLK timing diagram.
THE FOLLOWING ARE NEW FEATURES AVAILABLE ON THE DS2155 REV B1
AND ARE EXPLAINED IN THE BODY OF THE DATA SHEET
Add FRAS0, TCCS, RCCS and GRSRE bits to Signaling Control Register (SIGCR)
Add section on AIS-CI and RAI-CI Generation and Detection
Add RAIS-CI status bit to Status Register 4 (SR4) and Interrupt Mask Register 4 (IMR4)
Add RAIS-CI status bit to Status Register 4 (SR4)
Add TRAI-CI control bit to T1 Common Control Register 1 (TCCR1)
Add TAIS-CI control bit to T1 Common Control Register 1 (TCCR1)
Add Pseudorandom 2E9-1 pattern to PS0, PS1 and PS2 bit description in Bert Control
Register 1 (BCR1)
Add BD bit to Information Register 2 (INFO2)
Add ILUT status bit to Status Register 1 (SR1) and Interrupt Mask Register 1 (IMR1)
Add INTDIS and TMSS bits to Common Control Register 3 (CCR3)
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3. MAIN FEATURES
The DS2155 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 SCTs plus
many new features.
General
§ Programmable output clocks for fractional T1, E1,
H0, and H12 applications
§ Interleaving PCM bus operation
§ 8-bit parallel control port, multiplexed or
nonmultiplexed, Intel or Motorola
§ IEEE 1149.1 JTAG-Boundary Scan
§ 3.3V supply with 5V tolerant inputs and outputs
§ Pin compatible with DS2156, DS2152/DS2154,
and DS21x5Y SCT family
§ Signaling System 7 Support
§ RAI-CI, AIS-CI support
§ 100-pin LQFP (14mm x 14mm) (DS2155L)
§ 100-pin CSBGA (10mm x 10mm) (DS2155G)
§ 3.3V supply with 5V tolerant inputs and outputs
§ Evaluation kits
§ IEEE 1149.1 JTAG boundary scan
§ Driver source code available from the factory
Line Interface
§ Requires only a 2.048MHz master clock for both
E1 and T1 operation with the option to use
1.544MHz for T1 operation
§ Fully software configurable
§ Short-haul and long-haul applications
§ Automatic receive sensitivity adjustments
§ Ranges include 0 to 43dB or 0 to 12dB for E1
applications and 0 to 13dB or 0 to 36dB for T1
applications
§ Receive level indication in 2.5dB steps from
-42.5dB to -2.5dB
§ Internal receive termination option for 75", 100",
and 120" lines
§ Internal transmit termination option for 75", 100",
and 120" lines
§ Monitor application gain settings of 20dB, 26dB,
and 32dB
§ G.703 receive synchronization-signal mode
§ Flexible transmit waveform generation
§ T1 DSX-1 line buildouts
§ T1 CSU line buildouts of -7.5dB, -15dB, and
-22.5dB
§ E1 waveforms include G.703 waveshapes for
both 75" coax and 120" twisted cables
§ AIS generation independent of loopbacks
§ Alternating ones and zeros generation
§ Square-wave output
§ Open-drain output option
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§ NRZ format option
§ Transmitter power-down
§ Transmitter 50mA short-circuit limiter with
current-limit-exceeded indication
§ Transmit open-circuit-detected indication
§ Line interface function can be completely
decoupled from the framer/formatter
Clock Synthesizer
§ Output frequencies include 2.048MHz, 4.096MHz,
8.192MHz, and 16.384MHz
§ Derived from recovered receive clock
Jitter Attenuator
§ 32-bit or 128-bit crystal-less jitter attenuator
§ Requires only a 2.048MHz master clock for both
E1 and T1 operation with the option to use
1.544MHz for T1 operation
§ Can be placed in either the receive or transmit path
or disabled
§ Limit trip indication
Framer/Formatter
§ Fully independent transmit and receive
functionality
§ Full receive and transmit path transparency
§ T1 framing formats include D4 (SLC-96) and ESF
§ Detailed alarm and status reporting with optional
interrupt support
§ Large path and line error counters for:
– T1: BPV, CV, CRC6, and framing bit errors
– E1: BPV, CV, CRC4, E-bit, and frame
alignment errors
§ Timed or manual update modes
§ DS1 idle code generation on a per-channel basis in
both transmit and receive paths
– User-defined
– Digital milliwatt
§ ANSI T1.403-1998 Support
§ RAI-CI detection and generation
§ AIS-CI detection and generation
§ E1ETS 300 011 RAI generation
§ G.965 V5.2 link detect
§ Ability to monitor one DS0 channel in both the
transmit and receive paths
§ In-band repeating pattern generators and detectors
– Three independent generators and detectors
– Patterns from 1 to 8 bits or 16 bits in length
§ RCL, RLOS, RRA, and RAIS alarms interrupt on
change-of-state
§ Flexible signaling support
– Software or hardware based
– Interrupt generated on change of signaling data
– Receive signaling freeze on loss-of-sync,
carrier loss, or frame slip
§ Addition of hardware pins to indicate carrier loss
and signaling freeze
§ Automatic RAI generation to ETS 300 011
specifications
§ Access to Sa and Si bits
§ Option to extend carrier loss criteria to a 1ms
period as per ETS 300 233
§ Japanese J1 support
– Ability to calculate and check CRC6 according
to the Japanese standard
– Ability to generate Yellow Alarm according to
the Japanese standard
TDM Bus
§ Dual two-frame independent receive and transmit
elastic stores
– Independent control and clocking
– Controlled slip capability with status
– Minimum delay mode supported
§ 16.384MHz maximum backplane burst rate
§ Supports T1 to CEPT (E1) conversion
§ Programmable output clocks for fractional T1, E1,
H0, and H12 applications
§ Interleaving PCM bus operation
§ Hardware signaling capability
– Receive signaling reinsertion to a backplane
multiframe sync
– Availability of signaling in a separate PCM
data stream
– Signaling freezing
§ Ability to pass the T1 F-bit position through the
elastic stores in the 2.048MHz backplane mode
§ Access to the data streams in between the
framer/formatter and the elastic stores
§ User-selectable synthesized clock output
HDLC Controllers
§ Two independent HDLC controllers
§ Fast load and unload features for FIFOs
§ SS7 support for FISU transmit and receive
§ Independent 128-byte Rx and Tx buffers with
interrupt support
§ Access FDL, Sa, or single/multiple DS0 channels
§ DS0 access includes Nx64 or Nx56
§ Compatible with polled or interrupt driven
environments
DS2155
§ Bit-oriented code (BOC) support
11 of 240
Test and Diagnostics
§ Programmable on-chip bit error-rate testing
§ Pseudorandom patterns including QRSS
§ User-defined repetitive patterns
§ Daly pattern
§ Error insertion single and continuous
§ Total bit and errored bit counts
§ Payload error insertion
§ Error insertion in the payload portion of the T1
frame in the transmit path
§ Errors can be inserted over the entire frame or
selected channels
§ Insertion options include continuous and absolute
number with selectable insertion rates
§ F-bit corruption for line testing
§ Loopbacks: remote, local, analog, and per-channel
loopback
Extended System Information Bus
§ Host can read interrupt and alarm status on up to 8
ports with a single bus read
User-Programmable Output Pins
§ Four user-defined output pins for controlling
external logic
Control Port
§ 8-bit parallel control port
§ Multiplexed or nonmultiplexed buses
§ Intel or Motorola formats
§ Supports polled or interrupt environments
§ Software access to device ID and silicon revision
§ Software reset supported
– Automatic clear on power-up
§ Hardware reset pin
The DS2155 is compliant with the following standards:
ANSI: T1.403-1995, T1.231–1993, T1.408
AT&T: TR54016, TR62411
ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161
ITU-T: Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer
Specification
ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4
Japanese: JTG.703, JTI.431, JJ-20.11 (CMI Coding Only)
DS2155
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DS2155
3.1 Functional Description
The DS2155 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and longhaul applications. The DS2155 is composed of an LIU, framer, HDLC controllers, and a TDM backplane
interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The
DS2155 is pin and software compatible with the DS2156.
The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct
source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line
buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes
G.703 waveshapes for both 75" coax and 120" twisted cables. The receive interface provides network
termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to
the incoming signal and can be programmed for 0 to 43dB or 0 to 12dB for E1 applications and 0 to 30dB
or 0 to 36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or
received signal. The crystal-less jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1
applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be placed in either
transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for interfacing to
optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane
interface section. The framer inserts the appropriate synchronization framing patterns, alarm information,
calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI
line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the
data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and
frame-sync signals to the backplane interface section.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and
receive data through the framer block. The HDLC controllers can be assigned to any time slot, group of
time slots, portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte FIFOs, thus
reducing the amount of processor overhead required to manage the flow of data. In addition, built-in
support for reducing the processor time is required in SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system.
Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1
network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also
manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up
to eight transceivers to share a high-speed backplane.
The parallel port provides access for control and configuration of the DS2155’s features. The extended
system information bus (ESIB) function allows up to eight transceivers to be accessed by a single read for
interrupt status or other user-selectable alarm status information. Diagnostic capabilities include
loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and
detection.
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DS2155
Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In
each 125ms frame there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent
first followed by channel 1. Each channel is made up of eight bits that are numbered 1 to 8. Bit number 1
is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The term “locked” is
used to refer to two clock signals that are phase- or frequency-locked or derived from a common clock
(i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
Throughout this data sheet, the following abbreviations are used:
B8ZS Bipolar with 8 Zero Substitution
BOC Bit-Oriented Code
CRC Cyclical Redundancy Check
D4 Superframe (12 frames per multiframe) Multiframe Structure
ESF Extended Superframe (24 frames per multiframe) Multiframe Structure
FDL Facility Data Link
FPS Framing Pattern Sequence in ESF
Fs Signaling Framing Pattern in D4
Ft Terminal Framing Pattern in D4
HDLC High-Level Data Link Control
MF Multiframe
SLC–96 Subscriber Loop Carrier—96 Channels
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DS2155
3.2 Block Diagram
Figure 3-1 shows a simplified block diagram featuring the major components of the DS2155. Details are
shown in subsequent figures. The block diagram is divided into three functional blocks: LIU, FRAMER,
and BACKPLANE INTERFACE.
Figure 3-1. Block Diagram
CLOCK
CLOCK
ADAPTER
RX
LIU
EXTERNAL ACCESS
TO RECEIVE SIGNALS
MUX
HDB3 / B8ZS
SYNC
SINGALING
ALARM DET
HDLCs
BACKPLANE
CLOCK SYNTH
BACKPLANE
INTERFACE
T1/E1/J1
NETWORK
TX
LIU
LIU
LOCAL LOOPBACK
JITTER ATTENUATOR
EXTERNAL ACCESS
TO TRANSMIT SIGNALS
REMOTE LOOPBACK
MUX
FRAMER LOOPBACK
FRAMER
SINGALING
ALARM GEN
HDLCs
CRC GEN
HDB3 / B8ZS
PAYLOAD LOOPBACK
FRAMER BACKPLANE
CIRCUIT
BACKPLANE
INTERFACE
JTAG ESIB
HOST INTERFACE
15 of 240
Figure 3-2. Receive and Transmit LIU
8XCLK
XTALD
MCLK
DS2155
RPOSO
RNEGO
RCLKO
RNEGI
RPOSI
RCLKI
RCL
RRING
RTIP
TRING
TTIP
VCO / PLL
32.768MHz
RECEIVE
LINE I/F
LOCAL LOOPBACK
TRANSMIT
LINE I/F
JITTER ATTENUATOR
OR RECEIVE PATH
TRANSMIT
MUX
TPOSI
LIUC
TCLKI
MUX
REMOTE LOOPBACK
TNEGO
TNEGI
TPOSO
TCLKO
JACLK
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
16 of 240
Figure 3-3. Receive and Transmit Framer/HDLC
REC
HDLC #1
128 Byte
FIFO
REC
HDLC #2
128 Byte
FIFO
DS2155
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
DATA
FRAMER LOOPBACK
RECEIVE
FRAMER
TRANSMIT
FRAMER
CLOCK
SYNC
SYNC
CLOCK
DATA
MAPPER MAPPER
MAPPER
XMIT
HDLC #1
128 Byte
FIFO
MAPPER
XMIT
HDLC #2
128 Byte
FIFO
PAYLOAD LOOPBACK
DATA
CLOCK
SYNC
SYNC
CLOCK
DATA
17 of 240
Figure 3-4. Backplane Interface
DS2155
DATA
CLOCK
Sa BIT/FDL
EXTRACTION
SIGNALING
BUFFER
ELASTIC
STORE
RLINK
RLCLK
RSIG
RSIGFR
RSYSCLK
RSER
RCLK
RSYNC
SYNC
RMSYNC
RFSYNC
RDATA
RCHCLK
RCHBLK
TSER
TSIG
TSSYNC
SYNC
DATA
Sa/FDL
INSERT
ELASTIC
STORE
CHANNEL
TIMING
SIGNALING
BUFFER
CLOCK
JACLK
CHANNEL
TIMING
TCLK
MUX
TSYSCLK
TSYNC
TESO
TDATA
TLCLK
TLINK
TCHCLK
TCHBLK
TCLK
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DS2155
4. PIN FUNCTION DESCRIPTION
4.1 Transmit Side
Signal Name:
Signal Description:
Signal Type:
A 1.544MHz (T1) or a 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter.
TCLK can be internally sourced from MCLK. This is the most flexible method and requires only a single clock
signal for both T1 or E1. If internal sourcing is used, then the TCLK pin should be connected low.
Signal Name:
Signal Description:
Signal Type:
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to
output a gated transmit bit clock on a per-channel basis. Synchronous with TCLK when the transmit-side elastic
store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallelto-serial conversion of channel data.
Signal Name:
Signal Description:
Signal Type:
A user-programmable output that can be forced high or low during any of the channels. Synchronous with TCLK
when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is
enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are
used such as Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN–PRI. Also useful for locating
individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
Signal Name:
Signal Description:
Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic
store function is enabled. Should be connected low in applications that do not use the transmit-side elastic store.
See Section 28
for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.
TCLK
Transmit Clock
Input
TSER
Transmit Serial Data
Input
TCHCLK
Transmit Channel Clock
Output
TCHBLK
Transmit Channel Block
Output
TSYSCLK
Transmit System Clock
Input
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DS2155
Signal Name:
Signal Description:
Signal Type:
TLCLK
Transmit Link Clock
Output
Demand clock for the transmit link data [TLINK] input.
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
Signal Description:
Signal Type:
TLINK
Transmit Link Data
Input
If enabled, this pin is sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or
the Fs-bit position (D4), or the Z-bit position (ZBTSI) or any combination of the Sa-bit positions (E1).
Signal Name:
Signal Description:
Signal Type:
TSYNC
Transmit Sync
Input/Output
A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. Can be programmed to
output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set by
IOCR1.3 to output double-wide pulses at signaling frames in T1 mode.
Signal Name:
Signal Description:
Signal Type:
TSSYNC
Transmit System Sync
Input
Only used when the transmit-side elastic store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Should be connected low in applications that do not use the transmit-side elastic
store.
Signal Name:
Signal Description:
Signal Type:
TSIG
Transmit Signaling Input
Input
When enabled, this input samples signaling bits for insertion into outgoing PCM data stream. Sampled on the
falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
TESO
Transmit Elastic Store Data Output
Output
Updated on the rising edge of TCLK with data out of the transmit-side elastic store whether the elastic store is
enabled or not. This pin is normally connected to TDATA.
Signal Name:
Signal Description:
Signal Type:
TDATA
Transmit Data
Input
Sampled on the falling edge of TCLK with data to be clocked through the transmit-side formatter. This pin is
normally connected to TESO.
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DS2155
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed
to source NRZ data by the output data format (IOCR1.0) control bit. This pin is normally connected to TPOSI.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally
connected to TNEGI.
Signal Name:
Signal Description:
Signal Type:
Buffered clock that is used to clock data through the transmit-side formatter (i.e., either TCLK or RCLKI). This pin
is normally connected to TCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected
to TPOSO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected
to TNEGO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications.
Signal Name:
Signal Description:
Signal Type:
Line interface transmit clock. Can be internally connected to TCLKO by connecting the LIUC pin high.
TPOSO
Transmit Positive-Data Output
Output
TNEGO
Transmit Negative-Data Output
Output
TCLKO
Transmit Clock Output
Output
TPOSI
Transmit Positive-Data Input
Input
TNEGI
Transmit Negative-Data Input
Input
TCLKI
Transmit Clock Input
Input
21 of 240
DS2155
4.2 Receive Side
Signal Name:
Signal Description:
Signal Type:
T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a
frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.
Signal Name:
Signal Description:
Signal Type:
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
Signal Description:
Signal Type:
1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK
when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Useful for parallel-to-serial conversion of channel data.
Signal Name:
Signal Description:
Signal Type:
A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels.
Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the
receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN–PRI.
Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and
for per-channel conditioning. See Section 18
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe
(IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.6, RSYNC can also be set to
output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin
can be enabled to be an input through IOCR1.4, at which a frame or multiframe boundary pulse is applied.
Signal Name:
Signal Description:
RLINK
Receive Link Data
Output
RLCLK
Receive Link Clock
Output
RCLK
Receive Clock
Output
RCHCLK
Receive Channel Clock
Output
RCHBLK
Receive Channel Block
Output
for details.
RSER
Receive Serial Data
Output
RSYNC
Receive Sync
Input/Output
RFSYNC
Receive Frame Sync
22 of 240
Signal Type:
An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries.
Output
DS2155
23 of 240
DS2155
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is
output at this pin that identifies multiframe boundaries.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLK with the data out of the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store function is
enabled. Should be connected low in applications that do not use the receive-side elastic store. See Section 28
details on 4.096MHz and 8.192MHz operation using the IBO.
Signal Name:
Signal Description:
Signal Type:
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
RMSYNC
Receive Multiframe Sync
Output
RDATA
Receive Data
Output
RSYSCLK
Receive System Clock
Input
for
RSIG
Receive Signaling Output
Output
Signal Name:
Signal Description:
Signal Type:
A dual function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle
high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not
been toggled for 5ms.
Signal Name:
Signal Description:
Signal Type:
Set high when the line interface detects a carrier loss.
Signal Name:
Signal Description:
Signal Type:
Set high when the signaling data is frozen by either automatic or manual intervention. Used to alert downstream
equipment of the condition.
Signal Name:
Signal Description:
Signal Type:
A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
RLOS/LOTC
Receive Loss-of-Sync/Loss-of-Transmit Clock
Output
RCL
Receive Carrier Loss
Output
RSIGF
Receive Signaling Freeze
Output
BPCLK
Backplane Clock
Output
24 of 240
DS2155
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally connected to
RPOSI.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally
connected to RNEGI.
Signal Name:
Signal Description:
Signal Type:
Buffered recovered clock from the network. This pin is normally connected to RCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI
can be connected together for an NRZ interface. Can be internally connected to RPOSO by connecting the LIUC
pin high.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI
can be connected together for an NRZ interface. Can be internally connected to RNEGO by connecting the LIUC
pin high.
RPOSO
Receive Positive-Data Output
Output
RNEGO
Receive Negative-Data Output
Output
RCLKO
Receive Clock Output
Output
RPOSI
Receive Positive-Data Input
Input
RNEGI
Receive Negative-Data Input
Input
Signal Name:
Signal Description:
Signal Type:
Clock used to clock data through the receive-side framer. This pin is normally connected to RCLKO. Can be
internally connected to RCLKO by connecting the LIUC pin high.
RCLKI
Receive Clock Input
Input
25 of 240
DS2155
4.3 Parallel Control Port Pins
Signal Name:
Signal Description:
Signal Type:
Flags host controller during conditions and events defined in the status registers. Active-low, open-drain output.
Signal Name:
Signal Description:
Signal Type:
A dual function pin. A 0-to-1 transition issues a hardware reset to the DS2155 register set. A reset clears all
configuration registers. Configuration register contents are set to 0. Leaving TSTRST high three-states all output
and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing.
Signal Name:
Signal Description:
Signal Type:
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
Signal Description:
Signal Type:
In nonmultiplexed bus operation (MUX = 0), these serve as the data bus. In multiplexed bus operation (MUX = 1),
these pins serve as an 8-bit multiplexed address/data bus.
Signal Name:
Signal Description:
Signal Type:
In nonmultiplexed bus operation (MUX = 0), these serve as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be connected low.
Signal Name:
Signal Description:
Signal Type:
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the
RD (DS), ALE (AS), and WR (R/W) pins.
If BTS = 1, then these pins assume the function listed in parentheses ().
Signal Name:
Signal Description:
Signal Type:
In Intel mode, RD determines when data is read from the device. In Motorola mode, DS is used to write to the
device. See Bus Timing Diagrams.
INT
Interrupt
Output
TSTRST
Three-State Control and Device Reset
Input
MUX
Bus Operation
Input
AD0 to AD7
Data Bus [D0 to D7] or Address/Data Bus
Input/Output
A0 to A6
Address Bus
Input
BTS
Bus Type Select
Input
RD (DS)
Read Input, Data Strobe
Input
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DS2155
Signal Name:
Signal Description:
Signal Type:
Must be low to read or write to the device. CS is an active-low signal.
Signal Name:
Signal Description:
Signal Type:
In nonmultiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive-going edge.
Signal Name:
Signal Description:
Signal Type:
WR is an active-low signal.
CS
Chip Select
Input
ALE(AS)/A7
Address Latch Enable (Address Strobe) or A7
Input
WR (R/W)
Write Input(Read/Write)
Input
4.4 Extended System Information Bus
Signal Name:
Signal Description:
Signal Type:
Used to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Section 29
more details.
Signal Name:
Signal Description:
Signal Type:
Used to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Section 29
more details.
Signal Name:
Signal Description:
Signal Type:
Used to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Section 29
more details.
ESIBS0
Extended System Information Bus Select 0
Input/Output
for
ESIBS1
Extended System Information Bus Select 1
Input/Output
for
ESIBRD
Extended System Information Bus Read
Input/Output
for
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DS2155
4.5 User Output Port Pins
Signal Name:
Signal Description:
Signal Type:
This output port pin can be set low or high by the CCR4.0 control bit. This pin is forced low on power-up and after
any device reset.
Signal Name:
Signal Description:
Signal Type:
This output port pin can be set low or high by the CCR4.1 control bit. This pin is forced low on power-up and after
any device reset.
Signal Name:
Signal Description:
Signal Type:
This output port pin can be set low or high by the CCR4.2 control bit. This pin is forced low on power-up and after
any device reset.
Signal Name:
Signal Description:
Signal Type:
This output port pin can be set low or high by the CCR4.3 control bit. This pin is forced low on power-up and after
any device reset.
UOP0
User Output Port 0
Output
UOP1
User Output Port 1
Output
UOP2
User Output Port 2
Output
UOP3
User Output Port 3
Output
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DS2155
4.6 JTAG Test Access Port Pins
Signal Name:
Signal Description:
Signal Type:
JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from
low to high. This action sets the device into the JTAG DEVICE ID mode. Normal device operation is restored by
pulling JTRST low. JTRST is pulled high internally by a 10k" resistor operation.
Signal Name:
Signal Description:
Signal Type:
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined
IEEE 1149.1 states. This pin has a 10k" pullup resistor.
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k" pullup
resistor.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be
left unconnected.
JTRST
IEEE 1149.1 Test Reset
Input
JTMS
IEEE 1149.1 Test Mode Select
Input
JTCLK
IEEE 1149.1 Test Clock Signal
Input
JTDI
IEEE 1149.1 Test Data Input
Input
JTDO
IEEE 1149.1 Test Data Output
Output
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DS2155
4.7 Line Interface Pins
Signal Name:
Signal Description:
Signal Type:
A (50ppm) clock source is applied at this pin. This clock is used internally for both clock/data recovery and for the
jitter attenuator for T1 and E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD
instead of the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using
the DS2155 in T1-only operation, a 1.544MHz (50ppm) clock source can be used.
Signal Name:
Signal Description:
Signal Type:
A quartz crystal of 2.048MHz (optional 1.544MHz in T1-only operation) can be applied across MCLK and
XTALD instead of a clock source at MCLK. Leave open circuited if a clock source is applied at MCLK.
Signal Name:
Signal Description:
Signal Type:
An 8x clock that is locked to the recovered network clock provided from the clock/data recovery block (if
the jitter attenuator is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is
enabled on the transmit side).
Signal Name:
Signal Description:
Signal Type:
Connect low to separate the line interface circuitry from the framer/formatter circuitry and activate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Connect high to connect the line interface circuitry to the
framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is
connected high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be connected low.
Signal Name:
Signal Description:
Signal Type:
Analog inputs for clock recovery circuitry. These pins connect through a 1:1 transformer to the network. See
Section 24
for details.
Signal Name:
Signal Description:
Signal Type:
Analog line driver outputs. These pins connect through a 1:2 step-up transformer to the network. See Section 24 for
details.
MCLK
Master Clock Input
Input
XTALD
Quartz Crystal Driver
Output
8XCLK
Eight Times Clock (8x)
Output
LIUC
Line Interface Connect
Input
RTIP and RRING
Receive Tip and Ring
Input
TTIP and TRING
Transmit Tip and Ring
Output
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