Dallas Semiconductor DS2141AQN, DS2141AQ, DS2141AN, DS2141A Datasheet

1 of 39 112099

FEATURES

 DS1/ISDN-PRI framing transceiver
 Frames to D4, ESF, and SLC-96 formats
 Parallel control port
 Onboard, dual two-frame elastic store slip

buffers

 Extracts and inserts robbed-bit signaling
 Programmable output clocks
 Onboard FDL support circuitry
 5V supply; low-power CMOS
 Available in 40-pin DIP and 44-pin PLCC

(DS2141Q)

 Compatible with DS2186 Transmit Line

Interface, DS2187 Receive Line Interface,
DS2188 Jitter Attenuator, DS2290 T1
Isolation Stik, and DS2291 T1 Long Loop
Stik

PIN ASSIGNMENT

DESCRIPTION

The DS2141A is a comprehensive, software-driven T1 framer. It is meant to act as a slave or coprocessor
to a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to
handle many T1 lines. The DS2141A is very flexible and can be configured into numerous orient ations
via software. The software orientation of the device allows the user to modify their design to conform to
future T1 specification changes. The controller contains a set of 62 8-bit internal registers which the user
can access. These internal registers are used to configure the device and obtain inform ation from the T1

DS2141

A

T1 Controlle

r

www.dalsemi.com

40-Pin DIP (600-mil)

13

39

TCHCLK

TNEG

AD1
AD2

AD3
AD4
AD5

AD6

BTS

AD7

VDD

TLCLK
INT1
INT2
RLOS/LOTC
TCHBLK
RCHBLK
LI CS
LI CLK

LI SDI

RNEG

SYSCLK

1
2

3
4

5
6

7
8

9
10

11
12

14

40

38
37

36
35

34
33

32
31

30
29

27

28

TSER

TPOS

AD0

TCLK

TSYNC
TLINK

19

RD(DS

)

CS

ALE

(AS)WR(

R/W

)

VSS

RLINK

RPOS
RSYNC
RSER

RCHCLK

RLCLK

RCLK

15
16

17
18

20

26
25

24
23

21

22

INT2

AD0
AD1
AD2
AD3
AD4
AD5

RLOS/LOTC
TCHBLK
RCHBLK
LI_CS
LI_CLK
LI_SDI

AD6

NC

TNEG

TPOS

TCHCLK

TSER

TCLK

VDD

TSYNC

NC

CS

ALE(AS)

WR(R/W)

RLIN

K

VSS

RLCL

K

39
38
37
36
35
34

33

7
8
9
10
11
12
13

6 5 4 3 2 1 44 43 42 41 40

18 19 20 21 22 2 3 24 25 26 27 2 8

AD7
BTS

RD(DS)

NC

TLINK

TLCLK

INT1

RCL

K

RCHCL

K

RSE

R

RSYNC

14
15
16
17

NC
SYSCLK
RNEG
RPOS

32

31
30

29

44-PIN PLCC

DS2141A

2 of 39

link. The device fully meets all of the latest T1 specifications including ANSI T1.403-1989, AT&T TR
62411 (12-90), and CCITT G.704 and G.706.

1.0 INTRODUCTION

The DS2141A T1 Controller has four main sections: the receive side, the transmit side, the line interface
controller, and the parallel control port. See the block diagram below. On the receive side, the device will
clock in the serial T1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and
multiframe patterns and establish their respective positions. This information will be used by the rest of
the receive side circuitry.

The DS2141A is an “off-line” framer, which means that all of the T1 serial stream that goes into the
device will come out of it unchanged. Once the T1 data has been framed to, the robbed-bit signaling data
and FDL can be extracted. The 2-frame elastic stores can either be enabled or bypassed.

The transmit side clocks in the unframed T1 stream at TSER and adds in the framing pattern, the robbed­bit signaling, and the FDL. The line interface control port will update line interface devices that contain a
serial port. The parallel control port contains a multiplexed address and data structure which can be
connected to either a microcontroller or microprocessor.

DS2141A BLOCK DIAGRAM

DS2141A

3 of 39

DS2141A FEATURES

 Parallel control port
 Large error counters
 Onboard dual 2-frame elastic store
 FDL support circuitry
 Robbed-bit signaling extraction and insertion
 Programmable output clocks
 Fully independent transmit and receive sections
 Frame sync generation
 Error-tolerant yellow and blue alarm detection
 Output pin test mode
 Payload loopback capability
 SLC-96 support
 Remote loop up/down code detection
 Loss of transmit clock detection
 Loss of receive clock detection
 1's density violation detection

PIN DESCRIPTION Table 1

PIN SYMBOL TYPE DESCRIPTION

1TCLK ITransmit Clock. 1.544 MHz primary clock.
2TSER ITransmit Serial Data. Transmit NRZ serial data, sampled on the

falling edge of TCLK.

3TCHCLKOTransmit Channel Clock. 192 kHz clock which pulses high during

the LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking

clocks in DDS applications. See Section 13 for timing details.
4
5

TPOS

TNEG

O Transmit Bipolar Data. Updated on rising edge of TCLK.

6-13 AD0-AD7 I/O Address/Data Bus. An 8-bit multiplexed address/data bus.

14 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap

low to select Intel bus timing. This pin controls the function of

RD (DS), ALE(AS), and WR (R/W ) pins. If BTS=1, then these pins

assume the function listed in parentheses ().

15

RD (DS)

I

Read Input (Data Strobe).

16 CS I Chip Select. Must be low to read or write the port.
17 ALE(AS) I Address Latch Enable (Address Strobe). A positive-going edge

serves to demultiplex the bus.

18

WR (R/ W )

I

Write Input (Read/Write).

19 RLINK O Receive Link Data. Updated with either FDL data (ESF) or Fs-bits

(D4) or Z-bits (ZBTSI) one RCLK before the start of a frame. See

Section 13 for timing details.

20 VSS - Signal Ground. 0.0 volts.
21 RLCLK O Receive Link Clock. 192 kHz clock which pulses high during the

LSB of each channel. Useful for parallel-to-serial conversion of

channel data, locating robbed-bit signaling bits, and for blocking

clocks in DDS applications. See Section 13 for timing details.

22 RCLK I Receive Clock. 1.544 MHz primary clock.

DS2141A

4 of 39

PIN SYMBOL TYPE DESCRIPTION

23 RCHCLK O Receive Channel Clock. 192 kHz clock which pulses high during

the LSB of each channel. Useful for parallel-to-serial conversion of

channel data, locating robbed-bit signaling bits, and for blocking

clocks in DDS applications. See Section 13 for timing details.

24 RSER O Receive Serial Data. Received NRZ serial data; updated on rising

edges of RCLK.

25 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this

pin which identifies either frame (RCR2.4=0) or multiframe

boundaries (RCR2.4=1). If set to output frame boundaries, then via

RCR2.5, RSYNC can also be set to output double-wide pulses on

signaling frames. If the elastic store is enabled via the CCR1.2, then

this pin can be enabled to be an input via RCR2.3 at which a frame

boundary pulse is applied. See Section 13 for timing details.

26
27

RPOS

RNEG

I Receive Bipolar Data Inputs. Sampled on falling edge of RCLK.

Tie together to receive NRZ data and disable bipolar violation

monitoring circuitry.

28 SYSCLK I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when

the elastic store function is enabled via the CCR. Should be tied low

in applications that do not use the elastic store.

29 LI_SDI O Serial Port Data for the Line Interface. Connects directly to the

SDI input pin on the line interface.

30 LI_CLK O Serial Port Clock for the Line Interface. Connects directly to the

SCLK input pin on the line interface.

31

LI_CS

O Serial Port Chip Select for the Line Interface. Connects directly

to the CS input pin on the line interface.

32
33

RCHBLK
TCHBLK

O Receive/Transmit Channel Block . A user-programmable output

that can be forced high or low during any of the 24 T1 channels.

Useful for blocking clocks to a serial UART or LAPD controller in

application where not all T1 channels are used such as Fractional

T1, 384K bps service, 768K bps, or ISDN-PRI. Also useful for

locating individual channels in drop-and-insert applications. See

Section 13 for timing details.

34 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function

output. If CCR1.6=0, then this pin will toggle high when the

synchronizer is searching for the T1 frame and multiframe. If

CCR1.6=1, then this pin will toggle high when the TCLK pin has

not been toggled for 5 ms.

35 INT2 O Receive Alarm Interrupt 2. Flags host controller during conditions

defined in Status Register 2. Active low, open drain output.

36 INT1 O Receive Alarm Interrupt 1. Flags host controller during alarm

conditions defined in Status Register 1. Active low, open drain

output.

37 TLCLK O Transmit Link Clock. 4 kHz or 2 kHz (ZBTSI) demand clock for

the TLINK input. See Section 13 for timing details.

DS2141A

5 of 39

PIN SYMBOL TYPE DESCRIPTION

38 TLINK I Transmit Link Data. If enabled via TCR1.2, this pin will be

sampled during the F-bit time on the falling edge of TCLK for data

insertion into either the FDL stream (ESF) or the Fs-bit position

(D4) or the Z-bit position (ZBTSI). See Section 13 for timing

details.

39 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or

multiframe boundaries for the DS2141A. Via TCR2.2, the DS2141A

can be programmed to output either a frame or multiframe pulse at

this pin. If this pin is set to output pulses at frame boundaries, it can

also be set via TCR2.4 to output double-wide pulses at signaling

frames. See Section 13 for timing details.

40 VDD - Positive Supply. 5.0 volts.

DS2141A REGISTER MAP

ADDRESS R/W REGISTER NAME

20 R/W Status Register 1
21 R/W Status Register 2
22 R/W Receive Information

Register

23 R Bipolar Violation/ESF

Error Event Count
Register 1

24 R Bipolar Violation/ESF

Error Event Count

Register 2
25 R CRC6 Count Register 1
26 R CRC6 Count Register 2
27 R Frame Error Count

Register
28 R Receive FDL Register
29 R/W Receive FDL Match

Register 1

2A R/W Receive FDL Match

Register 2

2B R/W Receive Control Register

1

2C R/W Receive Control Register

2

2D R/W Receive Mark Register 1
2E R/W Receive Mark Register 2

2F R/W Receive Mark Register 3
30 Not Assigned
31 Not Assigned
32 R/W Transmit Channel

Blocking Register 1
33 R/W Transmit Channel

Blocking Register 2

ADDRESS R/W REGISTER NAME

34 R/W Transmit Channel

Blocking Register 3

35 R/W Transmit Control

Register 1

36 R/W Transmit Control

Register 2

37 R/W Common Control

Register 1

38 R/W Common Control

Register 2

39 R/W Transmit Transparency

Register 1

3A R/W Transmit Transparency

Register 2

3B R/W Transmit Transparency

Register 3
3C R/W Transmit Idle Register 1
3D R/W Transmit Idle Register 2
3E R/W Transmit Idle Register 3

3F R/W Transmit Idle Definition

Register

60 R Receive Signaling

Register 1

61 R Receive Signaling

Register 2

62 R Receive Signaling

Register 3

63 R Receive Signaling

Register 4

64 R Receive Signaling

Register 5

DS2141A

6 of 39

ADDRESS R/W REGISTER NAME

65 R Receive Signaling

Register 6

66 R Receive Signaling

Register 7

67 R Receive Signaling

Register 8

68 R Receive Signaling

Register 9

69 R Receive Signaling

Register 10

6A R Receive Signaling

Register 11

6B R Receive Signaling

Register 12

6C R/W Receive Channel

Blocking Register 1

6D R/W Receive Channel

Blocking Register 2

6E R/W Receive Channel

Blocking Register 3
6F R/W Interrupt Mask Register 2
70 R/W Transmit Signaling

Register 1
71 R/W Transmit Signaling

Register 2
72 R/W Transmit Signaling

Register 3

ADDRESS R/W REGISTER NAME

73 R/W Transmit Signaling

Register 4

74 R/W Transmit Signaling

Register 5

75 R/W Transmit Signaling

Register 6

76 R/W Transmit Signaling

Register 7

77 R/W Transmit Signaling

Register 8

78 R/W Transmit Signaling

Register 9

79 R/W Transmit Signaling

Register 10

7A R/W Transmit Signaling

Register 11

7B R/W Transmit Signaling

Register 12

7C R/W LI Control Register Byte

1

7D R/W LI Control Register Byte

2

7E R/W Transmit FDL Register

7F R/W Interrupt Mask Register 1
Note: All values indicated within the Address
column are hexadecimal.

2.0 PARALLEL PORT

The DS2141A is controlled via a multiplexed bidirectional address/data bus by an external
microcontroller or microprocessor. The DS2141A can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC
Electrical Characteristics for more details. The multiplexed bus on the DS2141A saves pins because the
address information and data information share t he same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2141A
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during

the later portion of the DS or WR pulses. In a read cycle, the DS2141A outputs a byte of data during th e
latter portion of the DS or

RD pulses. The read cycle is terminated and the bus returns to a high

impedance state as

RD transitions high in Intel timing or as DS transitions low in Motorola timing.

3.0 CONTROL REGISTERS

The operation of the DS2141A is configured via a set of six registers. Typically, the control re gisters are
only accessed when the system is first powered up. Once, the DS2141A has been initialized, the control
registers will only need to be accessed when there is a chan ge in the s ystem configuration. There are two
Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and
two Common Control Registers (CCR1 and CCR2). Each of the six registers is described below.

DS2141A

7 of 39

RCR1: RECEIVE CONTROL REGISTER 1 (2Bh)

(MSB) (LSB)

- ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC

SYMBOL POSITION NAME AND DESCRIPTION

- RCR1.7 Not Assigned. Should be set to 0 when written to.

ARC RCR1.6

Auto Resync Criteria.

0=Resync on OOF or RCL event.
1=Resync on OOF only.

OOF1 RCR1.5

Out Of Frame Select 1.

0=2/4 frame bits in error.
1=2/5 frame bits in error.

OOF2 RCR1.4

Out Of Frame Select 2.

0=follow RCR1.5.
1=2/6 frame bits in error.

SYNCC RCR1.3

Sync Criteria.

In D4 Framing Mode.
0=search for Ft pattern, then search for Fs pattern.
1=cross couple Ft and Fs pattern.
In ESF Framing Mode.
0=search for FPS pattern only.
1=search for FPS and verify with CRC6.

SYNCT RCR1.2

Sync Time.

0=qualify 10 bits.
1=qualify 24 bits.

SYNCE RCR1.1

Sync Enable.

0=auto resync enabled.
1=auto resync disabled.

RESYNC RCR1.0 Resync. When toggled from low to high, a resync is initiated.

Must be cleared and set again for a subsequent resync.

DS2141A

8 of 39

RCR2: RECEIVE CONTROL REGISTER 2 (2Ch)

(MSB) (LSB)

RCS RZBTSI RSDW RSM RSIO RD4YM FSBE BPVCRS

SYMBOL POSITION NAME AND DESCRIPTION

RCS RCR2.7

Receive Code Select.

0=idle code (7F Hex).
1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex).

RZBTSI RCR2.6

Receive Side ZBTSI Enable.

0=ZBTSI disabled.
1=ZBTSI enabled.

RSDW RCR2.5

RSYNC Double-Wide.

0=do not pulse double-wide in signaling frames.
1=do pulse double-wide in signaling frames.
(note: this bit must be set to 0 when RCR2.4 = 1 or when
RCR2.3 = 1).

RSM RCR2.4

RSYNC Mode Select.

0=frame mode (see the timing in Section 13).
1=multiframe mode (see the timing in Section 13).

RSIO RCR2.3

RSYNC I/O Select.

0=RSYNC is an output.
1=RSYNC is an input (only valid if elastic store enabled).
(note: this bit must be set to 0 when CCR1.2 = 0).

RD4YM RCR2.2

Receive Side D4 Yellow Alarm Select.

0=0 in bit 2 of all channels.
1=a 1 in the S-bit position of frame 12.

FSBE RCR2.1

Fs-Bit Error Report Enable.

0=do not report bit errors in the Fs-bit position in FECR.
1=report bit errors in the Fs-bit position in FECR.

BPVCRS RCR2.0

BPVCRS Function Select.

0=counts bipolar violations.
1=counts ESF error events (CRC6 OR 'ed with RLOS).

DS2141A

9 of 39

TCR1: TRANSMIT CONTROL REGISTER 1 (35h)

(MSB) (LSB)

ODF TFPT TCPT RBSE GB7S TLINK TBL TYEL

SYMBOL POSITION NAME AND DESCRIPTION

ODF TCR1.7

Output Data Format.

0=bipolar data at TPOS and TNEG.
1=NRZ data at TPOS; TNEG = 0.

TFPT TCR1.6

Transmit Framing Pass Through.

0=Ft or FPS bits sourced internally.
1=Ft or FPS bits sampled at TSER during F-bit time.

TCPT TCR1.5

Transmit CRC Pass Through.

0=source CRC6 bits internally.
1=CRC6 bits sampled at TSER during F-bit time.

RBSE TCR1.4

Robbed Bit Signaling Enable.

0=no signaling is inserted in any channel.
1=signaling is inserted in all channels (the TTR registers can be
used to block insertion on a channel by channel basis).

GB7S TCR1.3

Global Bit 7 Stuffing.

0=allow the TTR registers to determine which channels
containing all zeros are to be bit 7 stuffed.
1=force bit 7 stuffing in all zero byte channels regardless of how
the TTR registers are programmed.

TLINK TCR1.2

TLINK Select.

0=source FDL or Fs bits from TFDL register.
1=source FDL or Fs bits from the TLINK pin.

TBL TCR1.1

Transmit Blue Alarm.

0=transmit data normally.
1=transmit an unframed all 1's code at TPOS and TNEG.

TYEL TCR1.0

Transmit Yellow Alarm.

0=do not transmit yellow alarm.
1=transmit yellow alarm.

DS2141A

10 of 39

TCR2: TRANSMIT CONTROL REGISTER 2 (36h)

(MSB) (LSB)

TESTM TESTIO TZBTSI TSDW TSM TSIO TD4YM B7ZS

SYMBOL POSITION NAME AND DESCRIPTION

TESTM TCR2.7 Test Mode Select. Set this bit to a 1 to force all outputs

(including I/O pins) either high (TCR2.6 = 1) or low (TCR2.6 =

0).

TESTIO TCR2.6

Test I/O Pins.

0=force all output (and I/O) pins to a logic 0.
1=force all output (and I/O) pins to a logic 1.

TZBTSI TCR2.5

Transmit Side ZBTSI Enable.

0=ZBTSI disabled.
1=ZBTSI enabled.

TSDW TCR2.4

TSYNC Double-Wide.

0=do not pulse double-wide in signaling frames.
1=do pulse double-wide in signaling frames.
(note: this bit must be set to 0 when TCR 2.3 = 1 or when
TCR2.2 = 0).

TSM TCR2.3

TSYNC Mode Select.

0=frame mode (see the timing in Section 13).
1=multiframe mode (see the timing in Section 13).

TSIO TCR2.2

TSYNC I/O Select.

0=TSYNC is an input.
1=TSYNC is an output.

TD4YM TCR2.1

Transmit Side D4 Yellow Alarm Select.

0=0s in bit 2 of all channels.
1=a 1 in the S-bit position of frame 12.

B7ZS TCR2.0

Bit 7 Zero Suppression Enable.

0=no stuffing occurs.
1=Bit 7 forced to a 1 in channels with all 0s.

DS2141A

11 of 39

CCR1: COMMON CONTROL REGISTER 1 (37h)

(MSB) (LSB)

TESE P34F RSAO - SCLKM RESE PLB LLB

SYMBOL POSITION NAME AND DESCRIPTION

TESE CCR1.7

Transmit Elastic Store Enable.

0=elastic store is bypassed.
1=elastic store is enabled.

P34F CCR1.6

Function of Pin 34.

0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).

RSAO CCR1.5

Receive Signaling All 1's.

0=allow robbed signaling bits to appear at RSER.
1=force all robbed signaling bits at RSER to 1.

- CCR1.4 Not Assigned. Should be set to 0 when written to.

SCLKM CCR1.3

SYSCLK Mode Select.

0=if SYSCLK is 1.544 MHz.
1=if SYSCLK is 2.048 MHz.

RESE CCR1.2

Receive Elastic Store Enable.

0=elastic store is bypassed.
1=elastic store is enabled.

PLB CCR1.1

Payload Loopback.

0=loopback disabled.
1=loopback enabled.

LLB CCR1.0

Local Loopback.

0=loopback disabled.
1=loopback enabled.

PAYLOAD LOOPBACK

When CCR1.1 is set to a 1, the DS2141A will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed. In a P LB situation, the DS2141A will
loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit
section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are
reinserted by the DS2141A. When PLB is enabled, the following will occur:

1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK.

2. All of the receive side signals will continue to operate normally.

3. The TCHCLK and TCHBLK signals are forced low.

4. Data at the TSER pin is ignored.

5. The TLCLK signal will become synchronous with RCLK instead of TCLK.

DS2141A

12 of 39

LOCAL LOOPBACK

When CCR1.0 is set to a 1, the DS2141A will enter a Local LoopBack (LLB) mode. This loopback is
useful in testing and debugging applications. In LLB, the DS2141A will loop data from the transmit side
back to the receive side. This loopback is synonymous with replacing the RCLK input with the TC LK
signal, and the RPOS/RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following
will occur:

1. The TPOS and TNEG pins will transmit an unframed all 1's.

2. Data at RPOS and RNEG will be ignored.

3. All receive side signals will take on timing synchronous with TCLK instead of RCLK.

CCR1: COMMON CONTROL REGISTER 2 (38h)

(MSB) (LSB)

TFM TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RFDL

SYMBOL POSITION NAME AND DESCRIPTION

TFM CCR2.7

Transmit Frame Mode Select.

0=D4 framing mode.
1=ESF framing mode.

TB8ZS CCR2.6

Transmit B8ZS Enable.

0=B8ZS disabled.
1=B8ZS enabled.

TSLC96 CCR2.5

Transmit SLC-96/Fs Bit Insertion Enable.

0=SLC-96 disabled.
1=SLC-96 enabled.

TFDL CCR2.4

Transmit Zero Stuffer Enable.

0=zero stuffer disabled.
1=zero stuffer enabled.

RFM CCR2.3

Receive Frame Mode Select.

0=D4 framing mode.
1=ESF framing mode.

RB8ZS CCR2.2

Receive B8ZS Enable.

0=B8ZS disabled.
1=B8ZS enabled.

RSLC96 CCR2.1

Receive SLC-96 Enable.

0=SLC-96 disabled.
1=SLC-96 enabled.

RFDL CCR2.0

Receive Zero Destuffer Enable.

0=zero destuffer disabled.
1=zero destuffer enabled.