dallas semiconductor DS1994 service manual

www.iButton.com

SPECIAL FEATURES

 4096 bits of Read/Write Nonvolatile

Memory

 256-bit Scratchpad Ensures Integrity of Data

Transfer

 Memory Partitioned into 256-bit Pages for

Packetizing Data

 Data Integrity Assured with Strict

Read/Write Protocols

 Contains Real-Time Clock/Calendar in

Binary Format

 Interval Timer Can Automatically

Accumulate Time When Power is Applied

 Programmable Cycle Counter can

Accumulate the Number of System Power­On/Off Cycles

 Programmable Alarms Can Be Set to

Generate Interrupts for Interval Timer, Real­Time Clock, and/or Cycle Counter

 Write-Protect Feature Provides Tamperproof

Time Data

 Programmable Expiration Date That Limits

Access to SRAM and Timekeeping

 Clock Accuracy is Better Than ±2 Minutes/

Month at 25°C

 Operating Temperature Range from -40°C to

+70°C

 Over 10 Years of Data Retention

COMMON iButton® FEATURES

 Unique, Factory-Lasered, and Tested 64-bit

Registration Number (8-bit Family Code +
48-bit Serial Number + 8-bit CRC Tester)
Assures Absolute Traceability Because No
Two Parts Are Alike

 Multidrop Controller for MicroLAN
 Digital Identification and Information by

Momentary Contact

 Chip-Based Data Carrier Compactly Stores

Information

4kb Plus Time Memory iButton

 Data Can Be Accessed While Affixed to

Object

 Economically Communicates to Bus Master

with a Single Digital Signal at 16.3kbps

 Standard 16mm Diameter and 1-Wire

Protocol Ensure Compatibility with i
Family

 Button Shape is Self-Aligning with Cup-

Shaped Probes

 Durable Stainless Steel Case Engraved with

Registration Number Withstands Harsh
Environments

 Easily Affixed with Self-Stick Adhesive

Backing, Latched by its Flange, or Locked
with a Ring Pressed onto its Rim

 Presence Detector Acknowledges when

Reader First Applies Voltage

 Meets UL#913 (4th Edit.); Intrinsically Safe

Apparatus, Approved under Entity Concept
for Use in Class I, Division 1, Group A, B, C
and D Locations

F5 MICROCAN

5.89

0.36

IO

GND

0.51

© 1993

YYWW REGISTERED RR

61

000000FBD804

04

16.25

All dimensions shown in millimeters.

ORDERING INFORMATION

DS1994L-F5 F5 MicroCan

DS1994

17.35

®

Button

iButton and 1-Wire are registered trademarks of Dallas Semiconductor.

1 of 22 012207

DS1994

EXAMPLES OF ACCESSORIES

DS9096P Self-Stick Adhesive Pad
DS9101 Multi-Purpose Clip
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
DS9092 iButton Probe

iButton DESCRIPTION

The DS1994 Memory iButton is a rugged read/write data carrier that acts as a localized database, easily
accessible with minimal hardware. The nonvolatile memory and optional timekeeping capability offer a
simple solution to storing and retrieving vital information pertaining to the object to which the iButton is
attached. Data is transferred serially through the 1-Wire protocol that requires only a single data lead and
a ground return.

The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
transfers the data to memory. This process ensures data integrity when modifying the memory. A 48-bit
serial number is factory lasered into each DS1994 to provide a guaranteed unique identity that allows for
absolute traceability. The durable MicroCan package is highly resistant to environmental hazards such as
dirt, moisture, and shock. Its compact, coin-shaped profile is self-aligning with mating receptacles,
allowing the DS1994 to be easily used by human operators. Accessories permit the DS1994 to be
mounted on almost any surface including plastic key fobs, photo-ID badges, and PC boards.

The DS1994 also includes time-keeping functions, a real-time clock/calendar, interval timer, cycle
counter, and programmable interrupts, in addition to the nonvolatile memory. The internal clock can be
programmed to deny memory access based on absolute time/date, total elapsed time, or the number of
accesses. These features allow the DS1994 to be used to create a stopwatch, alarm clock, time and date
stamp, logbook, hour meter, calendar, system power cycle timer, interval timer, and event scheduler.

OPERATION

The DS1994 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 4096-bit
SRAM, and 4) timekeeping registers. The timekeeping section utilizes an on-chip oscillator that is
connected to a 32.768kHz crystal. The SRAM and time-keeping registers reside in one contiguous
address space referred to hereafter as memory. All data is read and written least significant bit first.

The memory functions are not available until the ROM function protocol has been established. This
protocol is described in the ROM functions flowchart (Figure 9). The master must first provide one of
four ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a
ROM function sequence has been successfully executed, the memory functions are accessible and the
master can then provide any one of the four memory function commands (Figure 6).

2 of 22

DS1994

Figure 1. DS1994 BLOCK DIAGRAM

1-WIRE

PORT

ROM

1-W

FUNCTION

CONTROL

64-BIT

LASERED

ROM

PARASITE­POWERED
CIRCUITRY

3V LITHIUM

32.768 kHz

OSCILLATOR

MEMORY

FUNCTION

CONTROL

SRAM

16 PAGES of

TIMEKEEPING

FUNCTIONS

HOLDING REGISTERS

INTERNAL REGISTERS

& COUNTERS

-

256-BIT

SCRATCHPAD

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever
the data input is high. The data line provides sufficient power as long as the specified timing and voltage
requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,
lithium is conserved, and 2) if the lithium is exhausted for any reason, the ROM can still be read
normally.

64-BIT LASERED ROM

Each DS1994 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 2.)
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates,
as shown in Figure 3. The polynomial is X

8

+ X5 + X4 + 1. Additional information about the Dallas 1-Wire

Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register bits
are initialized to zero. Then starting with the least significant bit of the family code, 1 bit at a time is
shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After
the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in
the 8 bits of CRC should return the shift register to all zeros.

Figure 2. 64-BIT LASERED ROM

MSB LSB

8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (04h)

MSB LSB MSB LSB MSB LSB

3 of 22

DS1994

Figure 3. 1-WIRE CRC CODE

Polynomial = X8 + X5 + X4 + 1

STAGE

0

X

st

1

STAGE

1

X

nd

2

STAGE

2

X

rd

3

STAGE

3

X

th

4

STAGE

4

X

th

5

5

X

th

6

STAGE

INPUT DATA

6

X

th

7

STAGE

STAGE

7

X

th

8

8

X

MEMORY

The memory map in Figure 4 shows a 32-Byte page called the scratchpad, and additional 32-Byte pages
called memory. The DS1994 contains 16 pages that make up the 4096-bit SRAM. The DS1994 also
contains page 16, which has only 30 Bytes containing the timekeeping registers.

The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
transfers the data to memory. This process ensures data integrity when modifying the memory.

TIMEKEEPING

A 32.768kHz crystal oscillator is used as the time base for the timekeeping functions. The oscillator can
be turned on or off by an enable bit in the control register. The oscillator must be on for the real-time
clock, interval timer, and cycle counter to function.

The timekeeping functions are double buffered. This feature allows the master to read time or count
without the data changing while it is being read. To accomplish this, a snapshot of the counter data is
transferred to holding registers that the user accesses. This occurs after the 8th bit of the read memory
function command.

Real-Time Clock

The real-time clock is a 5-Byte binary counter. It is incremented 256 times per second. The least
significant Byte is a count of fractional seconds. The upper 4 Bytes are a count of seconds. The real-time
clock can accumulate 136 years of seconds before rolling over. Time/date is represented by the number of
seconds since a reference point, which is determined by the user. For example, 12:00 A.M., January 1,
1970 could be a reference point.

4 of 22

DS1994

A

A

A

A

Figure 4. DS1994 MEMORY MAP

SCRATCHPAD

PAGE

NOTE: Each page is 32 bytes (256 bits). The hex values
represent the starting address for each page or register.

MEMORY

PAGE 0
PAGE 1

PAGE 2
PAGE 3
PAGE 4

PAGE 5
PAGE 6

PAGE 7
PAGE 8

PAGE 9
PAGE 10
PAGE 11

PAGE 12
PAGE 13

0000h
0020h

0040h
0060h

0080h

00A0h
00C0h

00E0h
0100h

0120h
0140h
0160h

0180h
01A0h

PAGE 16

TIMEKEEPING REGISTERS

STATUS REGISTER

CONTROL REGISTER

REAL-TIME

COUNTER REGISTERS

INTERVAL TIME

COUNTER REGISTERS

CYCLE

COUNTER REGISTERS

REAL-TIME

LARM REGISTERS

0200h

0201h

0202h

0207h

020Ch

0210h

PAGE 14

PAGE 15

PAGE 16

STATUS REGISTER

76543210

X X CCE ITE RTE CCF ITF RTF

CONTROL REGISTER

76543210

DSEL

STOP
START

UTO

MAN

01C0h
01E0h

0200h

OSC RO WPC WPI WPR

INTERVAL TIME

LARM REGISTERS

CYCLE

LARM REGISTERS

0215h

021Ah

0200h

0201h

5 of 22

DS1994

Interval Timer

The interval timer is a 5-Byte binary counter. When enabled, it is incremented 256 times per second. The
least significant Byte is a count of fractional seconds. The interval timer can accumulate 136 years of
seconds before rolling over. The interval timer has two modes of operation that are selected by the
AUTO/MAN bit in the control register. In the auto mode, the interval timer begins counting after the data
line has been high for a period of time determined by the DSEL bit in the control register. Similarly, the
interval timer stops counting after the data line has been low for a period of time determined by the DSEL
bit. In the manual mode, time accumulation is controlled by the STOP/START bit in the control register.

NOTE: For auto mode operation, the high level on the data line must be greater than or equal to 2.1V.

Cycle Counter

The cycle counter is a 4-Byte binary counter. It increments after the falling edge of the data line if the
appropriate data line timing has been met. This timing is selected by the DSEL bit in the control register.
(See the Status/Control section).

NOTE: For cycle counter operation, the high level on the data line must be greater than or equal to 2.1V.

Alarm Registers

The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same
manner. When the value of a given counter equals the value in its associated alarm register, the
appropriate flag bit is set in the status register. If the corresponding interrupt enable bit in the status
register is set, an interrupt is generated. If a counter and its associated alarm register are write protected
when an alarm occurs, access to the device becomes limited. (See the Status/Control, Interrupts, and
Programmable Expiration sections.)

STATUS/CONTROL REGISTERS

The status and control registers are the first two Bytes of page 16 (see Figure 4).

Status Register

7 6 5 4 3 2 1 0

X X CCE ITE RTE CCF ITF RTF 0200h

DON’T CARE BITS READ ONLY

0 RTF Real-time clock alarm flag
1 ITF Interval timer alarm flag

2 CCF Cycle counter alarm flag

When a given alarm occurs, the corresponding alarm flag is set to a logic 1. The alarm flag is cleared by
reading the status register.

6 of 22

DS1994

3 RTE Real-time clock alarm flag
4 ITE Interval timer alarm flag

5 CCE Cycle counter alarm flag

Writing any of the interrupt enable bits to a logic 0 allows an interrupt condition to be generated when its
corresponding alarm flag is set (see the Interrupts section).

Control Register

7 6 5 4 3 2 1 0

DSEL

STOP

START

0 WPR Write protect real-time clock/alarms registers
1 WPI Write protect interval timer/alarms registers

2 WPC Write protect cycle counter/alarms registers

Setting a write protect bit to a logic 1 permanently write protects the corresponding counter and alarm
registers, all write protect bits, and additional bits in the control register. The write protect bits cannot be
written in a normal manner (see the Write Protect/Programmable Expiration section).

AUTO

MAN.

OSC RO WPC WPI WPR 0201h

3 RO Read only

If a programmable expiration occurs and the read only bit is set to a logic 1, then the DS1994 becomes
read only. If a programmable expiration occurs and the read only bit is a logic 0, then only the 64-bit
lasered ROM can be accessed (see the Write Protect/Programmable Expiration section).

4 OSC Oscillator enable

This bit controls the crystal oscillator. When set to a logic 1, the oscillator starts operation. When the
oscillator bit is a logic 0, the oscillator stops.

5 AUTO/MAN Automatic/Manual Mode

When this bit is set to a logic 1, the interval timer is in automatic mode. In this mode, the interva l timer is
enabled by the data line. When this bit is set to a logic 0, the interval timer is in manual mode. In this
mode, the interval timer is enabled by the STOP/START bit.

6 STOP/START Stop/Start (in manual mode)

If the interval timer is in manual mode, the interval timer starts counting when this bit is set to a logic 0
and stops counting when set to a logic 1. If the interval timer is in automatic mode, this bit has no effect.

7 of 22