Dallas Semiconductor DS1982-F5, DS1982-F3 Datasheet
www.iButton.com
SPECIAL FEATURES
1024 bits Electrically Programmable Read-
Only Memory (EPROM) communicates with
the economy of one signal plus ground
EPROM partitioned into four 256-bit pages
for randomly accessing packetized data
Each memory page can be permanently
write-protected to prevent tampering
Device is an “add only” memory where
additional data can be programmed into
EPROM without disturbing existing data
Architecture allows software to patch data by
superseding an old page in favor of a newly
programmed page
Reduces control, address, data, power, and
programming signals to a single data pin
8-bit family code specifies DS1982
communications requirements to reader
Reads over a wide voltage range of 2.8V to
6.0V from -40°C to +85°C; programs at
11.5V to 12.0V from -40°C to +50°C
COMMON iButton FEATURES
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alike
DS1982
1-kbit Add-Only iButton
TM
Multidrop controller for MicroLAN
Digital identification and information by
momentary contact
Chip-based data carrier compactly stores
information
Data can be accessed while affixed to object
Economically communicates to bus master
with a single digital signal at 16.3 kbits per
second
Standard 16 mm diameter and 1-Wire
protocol ensure compatibility with iButton
family
Button shape is self-aligning with cup-
shaped probes
Durable stainless steel case engraved with
registration number withstands harsh
environments
Easily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rim
Presence detector acknowledges when reader
first applies voltage
Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
®
F3 MICROCAN F5 MICROCAN
0.36
DATA
5.89
GROUND
0.51
YYWW REGISTERED RR
17
000000FBD8B3
c
1993
09
16.25
17.35
3.10
0.36
DATA
GROUND
0.51
YYWW REGISTERED RR
97
000000FBC52B
c
1993
16.25
09
17.35
All dimensions shown in millimeters.
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DS1982
ORDERING INFORMATION
DS1982-F3 F3 MicroCan
DS1982-F5 F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P Self-Stick Adhesive Pad
DS9101 Multi-Purpose Clip
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
DS9092 iButton Probe
iButton DESCRIPTION
The DS1982 1-kbit Add-Only iButton is a rugged read/write data carrier that identifies and stores relevant
information about the product or person to which it is attached. This information can be ac cessed with
minimal hardware, for example, a single port pin of a microcontroller. The DS1982 consists of a factor ylasered registration number that includes an unique 48-bit serial number, an 8–bit CRC, and an 8-bit
Family Code (09h) plus 1 kbit of EPROM which is user-programmable. The power to program and read
the DS1982 is derived entirely from the 1-Wire communication line. Data is transferred seriall y via the 1 Wire protocol which requires only a single data lead and a ground return. The entire device can be
programmed and then write-protected if desired. Alternatively, the part may be programmed multiple
times with new data being appended to, but not overwriting, existing data with each subsequent
programming of the device. Note: Individual bits can be changed only from a logical 1 to a logical 0,
never from a logical 0 to a logical 1. A provision is also included for indicating that a certain page or
pages of data are no longer valid and have been replaced with new or upd ated data that is now residing at
an alternate page address. This page address redirection all ows software to patch data and enhance the
flexibility of the device as a standalone database. The 48-bit serial number that is factory-lasered into
each DS1982 provides a guaranteed unique identity which allows for absolute traceability. The durable
MicroCan package is highly resistant to harsh environments such as dirt, moisture, and shock. Its compact
button-shaped profile is self-aligning with cup-shaped receptacles, allowing the DS1982 to be used easily
by human operators or automatic equipment. Accessories permit the DS1982 to be mounted on printed
circuit boards, plastic key fobs, photo-ID badges, ID bracelets, and many other objects. Applications
include work-in-progress tracking, electronic travelers, access control, storage of calibration constants,
and debit tokens.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1982. The DS1982 has three main data components: 1) 64-bit lasered ROM, 2) 1024-bit EPROM,
and 3) EPROM Status Bytes. The device derives its power for r ead operations entirely from the 1-Wire
communication line by storing energy on an internal capacitor during periods of time when the signal line
is high and continues to operate off of this “parasite” power source during the low times of the 1-Wire
line until it returns high to replenish the parasite (capacitor) supply. During programming, 1-Wire
communication occurs at normal voltage levels and then is pulsed momentarily to the programming
voltage to cause the selected EPROM bits to be programmed. The 1-Wire line must be able to provide 12
volts and 10 milliamperes to adequately program the EPROM portions of the part. Whenever
programming voltages are present on the 1-Wire line a special high voltage detect circuit within the
DS1982 generates an internal logic signal to indicate this condition. The hierarchical structure of the 1 Wire protocol is shown in Figure 2. The bus master must first provide one of the four ROM function
commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on
the 64-bit lasered ROM portion of each device and can singulate a spe cific device if man y are p resent on
the 1-Wire line as well as indicate to the bus master how man y and what t ypes of devices ar e pres ent . The
protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory functions that operate on the EPROM portions of the
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DS1982
DS1982 become accessible and the bus master may issue any one of the five memory function commands
specific to the DS1982 to read or program the various data fields. The protocol for these memory function
commands is described in Figure 6. All data is read and written least significant bit first.
64-BIT LASERED ROM
Each DS1982 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3).
The 64-bit ROM and ROM Function Control section allow the DS1982 to operate as a 1-W ire device and
follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The memor y functions required
to read and program the EPROM sections of the DS1982 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow ch art (Fi gure 9 ). The 1Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM,
3) Search ROM, or 4) Skip ROM. After a ROM function sequence h as been successfully executed, the
bus master may then provide any one of the memory function commands specific to the DS1982 (Figure
6).
The 1-Wire CRC of the lasered ROM is generated using the polynomial X
8
+ X5 + X4 + 1. Additional
information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book
of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to 0. Then
starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the
family code has been entered, then the serial number is entered. After the 48th bit of the serial number has
been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the
shift register to all 0s.
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DS1982 BLOCK DIAGRAM Figure 1
DS1982
4 of 23
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
(
)
DS1982
BUS
MASTER
OTHER
DEVICES
DS 1982
COMMAN D AVAILABLE DATA FIELD
LEVEL: COMMANDS:
1-WIRE ROM FUNCTION
COMMANDS (SEE FIGURE 9)
DS1982-SPECIFIC
MEMORY FUNCTION
COMMANDS
SEE FIGURE 6
READ ROM 64-BIT ROM
MATCH ROM 64-BIT ROM
SEARCH ROM 64-BIT ROM
SKIP ROM N/A
WRITE MEMORY 1024-BIT EPROM
WRITE STATUS BYTE EPROM STATUS BYTES
READ MEMORY 1024-BIT EPROM
READ STATUS B YTE EPROM STATUS BYTES
READ DATA/GENERATE 1024-BIT EPROM
8-BIT CRC
AFFECTED:
64-BIT LASERED ROM Figure 3
8-Bit CRC Code 48- Bit Serial Number 8- Bit Family Code (09h)
MSB LSB MSB LSB MSB LSB
1-WIRE CRC GENERATOR Figure 4
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DS1982
1024-BIT EPROM
The memory map in Figure 5 shows the 1024-bit EPROM section of the DS1982 which is configured as
four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit
CRC from the DS1982 that confirms proper receipt of the data. If the buffer contents are correct, a
programming voltage should be applied and the byte of data will be written into the selected address in
memory. This process ensures data integrity when programming the memory. The details for reading and
programming the 1024-bit EPROM portion of the DS1982 are given in the "Memory Function
Commands" section.
EPROM STATUS BYTES
In addition to the 1024 bits of data memory the DS1982 provides 64 bits of status memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS1982. The first byte of the EPROM status memory contains the Write-Protect Page
bits which inhibit programming of the corresponding page in the 1024-bit main memory area if the
appropriate write protection bit is programmed. Once a bit has been programmed in the Write-Protect
Page byte, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be
read.
The next 4 bytes of the EPROM Status Memory contain the Page Address Redirection Bytes which
indicate if one or more of the pages of data in the 1024-bit EPROM section have been invalidated and
redirected to the page address contained in the appropriate redirection byte. The hardware of the DS1982
makes no decisions based on the contents of the Page Address Redirection Bytes. These additional bytes
of status EPROM allow for the redirection of an entire page to another page address, indicating that the
data in the original page is no longer considered relevant or valid. With EPROM technology, bits within a
page can be changed from a logical 1 to a logical 0 by programming, but cannot be changed back.
Therefore, it is not possible to simply rewrite a page if the data requires changing or updating, but with
space permitting, an entire page of data can be redirected to another pa ge within the DS1982 by writing
the one’s complement of the new page address into the Page Address Redirection Byte that corresponds
to the original (replaced) page.
This architecture allows the user’s soft ware to make a “data patch” to the EP ROM by indicating that a
particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.
If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to that
page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page
corresponding to that redirection byte is invalid, and the valid data can now be found at the one’s
complement of the page address indicated by the hex value stored in the associated Page Address
Redirection Byte. A value of FDH in the redirection byte for page 1, for ex ample, would indicate that the
updated data is now in page 2. The details for reading and programming the EPROM status memory
portion of the DS1982 is given in the Memory Function Commands section.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the
various data fields within the DS1982. The Memory Function Control section, 8-bit scratchpad, and the
Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create
the correct control signals within the device. A 3-byte protocol is issued by the bus master. It is comprised
of a command byte to determine the type of operation and 2 address bytes to determine the specific
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DS1982
starting byte location within a data field. The command byte indicates if the device is to be read or
written. Writing data involves not only issuing the correct command sequence but also providing a 12volt programming voltage at the appropriate times. To execute a write sequence, a byte of data is first
loaded into the scratchpad and then pro grammed into the s elected address. W rite sequences always occu r
a byte at a time. To execute a read sequence, the starting address is issued by the bus master and data is
read from the part beginning at that initial location and continuing to the end of the selected data field or
until a reset sequence is issued. All bits transferred to the DS1982 and received back by the bus master
are sent least significant bit first.
DS1982 MEMORY MAP Figure 5
8-BIT SCRATCHPAD
STARTING
ADDRESS
1024-BIT
EPROM
0000h
0020h
0040h
0060h
PAGE 0
32 BYTES
PAGE 1
32 BYTES
PAGE 2
32 BYTES
PAGE 3
32 BYTES
EPROM STATUS BYTES
ADDRESS: 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h
(MSB) (LSB)
BIT 0 WRITE PROTEC T P AGE 0
BIT 1 WRITE PROTEC T P AGE 1
BIT 2 WRITE PROTEC T P AGE 2
BIT 3 WRITE PROTEC T P AGE 3
BIT 4-7 BITMAP OF USED PAGES (RESERVED FOR TMEX)
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