Dallas Semiconductor DS1834U, DS1834S, DS1834DU, DS1834DS, DS1834D Datasheet
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FEATURES
5V power-on reset
3.3V power-on reset
Internal power is drawn from higher of either
the 5VIN input or the 3.3VIN input
Excellent for systems designed to operate
with dual power supplies
Asserts resets during power transients
Pushbutton reset input for system override
Maintains reset for 350 ms after VCC returns
to an in-tolerance condition
Reduces need for discrete components
Precision temperature-compensated voltage
reference and voltage sensor
8-pin DIP, 8-pin SOIC, and 8-pin µ-SOP
available
CMOS output for low current operation on
the DS1834 and DS1834D
Operating temperature of -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTION
5VIN - 5V Power Supply Input
5VRST (*RST) - 5V Reset Output
5V TOL - Selects 5V Input Tolerance
GND - Ground
PBRST - Pushbutton Reset
3.3V TOL - Selects 3.3V Input Tolerance
3.3V
RST (*RST) - 3.3V Reset Output
3.3V
IN
- 3.3V Power Supply Input
*DS1834D Active High Reset
DESCRIPTION
The DS1834 Dual EconoResets monitors three vital system conditions: 5-volt supply, 3.3-volt supply,
and an external override. First a pr ecisi on temperat u re r efe rence and com parat o r circuit moni tor t he stat us
of the 5-volt supply and the 3.3-volt supply. When an out-of-tolerance condition is detected, an internal
power-fail signal is generated which forces the reset of the affected supply to an active state.
Lastly, the DS1834 supports an external reset via an internally debounced pushbutton input. When the
pushbutton is pulled low both resets will be asserted for approximately 350 ms aft er the pushbutton is
released.
DS1834/A/D
Dual EconoReset with Pushbutton
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DS1834 8-Pin SOIC (150-mil)
1
2
3
4
8
7
6
5
5V
IN
5V RST
5V TOL
GND
3.3V
IN
3.3V RST
3.3V TOL
PBRST
DS1834 8-Pin µ-SOP (118-mil)
5V
5V RST (*RST
)
5V TOL
GND
3.3V
IN
3.3V RST (*RST)
3.3V TOL
PBRST
1
2
3
4
8
7
6
5
DS1834 8-Pin DIP (300-mil)
5V
IN
5V RST
5V TOL
GND
3.3V
IN
3.3V RST
3.3V TOL
PBRST
1
2
3
4
8
7
6
5
DS1834/A/D
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OPERATION
Power Monitor
The DS1834 provides the functions of detecting out-of-tolerance conditions on a 3.3-volt and 5-volt
power supply and warning a processor-based system of impending power failure. When an input is
detected as out of tolerance on either voltage input the RST for that supply will be forced active. When
that input returns to a valid state the RST will remain active for about 350 ms and then return to an
inactive state until the next input out-of-tolerance condition.
On power-up both resets are kept active for approximately 350 ms after the power supply inputs have
reached the selected tolerance. This allows the power supply and s ystem power to stabilize befor e RST is
released.
All internal operating current for the DS1834 will be drawn from the input with the hi ghest voltage level.
The outputs will draw current only from the controlling input (5V IN or 3.3V IN).
DS1834 BLOCK DIAGRAM Figure 1
DS1834A BLOCK DIAGRAM OUTPUT Figure 2
DS1834/A/D
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Tolerance Select
The DS1834 provides two TOL inputs for individual customization of the DS1834 to specific applic ation
requirements. If the TOL for the 5-volt supply is tied to the 5-volt input a 10% tolerance is selected for
the 5 volt supply. If the TOL for the 3.3-volt supply is tied to the 3.3-volt input, a 20% tolerance is
selected for the 3.3-volt supply. If TOL inputs are tied to ground, the 5-volt input will be set at a 5%
tolerance and the 3.3-volt input would be set to a 10% tolerance.
Pushbutton Reset
The DS1834 provides a pushbutton switch for manual reset control. When at least one of the DS1834
resets are not in a reset cycle, a pushbutton reset can be generated by pulling the PBRST pin low for at
least 2 ms. When the pushbutton is held low, both resets are forced active and will remain active for about
350 ms after the pushbutton is released. The pushbutton input is pulled high through an internal
40 kΩ=pull-up resistor and debounced via internal circuitry. See Figure 3 for an application ex ample and
Figure 4 for the timing diagram.
PUSHBUTTON RESET Figure 3
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
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