Dallas Semiconductor DS1820S, DS1820 Datasheet

DS1820

1–Wire

Digital Thermometer

DS1820

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FEATURES

• Unique 1–Wire

interface requires only one port pin

for communication

• Multidrop capability simplifies distributed temperature

sensing applications

• Requires no external components

• Can be powered from data line

• Zero standby power required

• Measures temperatures from –55°C to +125°C in

0.5°C increments. Fahrenheit equivalent is –67°F to +257°F in 0.9°F increments

• Temperature is read as a 9–bit digital value.

• Converts temperature to digital word in 200 ms (typ.)

• User–definable, nonvolatile temperature alarm set-

tings

• Alarm search command identifies and addresses

devices whose temperature is outside of programmed limits (temperature alarm condition)

• Applications include thermostatic controls, industrial

systems, consumer products, thermometers, or any thermally sensitive system

PIN ASSIGNMENT

321

DALLAS DS2434

GND

VDD

DALLAS DS1820

321

DS1820S

16–PIN SSOP

DS1820

PR35 PACKAGE

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

NC NC NC NC NC NC NC GND

NC NC NC NC NC NC

VDD

BOTTOM VIEW

See Mech. Drawings

Section

See Mech. Drawings

Section

PIN DESCRIPTION

GND – Ground DQ – Data In/Out V

– Optional V

NC – No Connect

DESCRIPTION

The DS1820 Digital Thermometer provides 9–bit temperature readings which indicate the temperature of the device.

Information is sent to/from the DS1820 over a 1–Wire interface, so that only one wire (and ground) needs to be connected from a central microprocessor to a DS1820. Power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for an external power source.

Because each DS1820 contains a unique silicon serial number, multiple DS1820s can exist on the same 1–Wire bus. This allows for placing temperature sensors in many different places. Applications where this feature is useful include HVAC environmental controls, sensing temperatures inside buildings, equipment or machinery, and in process monitoring and control.

DS1820

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DETAILED PIN DESCRIPTION

16–PIN SSOP

PR35

SYMBOL DESCRIPTION

9 1 GND Ground. 8 2 DQ Data Input/Output pin. For 1–Wire operation: Open drain. (See

“Parasite Power” section.)

7 3 V

Optional VDD pin. See “Parasite Power” section for details of connection.

DS1820S (16–pin SSOP): All pins not specified in this table are not to be connected.

OVERVIEW

The block diagram of Figure 1 shows the major components of the DS1820. The DS1820 has three main data components: 1) 64–bit lasered ROM, 2) temperature sensor, and 3) nonvolatile temperature alarm triggers TH and TL. The device derives its power from the 1–Wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off this power source during the low times of the 1–Wire line until it returns high to replenish the parasite (capacitor) supply. As an alternative, the DS1820 may also be powered from an external 5 volts supply.

Communication to the DS1820 is via a 1–Wire port. With the 1–Wire port, the memory and control functions will not be available before the ROM function protocol has been established. The master must first provide one of five ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. These commands operate on the 64–bit lasered ROM portion of each device and can single out

a specific device if many are present on the 1–Wire line as well as indicate to the Bus Master how many and what types of devices are present. After a ROM function sequence has been successfully executed, the memory and control functions are accessible and the master may then provide any one of the six memory and control function commands.

One control function command instructs the DS1820 to perform a temperature measurement. The result of this measurement will be placed in the DS1820’s scratchpad memory, and may be read by issuing a memory function command which reads the contents of the scratchpad memory. The temperature alarm triggers TH and TL consist of one byte EEPROM each. If the alarm search command is not applied to the DS1820, these registers may be used as general purpose user memory. Writing TH and TL is done using a memory function command. Read access to these registers is through the scratchpad. All data is read and written least significant bit first.

DS1820 BLOCK DIAGRAM Figure 1

64–BIT ROM

SCRATCHPAD

MEMORY AND

CONTROL LOGIC

AND

1–WIRE PORT

TEMPERATURE SENSOR

8–BIT CRC

GENERATOR

POWER SUPPLY

SENSE

INTERNAL V

HIGH TEMPERATURE

TRIGGER, TH

LOW TEMPERATURE

TRIGGER, TL

+5V

DS1820

I/O

4.7K

µP

GND

DS1820

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PARASITE POWER

The block diagram (Figure 1) shows the parasite powered circuitry. This circuitry “steals” power whenever the I/O or VDD pins are high. I/O will provide sufficient power as long as the specified timing and voltage requirements are met (see the section titled “1–Wire Bus System”). The advantages of parasite power are two–fold:

1) by parasiting off this pin, no local power source is needed for remote sensing of temperature, and 2) the ROM may be read in absence of normal power.

In order for the DS1820 to be able to perform accurate temperature conversions, sufficient power must be provided over the I/O line when a temperature conversion is taking place. Since the operating current of the DS1820 is up to 1 mA, the I/O line will not have sufficient drive due to the 5K pull–up resistor. This problem is particularly acute if several DS1820’s are on the same I/O and attempting to convert simultaneously .

There are two ways to assure that the DS1820 has sufficient supply current during its active conversion cycle. The first is to provide a strong pull–up on the I/O line whenever temperature conversions or copies to the E

memory are taking place. This may be accomplished by using a MOSFET to pull the I/O line directly to the power supply as shown in Figure 2. The I/O line must be switched over to the strong pull–up within 10 µs maximum after issuing any protocol that involves copying to the E

memory or initiates temperature conversions. When using the parasite power mode, the VDD pin must be tied to ground.

Another method of supplying current to the DS1820 is through the use of an external power supply tied to the

pin, as shown in Figure 3. The advantage to this is that the strong pull–up is not required on the I/O line, and the bus master need not be tied up holding that line high during temperature conversions. This allows other data traffic on the 1–Wire bus during the conversion time. In addition, any number of DS1820’s may be placed on the 1–Wire bus, and if they all use external power, they may all simultaneously perform temperature conversions by issuing the Skip ROM command and then issuing the Convert T command. Note that as long as the external power supply is active, the GND pin may not be floating.

The use of parasite power is not recommended above 100°C, since it may not be able to sustain communications given the higher leakage currents the DS1820 exhibits at these temperatures. For applications in which such temperatures are likely, it is strongly recommended that VDD be applied to the DS1820.

For situations where the bus master does not know whether the DS1820’s on the bus are parasite powered or supplied with external V

, a provision is made in the DS1820 to signal the power supply scheme used. The bus master can determine if any DS1820’s are on the bus which require the strong pull–up by sending a Skip ROM protocol, then issuing the read power supply command. After this command is issued, the master then issues read time slots. The DS1820 will send back “0” on the 1–Wire bus if it is parasite powered; it will send back a “1” if it is powered from the V

pin. If the master receives a “0”, it knows that it must supply the strong pull–up on the I/O line during temperature conversions. See “Memory Command Functions” section for more detail on this command protocol.

STRONG PULL–UP FOR SUPPLYING DS1820 DURING TEMPERATURE CONVERSION Figure 2

DS1820

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USING VDD TO SUPPLY TEMPERATURE CONVERSION CURRENT Figure 3

+5V

DS1820

I/O

4.7K

µP

TO OTHER 1–WIRE DEVICES

EXTERNAL +5V SUPPLY

OPERATION – MEASURING TEMPERATURE

The DS1820 measures temperature through the use of an on–board proprietary temperature measurement technique. A block diagram of the temperature measurement circuitry is shown in Figure 4.

The DS1820 measures temperature by counting the number of clock cycles that an oscillator with a low temperature coefficient goes through during a gate period determined by a high temperature coefficient oscillator . The counter is preset with a base count that corresponds to –55°C. If the counter reaches zero before the gate period is over, the temperature register, which is also preset to the –55°C value, is incremented, indicating that the temperature is higher than –55°C.

At the same time, the counter is then preset with a value determined by the slope accumulator circuitry. This circuitry is needed to compensate for the parabolic behavior of the oscillators over temperature. The counter is then clocked again until it reaches zero. If the gate period is still not finished, then this process repeats.

The slope accumulator is used to compensate for the non–linear behavior of the oscillators over temperature, yielding a high resolution temperature measurement. This is done by changing the number of counts necessary for the counter to go through for each incremental degree in temperature. T o obtain the desired resolution, therefore, both the value of the counter and the number of counts per degree C (the value of the slope accumulator) at a given temperature must be known.

Internally, this calculation is done inside the DS1820 to provide 0.5°C resolution. The temperature reading is

provided in a 16–bit, sign–extended two’s complement reading. T able 1 describes the exact relationship of output data to measured temperature. The data is transmitted serially over the 1–Wire interface. The DS1820 can measure temperature over the range of –55°C to +125°C in 0.5°C increments. For Fahrenheit usage, a lookup table or conversion factor must be used.

Note that temperature is represented in the DS1820 in terms of a

/2°C LSB, yielding the following 9–bit format:

MSB LSB

1 1 1 0 0 1 1 1 0

= –25°C

The most significant (sign) bit is duplicated into all of the bits in the upper MSB of the two–byte temperature register in memory. This “sign–extension” yields the 16–bit temperature readings as shown in Table 1.

Higher resolutions may be obtained by the following procedure. First, read the temperature, and truncate the 0.5°C bit (the LSB) from the read value. This value is TEMP_READ. The value left in the counter may then be read. This value is the count remaining (COUNT_REMAIN) after the gate period has ceased. The last value needed is the number of counts per degree C (COUNT_PER_C) at that temperature. The actual temperature may be then be calculated by the user using the following:

TEMPERATURE = TEMP_READ – 0.25



(COUNT_PER_C – COUNT_REMAIN)

COUNT_PER_C

DS1820

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TEMPERATURE MEASURING CIRCUITRY Figure 4

SLOPE ACCUMULATOR

PRESET

COUNTER

STOP

INC

COMPARE

TEMPERATURE REGISTER

LOW TEMPERATURE

COEFFICIENT OSCILLATOR

HIGH TEMPERATURE

COEFFICIENT OSCILLATOR

SET/CLEAR LSB

TEMPERATURE/DATA RELATIONSHIPS Table 1

TEMPERATURE

DIGITAL OUTPUT

(Binary)

DIGITAL OUTPUT

(Hex)

+125°C 00000000 111 11010 00FA

+25°C 00000000 00110010 0032h +

°C 00000000 00000001 0001h

+0°C 00000000 00000000 0000h –1/2°C 11111111 11111111 FFFFh –25°C 11111111 11001110 FFCEh –55°C 11111111 10010010 FF92h

OPERATION – ALARM SIGNALING

After the DS1820 has performed a temperature conversion, the temperature value is compared to the trigger values stored in TH and TL. Since these registers are 8–bit only, the 0.5°C bit is ignored for comparison. The most significant bit of TH or TL directly corresponds to the sign bit of the 16–bit temperature register. If the result of a temperature measurement is higher than TH or lower than TL, an alarm flag inside the device is set.

This flag is updated with every temperature measurement. As long as the alarm flag is set, the DS1820 will respond to the alarm search command. This allows many DS1820s to be connected in parallel doing simultaneous temperature measurements. If somewhere the temperature exceeds the limits, the alarming device(s) can be identified and read immediately without having to read non–alarming devices.

DS1820

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64–BIT LASERED ROM

Each DS1820 contains a unique ROM code that is 64–bits long. The first eight bits are a 1–Wire family code (DS1820 code is 10h). The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 5.) The 64–bit ROM and ROM Function Control section allow the DS1820 to operate as a 1–Wire device and follow the 1–Wire protocol detailed in the section “1–Wire Bus System”. The functions required to control sections of the DS1820 are not accessible until the ROM function protocol has been satisfied. This protocol is described in the ROM function protocol flowchart (Figure 6). The 1–Wire bus master must first provide one of five ROM function commands:

1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. After a ROM functions sequence has been successfully executed, the functions specific to the DS1820 are accessible and the bus master may then provide and one of the six memory and control function commands.

CRC GENERATION

The DS1820 has an 8–bit CRC stored in the most significant byte of the 64–bit ROM. The bus master can compute a CRC value from the first 56–bits of the 64–bit ROM and compare it to the value stored within the DS1820 to determine if the ROM data has been received error–free by the bus master. The equivalent polynomial function of this CRC is:

CRC = X

+ X5 + X4 + 1

The DS1820 also generates an 8–bit CRC value using the same polynomial function shown above and pro-

vides this value to the bus master to validate the transfer of data bytes. In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function given above and compare the calculated value to either the 8–bit CRC value stored in the 64–bit ROM portion of the DS1820 (for ROM reads) or the 8–bit CRC value computed within the DS1820 (which is read as a ninth byte when the scratchpad is read). The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry inside the DS1820 that prevents a command sequence from proceeding if the CRC stored in or calculated by the DS1820 does not match the value generated by the bus master.

The 1–Wire CRC can be generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 7. Additional information about the Dallas 1–Wire Cyclic Redundancy Check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products”.

The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros.

64–BIT LASERED ROM Figure 5

8–BIT CRC CODE 48–BIT SERIAL NUMBER 8–BIT FAMILY CODE (10h)

MSB LSB MSB LSB MSB LSB

DS1820 T

PRESENCE

PULSE

33h READ ROM COMMAND

55h

MATCH ROM

COMMAND

F0h

SEARCH ROM

COMMAND

CCh

SKIP ROM

COMMAND

DS1820 T

FAMILY

CODE

1 BYTE

BIT 0

MATCH?

BIT 0

MATCH?

BIT 1

MATCH?

BIT 1

MATCH?

BIT 63

MATCH?

BIT 63

MATCH?

DS1820 T

SERIAL NUMBER

6 BYTES

DS1820 T

CRC BYTE

DS1820 TX BIT 0 DS1820 TX BIT 0

DS1820 TX BIT 1 DS1820 T

BIT 1

DS1820 TX BIT 63 DS1820 TX BIT 63

MASTER TX BIT 1

MASTER TX BIT 0

MASTER TX BIT 1

MASTER TX BIT 63

MASTER T

RESET PULSE

MASTER T

ROM

FUNCTION COMMAND

MASTER TX MEMORY OR CONTROL

FUNCTION COMMAND

ECh

ALARM SEARCH

COMMAND

ALARM

CONDITION

DS1820

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ROM FUNCTIONS FLOW CHART Figure 6

DS1820

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1–WIRE CRC CODE Figure 7

(MSB) (LSB)

XOR XOR XOR

INPUT

MEMORY

The DS1820’s memory is organized as shown in Figure 8. The memory consists of a scratchpad RAM and a nonvolatile, electrically erasable (E2) RAM, which stores the high and low temperature triggers TH and TL. The scratchpad helps insure data integrity when communicating over the 1–Wire bus. Data is first written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command will transfer the data to the nonvolatile (E

) RAM. This pro-

cess insures data integrity when modifying the memory.

The scratchpad is organized as eight bytes of memory. The first two bytes contain the measured temperature

information. The third and fourth bytes are volatile copies of TH and TL and are refreshed with every power–on reset. The next two bytes are not used; upon reading back, however, they will appear as all logic 1’ s. The seventh and eighth bytes are count registers, which may be used in obtaining higher temperature resolution (see “Operation–measuring T emperature” section).

There is a ninth byte which may be read with a Read Scratchpad command. This byte contains a cyclic redundancy check (CRC) byte which is the CRC over all of the eight previous bytes. This CRC is implemented in the fashion described in the section titled “CRC Generation”.

DS1820 MEMORY MAP Figure 8

TEMPERATURE LSB

TEMPERATURE MSB

TH/USER BYTE 1

TL/USER BYTE 2

RESERVED

COUNT REMAIN

CRC

BYTE

TH/USER BYTE 1

TL/USER BYTE 2

SCRATCHPAD

RAM

COUNT PER °C

DS1820

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1–WIRE BUS SYSTEM

The 1–Wire bus is a system which has a single bus master and one or more slaves. The DS1820 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1–Wire signaling (signal types and timing).

HARDWARE CONFIGURATION

The 1–Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it

at the appropriate time. To facilitate this, each device attached to the 1–Wire bus must have open drain or 3–state outputs. The 1–Wire port of the DS1820 (I/O pin) is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1–Wire bus with multiple slaves attached. The 1–Wire bus requires a pullup resistor of approximately 5KΩ.

HARDWARE CONFIGURATION Figure 9

+5V

4.7K

1OO OHM MOSFET

DS1820 1–WIRE PORTBUS MASTER

5 µA Typ.

RX = RECEIVE T

= TRANSMIT

The idle state for the 1–Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1–Wire bus is in the inactive (high) state during the recovery period. If this does not occur and the bus is left low for more than 480 µs, all components on the bus will be reset.

TRANSACTION SEQUENCE

The protocol for accessing the DS1820 via the 1–Wire port is as follows:

• Initialization

• ROM Function Command

• Memory Function Command

• Transaction/Data

INITIALIZATION

All transactions on the 1–Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s).

The presence pulse lets the bus master know that the DS1820 is on the bus and is ready to operate. For more details, see the “1–Wire Signaling” section.

ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the five ROM function commands. All ROM function commands are 8–bits long. A list of these commands follows (refer to flowchart in Figure 6):

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