dallas semiconductor DS1808 service manual

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DS1808

Dual Log Digital Potentiomete

FEATURES

§ Two 32-position log-tapers

§ 60dB attenuation range:

–1dB per step (12 taps)
–2dB per step (12 taps)
–3dB per step (8 taps)
–90dB low-end attenuation

§ 2-Wire Interface Control

§ Power Supply: Dual ±12V

§ Maximum Voltage Across Potentiometers:

±12V

§ Standard Resistance Value: 45kW

§ Packages: 16-Pin SOIC

§ Operating Temperature: -40oC to +85oC

ORDERING INFORMATION

DS1808Z-050 16-Pin SOIC -40ºC to
+85ºC 45kΩ

DS1808Z-050/T&R 16-Pin SOIC -40ºC to
+85ºC 45kΩ

PIN ASSIGNMENT

V

GND

A2

A1

V

A0

W0
L0

H0

1

2

3

B

4

5

6

7

8

16-Pin SOIC (150-mil)

16

15

14

13

12

11

10

DD

V

CC

SCL

SDA

CE

W

H1

9

L1

PIN DESCRIPTION

V

CC

V

B

V

DD

H0, H

1

L0, L

1

W0, W1 - Wiper Terminals
SDA - 2-Wire Serial Data Input/Output
SCL - 2-Wire Clock Input
/CE - 2-Wire Interface Enable
GND - Ground
A0, A1, A2 - Address Pins

- +12V Supply

- -12V Supply (substrate bias)

- 5V Digital Supply

- High-end Terminals

- Low-end Terminals

DESCRIPTION

The DS1808 is a dual-channel, digitally controlled, log-taper potentiometer. Each potentiometer is
comprised of 32 wiper terminal positions plus a mute position. The device has three accessible
potentiometer terminals that include the high-side terminal (H), the low-side terminal (L), and the wiper
terminal (W). The resolution of the DS1808 is shown in Figure 8 and represents 1dB per step for the first
12 taps, 2dB per step for the next 12 taps and 3dB per step for the bottom 8 taps, providing a total
attenuation range of 60dB. The mute position of the DS1808 provides greater than 90dB of attenuation.
The wiper position on the resistor ladder is selected via a 6-bit register, whose value is controlled by the
industry-standard 2-wire interface. The interface consists of two control signals: SDA and SCL. The
DS1808 is available in a standard 45kW resistor value. The DS1808 is specified to operate over the

o

industrial temperature range (-40

C to +85oC) and is available in the 16-pin SOIC package. The DS1808
was designed for low-cost, stereo volume control applications. The device is specified to operate from
±12V

±10% supplies and accept a maximum input signal range of ±12V.

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DS1808 BLOCK DIAGRAM Figure 1

DS1808

SDA

SCL

GND

W

H

W

0

0

60dB

L

0

>90dB

Control Logic

Power Supply VB (-12V Supply)

0dB0dB

60dB

>90dB

1

H

1

L

1

Address Lines
A0 – A2

CE

(+12V Supply)

V

CC

V

(5V Supply)

DD

PIN DESCRIPTIONS

VCC – Power Supply Terminal. This pin acts as the positive rail. The DS1808 will support positive supply
voltages ranging from 5 to 13.2 volts. When VCC–VB is less than 8 volts the series wiper resistance will
increase up to 1kW. The value of VDD should never exceed VCC.

VB – Substrate Bias Supply. This pin acts as a negative rail. The DS1808 will support negative voltages
ranging from 0 to -13.2 volts. When V

CC–VB

up to 1kW.

V

DC Supply Terminal. 5V DC voltage supply. The value of VDD should never exceed VCC.

DD –

GND – Ground Terminal.

SDA – 2-wire serial data interface. The serial data pin is for serial data transfer to and from the DS1808.

The pin is open drain and may be wire-ORed with other open drain or open collector interfaces.

SCL – 2-wire serial clock interface. The serial clock input is used to clock data into the DS1808 on rising
edges and clock data out on falling edges.

/CE – Port Enable Pin. When active (/CE=0), the port inputs SDA and SCL are recognized by the device.
If inactive (/CE=1), the port input pins SDA and SCL are disabled making 2-wire communication
impossible.

is less than 8 volts the series wiper resistance will increase

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DS1808

A0, A1, A2 – Address Inputs. These input pins specify the address of the device when used in a multi­dropped configuration. Up to eight individual DS1808s may be addressed on a single 2-wire bus.

H0, H1 – These are the high-end terminals of the potentiometers. For both potentiometers, it is not
required that these terminals be connected to a potential greater than the low-end terminal of the
potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power supply
voltage, VCC, or go below VB.

L0, L1 – These are the low-end terminals of the potentiometers. It is not required that these terminals be
connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the
potentiometers cannot exceed the power-supply voltage, VCC, or go below VB.

W0, W1 – Wiper of the Potentiometer. This pin is the wiper terminal of the potentiometer. Voltage
applied to either wiper terminal cannot exceed the power-supply voltage, VCC, or go below VB.

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DS1808

OPERATION

The DS1808 is a dual-channel, digitally controlled, logarithmic potentiometer. Each potentiometer has
three accessible terminals, which include H, L, and W. Between each resistor element is a tap-point that is
multiplexed to the wiper terminal, W. A block diagram of the DS1808 is shown in Figure 1.

Potentiometer Characteristics

The DS1808 is a volatile device and always powers-up with the wiper positions set to the mute position
(33-decimal) with 90-dB of signal attenuation. The resistor section of the DS1808 is composed of two 32­position resistor arrays that provide a logarithmic attenuation. The resistor section of the DS1808
provides a typical 50kW end-to-end resistance between the H terminal and the L terminal. The wiper
terminal will have a total possible 34 tap positions. The 34th position is considered the mute position and
will provide attenuation in excess of 90dB.

The potentiometers of the DS1808 are closely matched and provide excellent tracking. Interchannel
matching for the device is specified to provide less than 0.5dB. Tap-to-tap tolerances for the device are
specified to provide less than 0.5dB.

Power Supplies

The DS1808 is designed to be powered from dual ±12V supplies. The maximum input signal that can be
placed across the potentiometer sections is ±12V. The device can also be powered using a single +12V
power source. When using the device in a single supply configuration, VB is set to 0V and the maximum
potentiometer input signals are restricted to single supply voltage rails.

Controlling the Potentiometers

All writing and reading to the potentiometers is done with the industry standard 2-wire interface, which
includes pins SDA and SCL.

2-WIRE SERIAL PORT OPERATION

The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a master. The devices that are controlled by the
master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL),
controls the bus access, and generates the start and stop conditions. The DS1808 operates as a slave on
the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The
following I/O terminals control the 2-wire serial port: /CE, SDA, SCL, A0, A1, A2. Timing diagrams for
the 2-wire serial port can be found in Figures 2 and 7.

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DS1808

2-WIRE SERIAL PROTOCOL

The following bus protocol has been defined:

§ Data transfer may be initiated only when the bus is not busy.

§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in the

data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain high.

Start data transfer: A change in the state of the data line from high to low while the clock is high

defines a start condition.

Stop data transfer: A change in the state of the data line from low to high while the clock line is high
defines the stop condition.

Data valid: The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line can be changed during
the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how
data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between start and stop conditions is not limited and is determined by the master
device. The information is transferred byte-wise and each receiver acknowledges with a 9th bit.

Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1808 works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an “acknowledge” after the
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the master to generate the stop condition.

1. The following occurs when data is transferred from a master transmitter to a slave receiver. The first

byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.

2. The following occurs when data is transferred from a slave transmitter to a master receiver. The

master transmits the first byte (the command/control byte) to the slave. The slave then returns an
acknowledge bit. Next, follows a number of data bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” can be returned.

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DS1808

The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended
with a stop condition or with a repeated start condition. Since a repeated start condition is also the
beginning of the next serial transfer, the bus will not be released.

The DS1808 may operate in the following two modes:

1. Slave receiver mode: Serial data and clock are received through SDA and SCL respectively. After

each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address recognition is performed by hardware after
reception of the slave (device) address and direction bit.

2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.

However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1808 while the serial clock is input on SCL. Start and stop conditions
are recognized as the beginning and end of a serial transfer.

3. Slave Address: command/control byte is the first byte received following the start condition from the

master device. The command/control byte consists of a 4-bit control code. For the DS1808, this is set
as 0101 binary for read/write operations. The next three bits of the command/control byte are the
device select bits or slave address (A2, A1, A0). They are used by the master device to select which
of eight devices is to be accessed. When reading or writing the DS1808, the device select bits must
match the device select pins (A2, A1, A0). The last bit of the command/control byte (R/W) defines
the operation to be performed. When set to a 1, a read operation is selected, and when set to a 0, a
write operation is selected.

Following the START condition, the DS1808 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the 0101 control code, the appropriate device address bits, and the
read/write bit, the slave device outputs an acknowledge signal on the SDA line.

COMMAND AND PROTOCOL

The command and protocol structure of the DS1808 allows the user to read from or write to the
potentiometer(s). Additionally, the 2-wire command/protocol structure of the DS1808 will support eight
different devices and a maximum of 16 channels that can be uniquely controlled. The command
structures for the device are presented in Figures 3, 4, 5, and 6. Potentiometer data values and
command/control values are always transmitted most significant bit (MSB) first. During communications,
the receiving unit always generates the acknowledgement.

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