Dallas Semiconductor DS1742-100, DS1742W-150, DS1742W-120, DS1742-70 Datasheet
www.dalsemi.com
A8A
A
DS1742
Y2KC Nonvolatile Timekeeping RAM
FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identical to the
static RAM. These registers are resident in
the eight top RAM locations
Century byte register
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100
Battery voltage level indicator flag
Power-fail write protection allows for ±10%
VCC power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Standard JEDEC bytewide 2k x 8 static RAM
pinout
Quartz accuracy ±1 minute a month @ 25°C,
factory calibrated
PIN ASSIGNMENT
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
9
WE
OE
10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
PIN DESCRIPTION
A0-A10 - Address Inputs
CE - Chip Enable
OE - Output Enable
WE - Write Enable
V
CC
GND - Ground
DQ0-DQ7 - Data Input/Outputs
- Power Supply Input
ORDERING INFORMATION
DS1742-XXX (5V)
-70 70 ns access
-100 100 ns access
DS1742W-XXX (3.3V)
-120 120 ns access
-150 150 ns access
DESCRIPTION
The DS1742 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8
non-volatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide
interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the
eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year
are made automatically.
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DS1742
The RTC clock registers are double-buffered to avoid access of incorrect data that can occur durin g clock
update cycles. The double buffered system also prevents time loss as the timekeeping countdown
continues unabated by access to time register data. The DS1742 also contains its own power-fail
circuitry, which deselects the device when the VCC supply is in an out of tolerance condition. This feature
prevents loss of data from unpredictable system operation brought on by low VCC as errant access and
update cycles are avoided.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chanc e of r eadin g incor rect d ata, internal updates
to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accurac y.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count,
that is day, date, and time that was current at the moment the halt command was issued. However, the
internal clock registers of the double-buffered system continue to update so that the clock accuracy is not
affected by the access of data. All of the DS1742 registers are updated simultaneously after the internal
clock register updating process has been re-enabled. Updating is within a second after the read bit is
written to 0. The READ bit must be a zero for a minimum of 500 µs to ensure the external registers wil l
be updated.
DS1742 BLOCK DIAGRAM Figure 1
DS1742 TRUTH TABLE Table 1
V
CC
VCC>V
VSO<VCC<V
VCC<VSO<V
PF
CE OE WE
V
V
V
V
PF
PF
X X DESELECT HIGH-Z STANDBY
IH
XVILWRITE DATA IN ACTIVE
IL
V
IL
V
IL
IL
IH
V
V
IH
IH
X X X DESELECT HIGH-Z CMOS STANDBY
X X X DESELECT HIGH-Z DATA RETENTION MODE
MODE
READ DATA OUT ACTIVE
READ HIGH-Z ACTIVE
DQ
POWER
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1742 registers. The user can then load them with the correct da y, date and
time data in 24-hour BCD format. Resetting the write bit to a 0 then transfe rs those values to the actual
clock counters and allows normal operation to resume.
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DS1742
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as lon g as conditions for
access remain valid (i.e.,
CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY
The DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements. The DS1742 does
not require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. Clock accuracy is also effected by the electrical environment and caution should be taken
to place the RTC in the lowest level EMI section of the PCB layout. For additional information please
see application note 58.
DS1742 REGISTER MAP Table 2
ADDRESS
7FF 10 Year YEAR YEAR 00-99
7FE X X X 10 Mo MONTH MONTH 01-12
7FD X X 10 Date DATE DATE 01-31
7FC BF FT X X X DAY DAY 01-07
7FB X X 10 HOUR HOUR HOUR 00-23
7FA X 10 MINUTES MINUTES MINUTES 00-59
7F9
7F8 W R 10 CENTURY CENTURY CONTROL 00-39
OSC = STOP BIT
B
OSC
7
B
6
B
5
10 SECONDS SECONDS SECONDS 0 0-59
W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG
DATA
B
4
B
3
B
B
2
B
1
0
FUNCTION/RANGE
R = READ BIT FT = FREQUENCY TEST
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device archit ecture allows ripplethrou gh access to any of the address locati ons
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the
and states are not met, valid data will be available at the latter of chip enable access (t
enable access time (t
the outputs are activated before t
CE , and OE access times and states are s atisfied. If CE , or OE access times
) or at output
CEA
). The state of the data input/output pins (DQ) is controlled by CE , and OE. If
OEA
, the data lines are driven to an intermediate state until tAA. If the
AA
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DS1742
address inputs are changed while CE , and OE remain valid, output data will remain valid for output data
hold time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE , on CE . The addresses must be held valid throughout
the cycle. CE , or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs t
after WE goes active.
WEZ
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when VCC is greater than V
However, when VCC is below the power fail point, V
, (point at which write protection occurs) the
PF
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (
below the battery switch point V
) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
RST
(battery supply level), device power is switched from the VCC pin to
SO
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is
greater than V
time the power fail reset output signal (
nominal levels. If V
when V
CC
backup supply (V
the battery until V
pull up. Except for the
. When VCC falls below the power fail point, VPF, access to the device is inhibited. At this
PF
) is driven active and will remain active until VCC returns to
RST
is less than Vso, the device power is switched from VCC to the backup supply (V
PF
drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the
) when VCC drops below Vso. RTC operation and SRAM data are maintained from
BAT
is returned to nominal levels. The
CC
, all control, data, and address signals must be powered down when VCC is
RST
signal is an open drain output and requires a
RST
powered down.
PF
BAT
.
)
BATTERY LONGEVITY
The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectanc y is 10 years at 25°C with the internal clock os cillator running in
the absence of V
power. Each DS1742 is shipped from Dallas Semiconductor with its lithium energy
CC
source disconnected, guaranteein g full energy capacit y. When VCC is first applied at a level greater than
, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
V
PF
DS1742 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
BATTERY MONITOR
The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energ y source is indicated
and both the contents of the RTC and RAM are questionable.
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