DS1707/DS1708
DS1707/DS1708
3.3 and 5.0 Volt MicroMonitor
FEATURES
• Holds microprocessor in check during power tran-
sients
• Automatically restarts microprocessor after power
failure
• Monitors pushbutton for external override
• Accurate 5%, 10% or 20% resets for 3.3 systems and
5% or 10% resets for 5.0 volt systems
• Eliminates the need for discrete components
• 20% tolerance compatible with 3.0 volt systems
• Pin compatible with the MAXIM MAX707/MAX708 in
8–pin DIP and 8–pin SOIC packages
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages
available
• Industrial temperature range –40°C to +85°C
DESCRIPTION
The DS1707/DS1708 3.3 or 5.0 Volt MicroMonitor monitors three vital conditions for a microprocessor: power
supply, voltage sense, and external override. A precision temperature–compensated reference and
comparator circuit monitors the status of VCC at the
device and at an upstream point for maximum protection. When the sense input detects an out–of–tolerance
PIN ASSIGNMENT
PBRST
PBRST
1
2
V
CC
3
GND
4
IN
8–PIN DIP
(300 MIL)
V
CC
GND
IN
8–PIN SOIC
(150 MIL)
PBRST
V
CC
GND
IN
8–PIN µ–SOP
See Mech. Drawings
1
2
3
4
1
2
3
4
(118 MIL)
Section
DS1707 and DS1708_/R/S/T
RST
8
RST
7
6
NC
5
NMI
RST
8
7
RST
6
NC
5
NMI
8
RST
7
RST
6
NC
5
NMI
PIN DESCRIPTION
PBRST – Pushbutton Reset Input
V
CC
GND – Ground
IN – Input
NMI
NC – No Connect
RST – Active Low Reset Output
RST – Active High Reset Output
condition a non–maskable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When VCC returns to an in–tolerance condition,
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
– Power Supply
– Non–maskable Interrupt
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
010996 1/9
DS1707/DS1708
The third function the DS1707/DS1708 performs is
pushbutton reset control. The DS1707/DS1708
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
OPERATION
Power Monitor
The DS1707/DS1708 detects out–of–tolerance power
supply conditions and warns a processor–based system of impending power failure. When VCC falls below
the minimum V
RST and RST
tolerance, a comparator outputs the
CC
signals. RST and RST are excellent control signals for a microprocessor, as processing is
stopped at the last possible moment of valid V
CC
. On
power–up, RST and RST are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
Pushbutton Reset
The DS1707/DS1708 provides an input pin for direct
connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally, this input is debounced and timed such that
RST and RST
signals of at least 130 ms minimum will be
generated. The 130 ms delay commences as the pushbutton reset input is released from the low level. The
pushbutton can be initiated by connecting the NMI
out-
put to the PBRST input as shown in Figure 3.
Non–Maskable Interrupt
The DS1707/DS1708 generates a non–maskable interrupt (NMI) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an internal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from a higher
DC voltage level closer to the main system power input.
Since the IN trip point V
is 1.25 volts, the proper val-
TP
ues for R1 and R2 can be determined by the equation as
shown in Figure 5. Proper operation of the
DS1707/DS1708 requires that the voltage at the IN pin
be limited to V
voltage at the supply being monitored (V
. Therefore, the maximum allowable
CC
MAX
) can also
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply system, maximizing the amount of time for system shut–
down between NMI
and RST/RST.
When the supply being monitored decays to the voltage
sense point, the DS1707/DS1708 pulses the NMI
output to the active state for a minimum 200 µs. The NMI
power fail detection circuitry also has built–in hysteresis
of 100 µV . The supply must be below the voltage sense
point for approximately 5 µs before a low NMI
will be
generated. In this way , power supply noise is removed
from the monitoring function, preventing false interrupts. During a power–up, any detected IN pin levels
below VTP by the comparator are disabled from generating an interrupt until VCC rises to V
any potential NMI
reaches V
Connecting NMI
pulse will not be initiated until V
.
CCTP
to PBRST would allow the non–mask-
. As a result,
CCTP
CC
able interrupt to generate an automatic reset when an
out–of–tolerance condition occurred in a monitored
supply. An example is shown in Figure 3.
010996 2/9
MICROMONITOR BLOCK DIAGRAM Figure 1
DS1707/DS1708
IN
–
+
T.C.
V
PBRST
REFERENCE
CC
–
+
LEVEL SENSE
DEBOUNCE
AND
PUSHBUTTON RESET Figure 2
5V
UPSTREAM
SUPPLY
VOLTAGE
DIGITAL
SAMPLER
DIGITAL
SAMPLER DIGITAL
PBRST
V
GND
CC
DS1708
IN
RST
RST
NC
NMI
DELAY
RST
INT0
8051
µP
NMI
RST
RST
PUSHBUTTON RESET CONTROLLED BY NMI Figure 3
PBRST
V
UPSTREAM
SUPPLY
VOLTAGE
5V
CC
DS1707
GND
IN
RST
RST
NC
NMI
µP
RST
010996 3/9