Dallas Semiconductor DS1706T, DS1706S, DS1706R, DS1706P, DS1706L Datasheet

DSDS1705/DS1706

DS1705/DS1706

3.3 and 5.0 Volt MicroMonitor

FEATURES

• Halts and restarts an out–of–control microprocessor

• Holds microprocessor in check during power tran-

sients

• Automatically restarts microprocessor after power

failure

• Monitors pushbutton for external override

• Accurate 5%, 10% or 20% resets for 3.3 systems and

5% or 10% resets for 5.0 volt systems

• Eliminates the need for discrete components

• 3.3 volt 20% tolerance for use with 3.0 volt systems

• Pin compatible with the MAXIM MAX705/MAX706 in

8–pin DIP and 8–pin SOIC

• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages

• Industrial temperature range –40°C to +85°C

DESCRIPTION

The DS1705/DS1706 3.3 or 5.0 Volt MicroMonitor moni­tors three vital conditions for a microprocessor: power
supply, software execution, and external override. A
precision temperature compensated reference and
comparator circuit monitors the status of V
device and at an upstream point for maximum protec­tion. When the sense input detects an out–of–tolerance

CC

at the

PIN ASSIGNMENT

PBRST

PBRST

1
2

V

CC

GND

3

IN

4
8–PIN DIP

(300 MIL)

V

CC

GND

IN

8–PIN SOIC

(150 MIL)

PBRST

VCC
GND

IN

8–PIN µ–SOP

See Mech. Drawings

1
2
3
4

1
2
3
4

(118 MIL)

Section

7
6
5

8
7
6
5

8
7
6
5

RST
ST
NMI

WDS
RST (*RST)
ST
NMI

WDS
RST (*RST)
ST
NMI

WDS

8

DS1705 and DS1706_/R/S/T (*DS1706L and DS1706P)

PIN DESCRIPTION

PBRST – Pushbutton Reset Input
V

CC

GND – Ground
IN – Input
NMI
ST
RST
*RST – Active High Reset Output

WDS

condition a non–maskable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When VCC returns to an in–tolerance condition,
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.

– Power Supply

– Non–maskable Interrupt
– Strobe Input
– Active Low Reset Output

(DS1706P and DS1706L only)

– Watchdog Status Output

Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.

011296 1/10

DS1705/DS1706

The second function the DS1705/DS1706 performs is
pushbutton reset control. The DS1705/DS1706
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.

The third function is a watchdog timer. The
DS1705/DS1706 has an internal timer that forces the
WDO signal to the active state if the strobe input is not
driven low prior to time–out.

OPERATION
Power Monitor

The DS1705/DS1706 detects out–of–tolerance power
supply conditions and warns a processor–based sys­tem of impending power failure. When VCC falls below
the minimum VCC tolerance, a comparator outputs the
RST (or RST) signal. RST (or RST) is an excellent con­trol signal for a microprocessor, as processing is
stopped at the last possible moment of valid V

CC

. On
power–up, RST (or RST) are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.

Pushbutton Reset

The DS1705/DS1706 provides an input pin for direct
connection to a push–button reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally , this input is debounced and timed such that a
RST (or RST) signal of at least 130 ms minimum will be
generated. The 130 ms delay commences as the push­button reset input is released from the low level. The
push–button can be initiated by connecting the WDS

outputs to the PBRST input as shown in Figure 3.

NMI

or

Non–Maskable Interrupt

The DS1705/DS1706 generates a non–maskable inter­rupt (NMI) for early warning of a power failure. A preci­sion comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an inter­nal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from a higher
DC voltage level closer to the main system power input.
Since the IN trip point V
ues for R1 and R2 can be determined by the equation as
shown in Figure 5. Proper operation of the

is 1.25 volts, the proper val-

TP

DS1705/DS1706 requires that the voltage at the IN pin
be limited to V
voltage at the supply being monitored (V

. Therefore, the maximum allowable

CC

MAX

) can also
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply sys­tem, maximizing the amount of time for system shut–
down between NMI

and RST (or RST).

When the supply being monitored decays to the voltage
sense point, the DS1705/DS1706 pulses the NMI

out­put to the active state for a minimum 200 µs. The NMI
power fail detection circuitry also has built–in hysteresis
of 100 µV . The supply must be below the voltage sense
point for approximately 5 µs before a low NMI will be
generated. In this way , power supply noise is removed
from the monitoring function, preventing false inter­rupts. During a power–up, any detected IN pin levels
below V
ating an interrupt until VCC rises to V
any potential NMI pulse will not be initiated until V
reaches V

Connecting NMI

by the comparator are disabled from gener-

TP

CCTP

.

. As a result,

CCTP

to PBRST would allow non–maskable

CC

interrupt to generate an automatic reset when an out–
of–tolerance condition occurred in a monitored supply.
An example is shown in Figure 3.

Watchdog Timer

The watchdog timer function forces WDS signals active
when the ST
time out period. Timeout of the watchdog starts when
RST
tion occurs on the ST input pin prior to time–out, the
watchdog timer is reset and begins to time–out again. If
the watchdog timer is allowed to time out, the WDS
nal is driven active (low) for a minimum of 130 ms. The
ST input can be derived from many microprocessor out­puts. The typical signals used are the microprocessors
address signals, data signals, or control signals. When
the microprocessor functions normally, these signals
would, as a matter of routine, cause the watchdog to be
reset prior to time–out. T o guarantee that the watchdog
timer does not time–out, a high–to–low transition must
occur at or less than the minimum watchdog time–out of
1 second. A typical circuit example is shown in Figure 6.

input is not clocked within the 1 second

(or RST) becomes inactive. If a high–to–low transi-

sig-

011296 2/10

MICROMONITOR BLOCK DIAGRAM Figure 1

DS1705/DS1706

IN

–
+

T.C.

V

PBRST

REFERENCE

CC

ST

–
+

LEVEL SENSE

DEBOUNCE

AND

PUSH–BUTTON RESET Figure 2

PBRST

V

CC

GND

IN

DIGITAL

SAMPLER

DIGITAL

SAMPLER DIGITAL

WATCHDOG

WDS

DS1706P

RST

ST

NMI

DELAY

STATUS

LATCH

RST

ALE

8051

µP

NMI

RST

DS1706_/A/R/S/T

DS1706L/DS1706P

RST

WDS

PUSH–BUTTON RESET CONTROLLED BY NMI AND WDS Figure 3

WDS

RST

ST

NMI

UPSTREAM

SUPPLY

VOLTAGE

PBRST

V

GND

CC

DS1706

IN

µP

RST

ALE

011296 3/10

DS1705/DS1706

TIMING DIAGRAM: PUSHBUTTON RESET Figure 4

t

PBRST

RST

RST

PDLY

t

PB

V

IL

NON–MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5

V

IH

t

RST

V

OH

V

OL

V

SENSE

V

SENSE

Example: V

Therefore:

PBRST

V

CC

GND

R1

R2

R1  R2



SENSE

= 3.3 volts

V

CC

10KΩ = R2

4.50

1.25

4.5 

IN

x1.25

R2

= 4.50 volts at the trip point

x3.312.4 volts maximum

R1  10K

x1.25 R126K

10K

DS1706

V

WDS
RST

ST

NMI

MAX

TO µP

V

SENSE



xV

V

TP

CC

011296 4/10

WATCHDOG TIMER Figure 6

DS1705/DS1706

PBRST

V

CC

WDS

RST

DS1706

GND

IN

ST

NMI

TIMING DIAGRAM: STROBE INPUT Figure 7

ST

WDS

RST

INVALID

STROBE

RESET INITIATED
BY PUSHBUTTON

VALID

STROBE

Z80

µP

RST

MREQ

DECODER

ADDRESS

BUS

INDETERMINATE

STROBE

MIN.

t

TD

MAX.

TIMING DIAGRAM: NON–MASKABLE INTERRUPT Figure 8

VIN > 1.25V

V

TP(MAX)

V

NMI

TP

V

TP(MIN)

t

IPD

V

OL

V

TP(MIN)

V

t

IPD

V

TP(MAX)

TP

V

OH

011296 5/10

DS1705/DS1706

TIMING DIAGRAM: POWER DOWN Figure 9

V

CC

V

CCTP(MAX)

V

CCTP

t

RPD

RST
(DS1705 AND DS1706_/R/S/T)

V

CCTP(MIN)

t

F

RST
(DS1706L AND DS1706P ONLY)

WDS

WDS SLEWS WITH V

V

OH

V

OL

CC

RST SLEWS WITH V

CC

011296 6/10

TIMING DIAGRAM: POWER UP Figure 10

V

CCTP(MIN)

V

CC

V

CCTP

V

CCTP(MAX)

t

RPU

RST

RST

RST
(DS1705 AND DS1706_/R/S/T)

V

OH

V

OL

RST
(DS1706L AND DS1706P ONLY)

DS1705/DS1706

WDS

011296 7/10

DS1705/DS1706

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Pin Relative to Ground –0.5V to +7.0V
Voltage on I/O Relative to Ground –0.5V to V
Operating Temperature –40°C to +85°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

CC

+ 0.5V

RECOMMENDED DC OPERATING CONDITIONS (–40°C to +85°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Supply Voltage V
ST and PBRST Input High Level V

ST and PBRST Input Low Level V

CC

IH

IL

1.0 5.5 V 1

2.0
–0.5

V

CC

VCC+0.3 V 1, 3

–0.03 +0.5 V 1

1, 4

DC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC=1.2V to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VCC Trip Point DS1705/DS1706L V
VCC Trip Point DS1706 V
VCC Trip Point DS1706T V
VCC Trip Point DS1706S V
VCC Trip Point DS1706P or R V
Input Leakage I
Output Current @ 2.4 volts I
Output Current @ 0.4 volts I
Output Voltage @ –500 µA V
Operating Current

< 5.5 volts

@ V

CC

Operating Current

< 3.6 volts

@ V

CC

IN Input Trip Point V

CCTP
CCTP
CCTP
CCTP
CCTP

IL
OH
OL

OH

I

CC

I

CC

TP

4.50 4.65 4.75 V 1

4.25 4.40 4.50 V 1

3.00 3.08 3.15 V 1

2.85 2.93 3.00 V 1

2.55 2.63 2.70 V 1
–1.0 +1.0 µA 2

350 µA 3

10 mA 3

VCC+–0.3 VCC–0.1 V 3

60 µA 5

50 µA 5

1.20 1.25 1.30 V 1

CAPACITANCE (tA=25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C
Output Capacitance C

011296 8/10

IN

OUT

5 pF
7 pF

DS1705/DS1706

AC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC=1.2V to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

PBRST = V

IL

Reset Active Time t
ST Pulse Width t
VCC Detect to RST and RST t
VCC Slew Rate t
VCC Detect to RST and RST t
VCC Slew Rate t
PBRST Stable Low to RST and

RST
Watchdog Timeout t
VIN Detect to NMI t

t

PB

RST

ST

RPD

RPU

t

PDLY

TD

IPD

150 ns
130 205 285 ms

10 ns 6

5 8 µs 9

F

20 µs

130 205 285 ms 7

R

0 ns

250 ns

1.0 1.6 2.2 s 8
5 8 µs 9

NOTES:

1. All voltages are referenced to ground.

2. PBRST

3. V

4. V

5. Measured with outputs open and all inputs at V

6. Must not exceed t

7. t

8. Minimum watchdog timeout tested at 2.7 volts for the 3.3 volt devices and 4.5 volts for the 5.0 volt devices.

9. Noise immunity – pulses < 2 µs at V

is internally pulled up to VCC with an internal impedance of 40KΩ typical and the ST input is internally

pulled up to VCC with an internal impedance of 180KΩ typical.

 2.4 volts

CC

< 2.4 volts

CC

or ground.

CC

minimum.

TD

= 5 µs

R

minimum will not cause a reset.

CCTP

011296 9/10

DS1705/DS1706

PART MARKING CODES

8765

ABCD

WWY

1234

8–PIN µ–SOP

(118 MIL)

A, B, C and D represents the device type and tolerance.

ABCD
705_ – DS1705
706_ – DS1706
706L – DS1706L
706P – DS1706P
706R – DS1706R
706S – DS1706S
706T – DS1706T

WWY represents the device manufacturing W
Week, Year.

ork

011296 10/10