Dallas Semiconductor DS1706T, DS1706S, DS1706R, DS1706P, DS1706L Datasheet
...
DSDS1705/DS1706
DS1705/DS1706
3.3 and 5.0 Volt MicroMonitor
FEATURES
• Halts and restarts an out–of–control microprocessor
• Holds microprocessor in check during power tran-
sients
• Automatically restarts microprocessor after power
failure
• Monitors pushbutton for external override
• Accurate 5%, 10% or 20% resets for 3.3 systems and
5% or 10% resets for 5.0 volt systems
• Eliminates the need for discrete components
• 3.3 volt 20% tolerance for use with 3.0 volt systems
• Pin compatible with the MAXIM MAX705/MAX706 in
8–pin DIP and 8–pin SOIC
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages
• Industrial temperature range –40°C to +85°C
DESCRIPTION
The DS1705/DS1706 3.3 or 5.0 Volt MicroMonitor monitors three vital conditions for a microprocessor: power
supply, software execution, and external override. A
precision temperature compensated reference and
comparator circuit monitors the status of V
device and at an upstream point for maximum protection. When the sense input detects an out–of–tolerance
CC
at the
PIN ASSIGNMENT
PBRST
PBRST
1
2
V
CC
GND
3
IN
4
8–PIN DIP
(300 MIL)
V
CC
GND
IN
8–PIN SOIC
(150 MIL)
PBRST
VCC
GND
IN
8–PIN µ–SOP
See Mech. Drawings
1
2
3
4
1
2
3
4
(118 MIL)
Section
7
6
5
8
7
6
5
8
7
6
5
RST
ST
NMI
WDS
RST (*RST)
ST
NMI
WDS
RST (*RST)
ST
NMI
WDS
8
DS1705 and DS1706_/R/S/T (*DS1706L and DS1706P)
PIN DESCRIPTION
PBRST – Pushbutton Reset Input
V
CC
GND – Ground
IN – Input
NMI
ST
RST
*RST – Active High Reset Output
WDS
condition a non–maskable interrupt is generated. As
the voltage at the device degrades an internal power fail
signal is generated which forces the reset to an active
state. When VCC returns to an in–tolerance condition,
the reset signal is kept in the active state for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
– Power Supply
– Non–maskable Interrupt
– Strobe Input
– Active Low Reset Output
(DS1706P and DS1706L only)
– Watchdog Status Output
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
011296 1/10
DS1705/DS1706
The second function the DS1705/DS1706 performs is
pushbutton reset control. The DS1705/DS1706
debounces the pushbutton input and guarantees an
active reset pulse width of 130 ms minimum.
The third function is a watchdog timer. The
DS1705/DS1706 has an internal timer that forces the
WDO signal to the active state if the strobe input is not
driven low prior to time–out.
OPERATION
Power Monitor
The DS1705/DS1706 detects out–of–tolerance power
supply conditions and warns a processor–based system of impending power failure. When VCC falls below
the minimum VCC tolerance, a comparator outputs the
RST (or RST) signal. RST (or RST) is an excellent control signal for a microprocessor, as processing is
stopped at the last possible moment of valid V
CC
. On
power–up, RST (or RST) are kept active for a minimum
of 130 ms to allow the power supply and processor to
stabilize.
Pushbutton Reset
The DS1705/DS1706 provides an input pin for direct
connection to a push–button reset (see Figure 2). The
pushbutton reset input requires an active low signal.
Internally , this input is debounced and timed such that a
RST (or RST) signal of at least 130 ms minimum will be
generated. The 130 ms delay commences as the pushbutton reset input is released from the low level. The
push–button can be initiated by connecting the WDS
outputs to the PBRST input as shown in Figure 3.
NMI
or
Non–Maskable Interrupt
The DS1705/DS1706 generates a non–maskable interrupt (NMI) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin
relative to an on–chip reference generated by an internal band gap. The IN pin is a high impedance input
allowing for a user–defined sense point. An external
resistor voltage divider network (Figure 5) is used to
interface with high voltage signals. This sense point
may be derived from a regulated supply or from a higher
DC voltage level closer to the main system power input.
Since the IN trip point V
ues for R1 and R2 can be determined by the equation as
shown in Figure 5. Proper operation of the
is 1.25 volts, the proper val-
TP
DS1705/DS1706 requires that the voltage at the IN pin
be limited to V
voltage at the supply being monitored (V
. Therefore, the maximum allowable
CC
MAX
) can also
be derived as shown in Figure 5. A simple approach to
solving the equation is to select a value for R2 high
enough to keep power consumption low, and solve for
R1. The flexibility of the IN input pin allows for detection
of power loss at the earliest point in a power supply system, maximizing the amount of time for system shut–
down between NMI
and RST (or RST).
When the supply being monitored decays to the voltage
sense point, the DS1705/DS1706 pulses the NMI
output to the active state for a minimum 200 µs. The NMI
power fail detection circuitry also has built–in hysteresis
of 100 µV . The supply must be below the voltage sense
point for approximately 5 µs before a low NMI will be
generated. In this way , power supply noise is removed
from the monitoring function, preventing false interrupts. During a power–up, any detected IN pin levels
below V
ating an interrupt until VCC rises to V
any potential NMI pulse will not be initiated until V
reaches V
Connecting NMI
by the comparator are disabled from gener-
TP
CCTP
.
. As a result,
CCTP
to PBRST would allow non–maskable
CC
interrupt to generate an automatic reset when an out–
of–tolerance condition occurred in a monitored supply.
An example is shown in Figure 3.
Watchdog Timer
The watchdog timer function forces WDS signals active
when the ST
time out period. Timeout of the watchdog starts when
RST
tion occurs on the ST input pin prior to time–out, the
watchdog timer is reset and begins to time–out again. If
the watchdog timer is allowed to time out, the WDS
nal is driven active (low) for a minimum of 130 ms. The
ST input can be derived from many microprocessor outputs. The typical signals used are the microprocessors
address signals, data signals, or control signals. When
the microprocessor functions normally, these signals
would, as a matter of routine, cause the watchdog to be
reset prior to time–out. T o guarantee that the watchdog
timer does not time–out, a high–to–low transition must
occur at or less than the minimum watchdog time–out of
1 second. A typical circuit example is shown in Figure 6.
input is not clocked within the 1 second
(or RST) becomes inactive. If a high–to–low transi-
sig-
011296 2/10
MICROMONITOR BLOCK DIAGRAM Figure 1
DS1705/DS1706
IN
–
+
T.C.
V
PBRST
REFERENCE
CC
ST
–
+
LEVEL SENSE
DEBOUNCE
AND
PUSH–BUTTON RESET Figure 2
PBRST
V
CC
GND
IN
DIGITAL
SAMPLER
DIGITAL
SAMPLER DIGITAL
WATCHDOG
WDS
DS1706P
RST
ST
NMI
DELAY
STATUS
LATCH
RST
ALE
8051
µP
NMI
RST
DS1706_/A/R/S/T
DS1706L/DS1706P
RST
WDS
PUSH–BUTTON RESET CONTROLLED BY NMI AND WDS Figure 3
WDS
RST
ST
NMI
UPSTREAM
SUPPLY
VOLTAGE
PBRST
V
GND
CC
DS1706
IN
µP
RST
ALE
011296 3/10
Loading...