DS1672
A
Low Voltage Serial Timekeeping Chip
FEATURES
32-bit counter
2-wire serial interface
Automatic power-fail detect and switch
circuitry
Power-fail reset output
Low-voltage oscillator operation (1.3V min.)
Trickle charge capability
ORDERING INFORMATION
DS1672X-X
2 2.0V operation
3 3.0V operation
33 3.3V operation
blank 8-pin DIP
S8-pin SOIC
U 8-pin µSOP
PIN ASSIGNMENT
V
8
7
RST
6
SCL
5
SD
V
BACKUP
GND
X1
X2
1
2
3
4
PIN DESCRIPTION
V
CC, VBACKUP
GND - Ground
X1, X2 - 32.768 kHz crystal pins
SCL - Serial clock
SDA - Serial data
RST - Reset output
- Power Supply Inputs
DESCRIPTION
The DS1672 incorporates a 32-bit counter and power monitoring functions. The 32-bit counter is
designed to count seconds and can be used to derive time of day, week, month, month, and year by using
a software algorithm. A precision temperature-compensated reference and comparator circuit monitors
the status of V
. When an out-of-tolerance condition occurs, an internal power-fail signal is generated
CC
which forces the reset to the active st ate. When VCC returns to an in-tolerance condition, the reset signal
is kept in the active state for 250 ms to allow the power supply and processor to stabilize.
OPERATION
The block diagram in Figure 1 shows the main elements of the DS1672. As shown, communications to
and from the DS1672 occur serially over a 2-wire bi-directional bus. The DS1672 operates as a slave
device on the serial bus. Access is obtained by implementing a START condition and providing a device
identification code followed by a register address. Subsequent registers can be accessed sequentially until
a STOP condition is executed.
1 of 13 082800
DS1672 BLOCK DIAGRAM Figure 1
X1 X2
OSCILLATOR
AND DIVIDER
V
CC
V
BACKUP
GND
RST
POWER
CONTROL
DS1672
32-BIT
COUNTER
(4 BYTES)
CONTROL
TRICKLE CHARGER
CONTROL
LOGIC
SCL
SDA
SERIAL BUS
INTERFACE
ADDRESS
REGISTER
ADDRESS MAP
The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h - 03h). The control
register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated
in Figure 2. If the master continues to send or request more data after the address pointer has reached
05h, the address pointer will wrap around to location 00h.
DS1672 REGISTERS Figure 2
AddressB7B6B5B4B3B2B1B0Function
00h Counter
Byte 1
01h Counter
Byte 2
02h Counter
Byte 3
03h Counter
Byte 4
04h
EOSC
05h TCS TCS TCS TCS DS DS RS RS Trickle
Control
Charger
DATA RETENTION MODE
The device is fully accessible and data can be written and ready only when VCC is greater than VPF.
However, when V
are blocked from any access. If VPF is less than V
V
BACKUP
VCC to V
when VCC drops below VPF. If VPF is greater than V
BACKUP
until VCC is returned to nominal levels.
falls below VPF, (point at which write protection occurs) the internal clock re gisters
CC
, the device power is switched from VCC to
BACKUP
, the device power is switched from
BACKUP
when VCC drops below V
BACKUP
BACKUP
. The registers are maintained from the V
2 of 13
source
DS1672
OSCILLATOR CONTROL
The EOSC bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when
set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is placed into a low-power standby mode with a current drain of less than 200 nanoamps when in
back-up mode. When the DS1672 is powered by V
of the
EOSC bit; however, the counter is incremented only when EOSC is a logic 0.
the oscillator is always on regardless of the status
CC,
CRYSTAL SELECTION
A standard 32.768 kHz quartz crystal should be directly connected to the X1 and X2 oscillator pins. The
crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information on
crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
MICROPROCESSOR MONITOR
A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the powerfail trip point, the RST signal (open drain) is pulled active. When VCC returns to nominal levels, the RST
signal is kept in the active state for 250 ms (typically) to allow the power supply and microprocessor to
stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable the oscillator during write
protection), the reset signal will be kept in an active state for 250 ms plus the start-up time of the
oscillator.
TRICKLE CHARGER
The trickle charger is controlled by the trickle charge register. The simplified schematic of Figure 3
shows the basic components of the trickle charger. The trickle charge select (TCS) bit (bits 4-7) controls
the selection of the trickle charger. In order to prevent accidental enablin g, only a pattern on 1010 will
enable the trickle charger. All other patterns will disable the trickle charger. The DS1672 powers up
with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select wheth er or not a diode is
connected between VCC and V
BACKUP
The RS bits (bits 0-1) select whether a r esist or is connect ed b etwe en VCC and V
of the resistor is. The resistor selected by the resistor select (RS) bits and the diode selected by the diode
select (DS) bits are as follows:
TCS TCS TCS TCS DS DS RS RS Function
XXXX 0 0 XXDisabled
XXXX 1 1 XXDisabled
XXXX XX0 0 Disabled
1010 0101
1010 1001
1010 0110
1010 1010
1010 0111
1010 1011
. If DS is 01, no diode is selected or if DS is 10, a diode is selected.
BACKUP
and what the value
No diode, 100Ω resistor
One diode, 100Ω resistor
No diode, 2 kΩ resistor
One diode, 2 kΩ resistor
No diode, 4 kΩ resistor
One diode, 4 kΩ resistor
3 of 13
DS1672
Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 3 volt is applied to VCC and a super cap is
connected to V
BACKUP
between VCC and V
= (3.0V – diode drop) / R2
I
max
. Also assume that the trickle charger has been enabled with a diode and resistor R2
BACKUP
. The maximum current I
would therefore be calculated as follows:
max
~ (3.0V – 0.7V) / 2 kΩ
~ 1.2 mA
Obviously, as the super cap changes, the voltage drop between V
and V
CC
therefore the charge current will decrease.
DS1672 PROGRAMMABLE TRICKLE CHARGER Figure 3
V
CC
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES
TCS TCS TCS TCS DS DS RS RS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 OF 2
SELECT
1 OF 3
SELECT
TCS = TRICKLE CHARGER SELECT
DS = DIODE SELECT
RS = RESISTOR SELECT
BACKUP
will decrease and
R1
Ω
100
R2
2k
Ω
V
BACKUP
Ω
R3
Ω
4k
TRICKLE CHARGE REGISTER
4 of 13
DS1672
2-WIRE SERIAL DATA BUS
The DS1672 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a “master." The devices th at are controlled b y the master are “slaves. ” The
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1672 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see Figure 4).
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be chan ged
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between the START and the STOP conditions is not limited, and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an a cknowledge after the
reception of each byte. The master device must generate an ex tra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
5 of 13
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 4
SDA
MSB
slave address
R/W
direction
bit
acknowledgement
signal from receiver
acknowledgement
signal from receiver
DS1672
SCL
START
CONDITION
12 6789
ACK ACK
12 89
3 - 8
repeated if more bytes
are transferred
STOP CONDITION
OR
REPEATED
START CONDITION
Figures 5 and 6 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2. Data transfer from a slave transmitter to a master rec eiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all re ceived
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1672 may operate in the following two modes:
1. Slave receiver mode (DS1672 write mode): Serial data and clock are received through SDA and
SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions
are recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit. The address byte is the first byte
received after the START condition is generated by the master. The address byte contains the 7-bit
DS1672 address, which is 1101000, followed by the direction bit (R/ W ), which for a write is a 0.
After receiving and decoding the address byte the DS1672 outputs an acknowledge on the SDA line.
After the DS1672 acknowledges the slave address + write bit, the master transmits a register address
to the DS1672. This will set the register pointer on the DS1672. The master will then begin
transmitting each byte of data with the DS1672 acknowledging each byte received. The master will
generate a STOP condition to terminate the data write.
2. Slave transmitter mode (DS1672 read mode): The first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is
reversed. Serial data is transmitted on SDA by the DS1672 while the serial clock is input on SCL.
START and STOP conditions are recogniz ed as the beginning and end of a se rial transfer. Address
recognition is performed by hardware after reception of the slave address and direction bit. The
address byte is the first byte received after the START condition is generated by the master. The
address byte contains the 7-bit DS1672 address, which is 1101000, followed by the direction bit
6 of 13
(R/W ), which for a read is a 1. After receiving and decoding the address byte the DS1672 inputs an
Acknowledge on the SDA line. The DS1672 then begins to transmit data starting with the register
address pointed to by the register pointer. If the register pointer is not written to before the initiation
of a read mode the first address that is read is the last one stored in the re gister pointer. The DS1672
must receive a not acknowledge to end a read.
DATA WRITE – SLAVE RECEIVER MODE Figure 5
DATA READ – SLAVE TRANSMITTER MODE Figure 6
DS1672
7 of 13
DS1672
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature -40°C to +85°C
Storage Temperature -55°C to +125°C
Soldering Temperature See J-STD-020A specification
* This is a stress rating only and functional operation of the device at these or an y other conditions abov e
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (-40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage (DS1672-33)
(DS1672-3)
(DS1672-2)
V
V
V
Logic 1 V
Logic 0 V
Backup Supply Voltage V
BACKUP
CC
CC
CC
IH
IL
2.97 3.3 3.63 V 1
2.7 3.0 3.3 V 1
1.8 2.0 2.2 V 1
0.7V
CC
-0.5 0.3V
V
+ 0.5 V 1
CC
CC
V1
1.3 3.6 V 1
DC ELECTRICAL CHARACTERISTICS
DS1672-33 (-40°C to +85°C; V
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current I
Standby Current
I
Power-Fail Voltage V
CCA
CCS
PF
2.80 2.88 2.97 V 1
2mA7
500
= 2.97 to 3.63V)
CC
µA
8
DC ELECTRICAL CHARACTERISTICS
DS1672-3 (-40°C to +85°C; V
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current I
Standby Current
I
Power-Fail Voltage V
CCA
CCS
PF
2.5 2.6 2.7 V 1
2mA7
500
= 2.7 to 3.3V)
CC
µA
9
DC ELECTRICAL CHARACTERISTICS
DS1672-2 (-40°C to +85°C; V
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current I
Standby Current I
Power-Fail Voltage V
CCA
CCS
PF
1.6 1.7 1.8 V 1
2mA7
500
= 1.8 to 2.2V)
CC
µA
10
DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCC < VPF)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Timekeeping Current I
Backup Standby Current
I
BACKUP
(Oscillator Off)
OSC
8 of 13
1
µA
12
200 nA 13
DS1672
AC ELEC TRICAL CHARACTERI STICS (-40°C to +85°C; VCC > VPF)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES
Fast Mode 100 400SCL Clock
Standard Mode 100
kHz
Frequency
f
SCL
t
Between a STOP
and START
Condition
t
HD:STA
(Repeated) START
Condition
t
SCL Clock
t
SCL Clock
t
SU:STA
Repeated START
Condition
HD:DAT
SU:DAT
SDA and SCL
Signals
SDA and SCL
Signals
t
SU:STO
STOP Condition
Capacitive Load for
each Bus Line
I/O Capacitance C
BUF
LOW
HIGH
t
R
t
F
C
B
I/O
Fast Mode 1.3Bus Free Time
Standard Mode 4.7
Fast Mode 0.6Hold Time
Standard Mode 4.0
Fast Mode 1.3LOW Period of
Standard Mode 4.7
Fast Mode 0.6HIGH Period of
Standard Mode 4.0
Fast Mode 0.6Set-up Time for a
Standard Mode 4.7
Fast Mode 0 0.9Data Hold Time t
Standard Mode 0
Fast Mode 100Data Set-up Time t
Standard Mode 250
Fast Mode 20 + 0.1C
B
300Rise Time of Both
Standard Mode 1000
Fast Mode 20 + 0.1C
B
300Fall Time of Both
Standard Mode 300
Fast Mode 0.6Set-up Time for
Standard Mode 4.0
400 pF 5
10 pF
µs
µs
µs
µs
µs
µs
µs
3, 4
11
ns 5
ns 5
µs
2
9 of 13
Timing Diagram Figure 7
SDA
t
BUF
DS1672
SCL
STOP
START
tLOW
t
HD:STA
t
HD:DAT
t
HIGH
tF
tSU:DAT
POWER-UP/DOWN TIMING Figure 8
V
CC
V
PF(max)
V
PF(min)
t
F
t
PD
t
RPD
RST
INPUTS
RECOGNIZED
t
SU:STA
REPEATED
START
tHD:STA
DON'T CARE
t
t
SU:STO
R
t
RPU
RECOGNIZED
OUTPUTS
VALID
HIGH-Z
VALID
10 of 13
DS1672
POWER-UP DOWN CHARACTERISTICS (-40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Detect to RST (VCC Falling)
VCC Detect to RST (VCC Rising)
VCC Fall Time; V
VCC Rise Time; V
PF(MAX)
PF(MIN)
to V
to V
PF(MIN)
PF(MAX)
t
RPD
t
RPU
250 ms 6
t
F
t
R
300
0
10 µs
µs
µs
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in write
protection.
NOTES:
1. All voltages are referenced to ground.
2. After this period, the first clock pulse is generated.
3. A device must internally provide a hold time of at least 300 ns for the SDA signal (referenced to the
V
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
IHMIN
4. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
SCL signal.
5. CB - total capacitance of one bus line in pF.
6. If the EOSC bit in the Control Register is set to logic 1, t
is equal to 250 ms plus the start-up time
RPU
of the crystal oscillator.
7. I
8. I
9. I
10. I
11. A fast mode device can be used in a standard mode system, but the requirement t
specified with SCL clocking at max frequency (400 kHz).
CCA
specified with VCC = 3.3V and SDA, SCL=3.3V.
CCS
specified with VCC = 3.0V and SDA, SCL=3.0V.
CCS
specified with VCC = 2.0V and SDA, SCL=2.0V.
CCS
>= to 250 ns
SU:DAT
must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SC L signal, it must output the
next data bit to the SDA line t
max + t
R
= 1000+250 = 1250 ns before the SCL line is released.
SU:DAT
) of the
12. I
13. I
specified with VCC = 0V, V
OSC
BACKUP
specified with VCC = 0V, V
BACKUP
BACKUP
=3.6V and oscillator enabled.
=3.6V and oscillator disabled.
11 of 13
8-PIN DIP
PKG 8-PIN
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
0.360
9.14
0.240
6.10
0.120
3.05
0.300
7.62
0.015
0.38
0.120
3.04
0.090
2.29
0.320
8.13
0.008
0.20
0.015
0.38
0.400
10.16
0.260
6.60
0.140
3.56
0.325
8.26
0.040
1.02
0.140
3.56
0.110
2.79
0.370
9.40
0.012
0.30
0.021
0.53
DS1672
12 of 13
8-PIN SOIC (150-MIL)
DS1672
PKG
8-PIN
(150-MIL)
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
L IN.
MM
phi
0.188
4.78
0.150
3.81
0.048
1.22
0.004
0.10
0.053
1.35
0.050 BSC
1.27 BSC
0.230
5.84
0.007
0.18
0.012
0.30
0.016
0.41
0° 8°
0.196
4.98
0.158
4.01
0.062
1.57
0.010
0.25
0.069
1.75
0.244
6.20
0.011
0.28
0.020
0.51
0.050
1.27
13 of 13
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