Dallas Semiconductor DS1642-70, DS1642-100 Datasheet

DS1642

Nonvolatile Timekeeping RAM

www.dalsemi.com

VCCA8A9WEOEA10A7A6A5A4A3A2A1A0

DQ0

DQ1

DQ2

GND

CE

DQ7

DQ6

DQ5

DQ4

DQ3123456789101112242322212019181716151413

FEATURES

§ Integrated NV SRAM, real time clock,

crystal, power fail control circuit and lithium
energy source

§ Standard JEDEC bytewide 2K x 8 static RAM

pinout

§ Clock registers are accessed identically to the

static RAM. These registers are resident in the
eight top RAM locations

§ Totally nonvolatile with over 10 years of

operation in the absence of power

§ Access times of 70 ns and 100 ns

§ Quartz accuracy ±1 minute a month @ 25°C,

factory calibrated

§ BCD coded year, month, date, day, hours,

minutes, and seconds with leap year
compensation valid up to 2100

§ Power-fail write protection allows for ±10%

VCC power supply tolerance

§ Lithium energy source is electrically

disconnected to retain freshness until power is
applied for the first time

PIN ASSIGNMENT

PIN DESCRIPTION

A0-A10 - Address Input

CE
OE
WE

V

CC

GND - Ground
DQ0-DQ7 - Data Input/Output

- Chip Enable

- Output Enable

- Write Enable

- +5 Volts

DESCRIPTION

The DS1642 is a 2K x 8 nonvolatile static RAM and a full-function real time clock which are both
accessible in a bytewide format. The nonvolatile time keeping RAM is pin- and function-equivalent to
any JEDEC standard 2K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets, providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid
access of incorrect data that can occur during clock update cycles. The double-buffered system also

ORDERING INFORMATION

DS1642-70 70 ns access
DS1642-100 100 ns access

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DS1642

prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1642 also contains its own power-fail circuitry which deselects the device when the V

supply is in

CC

an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low VCC as errant access and update cycles are avoided.

CLOCK OPERATIONS-READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1642 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.

DS1642 BLOCK DIAGRAM Figure 1

DS1642 TRUTH TABLE Table 1

V

CC

5 VOLTS ± 10%

<4.5 VOLTS >V

<V

BAT

BAT

CE OE WE

V
V
V
V

IH
IL
IL
IL

X X DESELECT HIGH Z STANDBY

X V
V
V

IL
IH

V

V
X X X DESELECT HIGH Z CMOS STANDBY
X X X DESELECT HIGH Z DATA RETENTION

IL
IH
IH

MODE DQ POWER

WRITE DATA IN ACTIVE

READ DATA OUT ACTIVE
READ HIGH Z ACTIVE

MODE

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DS1642

SETTING THE CLOCK

The 8th bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the DS1642 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The

a 1 stops the oscillator.

bit is the MSB for the seconds registers. Setting it to

OSC

FREQUENCY TEST BIT

Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid

(i.e., CE low, and OE low) and address for seconds register remain valid and stable.

CLOCK ACCURACY

The DS1642 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The clock is
calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements.
The DS1642 does not require additional calibration and temperature deviations will have a negligible
effect in most applications. For this reason, methods of field clock calibration are not available and not
necessary.

DS1642 REGISTER MAP – BANK1 Table 2

ADDRESS

7FF - - - - - - - - YEAR 00-99

7FE X X X - - - - - MONTH 01-12
7FD X X - - - - - - DATE 01-31
7FC X FT X X X - - - DAY 00-23
7FB X X - - - - - - HOUR 00-59
7FA X - - - - - - - MINUTES 00-59

7F9
7F8 W R X X X X X X CONTROL A

= STOP BIT

OSC

W = WRITE BIT X = UNUSED

B7 B6 B5 B4 B3 B2 B1 B0

OSC

- - - - - - - SECONDS 00-59

DATA

R = READ BIT FT = FREQUENCY TEST

FUNCTION

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

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RETRIEVING DATA FROM RAM OR CLOCK

DS1642

The DS1642 is in the read mode whenever

(write enable) is high, and CE (chip enable) is low. The

WE

device architecture allows ripple–through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t

after the last address input is stable, providing that the

AA

CE

and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (t

) or at output enable access time (t

CEA

). The state of the

OEA

data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and

OE

remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1642 is in the write mode whenever
referenced to the latter occurring transition of
the cycle. CE or

must return inactive for a minimum of tWR prior to the initiation of another read or

WE

write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to
the data bus can become active with read data defined by the address inputs. A low transition on
then disable the outputs t

after WE goes active.

WEZ

and CE are in their active state. The start of a write is

WE

or CE. The addresses must be held valid throughout

WE

transitioning low

WE

WE

will

DATA RETENTION MODE

When V
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished

internally by inhibiting access via the CE signal. When VCC falls below the level of the internal battery
supply, power input is switched from the VCC pin to the internal battery and clock activity, RAM, and
clock data are maintained from the battery until VCC is returned to nominal level.

is within nominal limits (V

CC

> 4.5 volts) the DS1642 can be accessed as described above by

CC

BATTERY LONGEVITY

The DS1642 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1642 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1642 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.

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