Dallas Semiconductor DS1554WP-150, DS1554WP-120, DS1554W-150, DS1554W-120, DS1554P-70 Datasheet

www.dalsemi.com

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DS1554

256K NV Y2KC Timekeeping RAM

FEATURES

 Integrated NV SRAM, real time clock, crystal,

power-fail control circuit and lithium energy
source

 Clock registers are accessed identically to the

static RAM; these registers are resident in the
16 top RAM locations

 Century byte register; i.e., Y2K complaint
 Totally nonvolatile with over 10 years of

operation in the absence of power

 Precision power-on reset
 Programmable watchdog timer and RTC alarm
 BCD coded year, month, date, day, hours,

minutes, and seconds with automatic leap year
compensation valid up to the year 2100

 Battery voltage level indicator flag
 Power-fail write protection allows for ±10%

V

power supply tolerance

CC

 Lithium energy source is electrically

disconnected to retain freshness until power is
applied for the first time

PIN ASSIGNMENT

RST
A16
A14
A12

DQ0
DQ1
DQ2

GND

32-PIN ENCAPSULATED PACKAGE

IRQ/FT

NC
NC

RST

V

WE

OE
CE

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

1

2

3
4
5

CC

6
7
8
9
10
11
12
13
14
15
16
17

34-Pin POWERCAP MODULE BOARD

(USES DS9034PCX POWERCAP)

A7
A6
A5
A4
A3
A2
A1

A0

1
2

3
4

5
6

7
8

9
10

11
12

13
14
15
16

X1 GND

V

BAT

32
31

30
29

28
27

26
25

24
23

22
21

20
19
18
17

X2

V

CC

NC
IRQ/FT
WE

11

OE

10

CE
DQ7
DQ6
DQ5
DQ4
DQ3

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

NC
NC

14
13

11
10
9
8
7
6
5
4
3
2

0

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ORDERING INFORMATION

DS1554P-XXX (5-Volt)

-70 70 ns access

-100 100 ns access

blank 32-pin DIP Module
P 34-pin PowerCap Module

board*

*DS1554WP-XXX (3.3 Volt)

-120 120 ns access

-150 150 ns access

blank 32-pin DIP Module
P 34-pin PowerCap Module

board*

*DS9034PCX (PowerCap) Required:

must be ordered seperately

PIN DESCRIPTION

A0-A14 - Address Input
DQ0-DQ7 - Data Input/Outputs

IRQ \FT - Interrupt, Frequency Test Output

(Open Drain)

DS1554

RST - Power-On Reset Output

(Open Drain)

CE - Chip Enable
OE - Output Enable
WE - Write Enable

V

CC

- Power Supply Input
GND - Ground
NC - No Connection
X1, X2 - Crystal Connection

- Battery Connection

V

BAT

DESCRIPTION

The DS1554 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) with a RTC
alarm, watchdog timer, power-on reset, battery monitor, and 32k x 8 non-volatile static RAM. User
access to all registers within the DS1554 is accomplished with a bytewide interface as shown in Figure 1.
The RTC Registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.

The RTC Registers are double-buffered into an internal and external set. The use r has dire ct ac cess to the
external set. Clock/calendar updat es to the external set of re gisters can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers a re
continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTC
information is always maintained.

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DS1554

The DS1554 has interrupt (IRQ /FT) and reset (RST ) outputs which can be used to control CPU activity.
The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC Register values

match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the batter y backed state to serve as a s ystem

wake-up. Either the IRQ /FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is
monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1554 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used
for this function.

The DS1554 also contains its own power-fail circuitry which automatically deselects the device when the
VCC supply enters an out of tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low VCC levels.

PACKAGES

The DS1554 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1554P after the completion of the surface mount process. Mounting the PowerCap aft er the surface
mount process prevents damage to the crystal and battery due to the hi gh tempe ratures requir ed for solde r
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.

DS1554 BLOCK DIAGRAM Figure 1

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DS1554

DS1554 OPERATING MODES Table 1

V

CC

VCC > V

PF

VSO < VCC <V

<V

BAT

CE OE WE

V

IH

V

IL

V

IL

V

IL

PF

X X X HIGH-Z DESELECT CMOS STANDBY
X X X HIGH-Z DATA

X X HIGH-Z DESELECT STANDBY

XVILD
V
V

IL
IH

V
V

DQ0-DQ7 MODE POWER

IN
IH
IH

D

OUT

HIGH-Z READ ACTIVE

WRITE ACTIVE

READ ACTIVE

RETENTION

BATTERY
CURRENT

DATA READ MODE

The DS1554 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available

at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip en able

access (t
controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an
intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data

will remain valid for output data hold time (tOH ) but will then go indeterminate until the next address
access.

) or at output enable access time (t

CEA

). The state of the data input/output pins (DQ) is

OEA

DATA WRITE MODE

The DS1554 is in the write mode whenever WE and CE are in th eir active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent

read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for t

DH

afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE

transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on

WE will then disable the outputs t

after WE goes active.

WEZ

DATA RETENTION MODE

The 5-volt device is fully accessible and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point VPF (point at which write protection occurs) the
internal clock registers and SRAM are bl ocked from any access. W hen V
point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until V
levels.

The 3.3-volt device is fully accessible and data can be written and read only when V
VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than V
power is switched from V
greater than V

drops below V

V

CC

, the device power is switched from VCC to the internal backup lithium battery when

BAT

BAT

to the internal backup lithium battery when VCC drops below VPF. If VPF is

CC

. RTC operation and SRAM data are maintained from the battery until VCC is

returned to nominal levels.

falls below the battery switch

CC

is returned to nominal

CC

is greater than

CC

, the device

BAT

All control, data, and address signals must be powered down when VCC is powered down.

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DS1554

BATTERY LONGEVITY

The DS1554 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the VCC supply is not present. The capability of this internal power
supply is sufficient to power the DS1554 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock
oscillator running in the absence of VCC. Each DS1554 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When V
level greater than V

, the lithium energy source is enabled for battery backup operation. Actual life

PF

is first applied at a

CC

expectancy of the DS1554 will be much longer than 10 years since no internal battery energy is
consumed when VCC is present.

INTERNAL BATTERY MONITOR

The DS15543 constantly monitors the battery voltage of the internal batter. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ev er
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.

POWER-ON RESET

A temperature compensated comparator circuit monitors the level of VCC. When VCC falls to the power
fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the

RST signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is

independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.

CLOCK OPERATIONS

Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.

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DS1554 REGISTER MAP Table 2

ADDRESS

7FFFh 10 Year YEAR YEAR 00-99
7FFEh X X X 10 M MONTH MONTH 01-12
7FFDh X X 10 Date DATE DATE 01-31
7FFCh X FT X X X DAY DAY 01-07
7FFBh X X 10 HOUR HOUR HOUR 00-23
7FFAh X 10 MINUTES MINUTES MINUTES 00-59
7FF9h
7FF8h W R 10 CENTURY CENTURY CONTROL 00-39
7FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 WATCHDOG
7FF6h AE Y ABE Y Y Y Y Y INTERRUPTS
7FF5h AM4 Y 10 DATE DATE ALARM DATE 01-31
7FF4h AM3 Y 10 HOURS HOURS ALARM HOURS 00-23
7FF3h AM2 10 MINUTES MINUT ES ALARM MINUTES 00-59
7FF2h AM1 10 SECONDS SECONDS ALARM SECONDS 00-59
7FF1h Y Y Y Y Y Y Y Y UNUSED
7FF0h WF AF 0 BLF 0 0 0 0 FLAGS

B

7

OSC

B

6

B

5

10 SECONDS SECONDS SECONDS 00-59

DATA

B

4

B

3

B

B

2

B

1

0

FUNCTION/RANGE

DS1554

X = Unused, read/writable under Write and Read AE = Alarm Flag Enable

bit control Y = Unused, read/writable without Write and Read

FT = Frequency Test bit bit control

OSC = Oscillator start/stop bit

ABE = Alarm in battery Back-up mode enable

W = Write bit AM1-AM4 = Alarm Mask bits
R = Read bit WF = Watchdog Flag
WDS = Watchdog Steering bit AF = Alarm Flag
BMB0-BMB4 = Watchdog Multiplier bits 0 = 0 and are read only
RB0-RB1 = Watchdog Resolution bits BLF = Battery Low Flag

CLOCK OSCILLATOR CONTROL

The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The

OSC bit is the

MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1554 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC

bit set to a 1.

READING THE CLOCK

When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).
As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is
set to a 0.

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DS1554

SETTING THE CLOCK

The 8th bit, B7 of the Control Register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the DS1554 (7FF8h-7FFFh) registers. After setting the write bit to a 1, RTC Registers can be
loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a
0 then transfers the values written to the internal RTC Registers and allows normal operation to resume.

CLOCK ACCURACY (DIP MODULE)

The DS1554 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements. The DS1554 does
not require additional calibration and, in most applications, temperature deviations will have a ne gligible
effect on accuracy. For this reason, methods of field clock calibration are not available and not necessary.
Attempts to calibrate the RTC that may be used with similar device types (M48T5x family) will not have
any effect even though the DS1554 appears to accept calibration data.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1554 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.

FREQUENCY TEST MODE

The DS1554 frequency test mode uses the open drain IRQ /FT output. With the oscillator running, the

IRQ /FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and

the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 7FF7h = 00h). The

IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the

32.768 kHz RTC oscillator. The IRQ/FT pin is an open drain output which requires a pullup resistor for
proper operation. The FT bit is cleared to a 0 on power-up.

USING THE CLOCK ALARM

The alarm settings and control for the DS1554 reside within Registers 7FF2h-7FF5h. Register 7FF6h
contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and

ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm
condition.

The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1554 is in the battery backed state of
operation to serve as a system wake-up. Alarm mask bits AM1-AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once per second mode to
notify the user of an incorrect alarm setting.

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