Dallas Semiconductor DS1386P32-120, DS1386P08-120, DS138632-120, DS138608-120 Datasheet

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DS1386/DS1386P

RAMified Watchdog Timekeepe

FEATURES

§ 8 or 32 kbytes of user NV RAM

§ Integrated NV SRAM, real time clock,

crystal, power-fail control circuit and lithium
energy source

§ Totally nonvolatile with over 10 years of

operation in the absence of power

§ Watchdog timer restarts an out-of-control

processor

§ Alarm function schedules real-time related

activities such as system wakeup

§ Programmable interrupts and square wave

output

§ All registers are individually addressable via

the address and data bus

§ Interrupt signals are active in power-down

mode

INT

PIN ASSIGNMENT

NC

A7
A6
A5
A4
A3
A2
A1

A0

1

2
3
4

5
6

7
8

9
10

11
12

13

14

15

16

INTB

A12

DQ0

DQ1
DQ2

GND

DS1386 8k x 8

32-Pin Encapsulated Package

32
31

30
29

28
27

26
25

24
23

22
21

20

19

18

17

V
SQW
V
WE
NC

9
11

OE

10

CE

DQ7

DQ6

DQ5

DQ4

DQ3

INTA

INTB

A14
A12

A7
A6
A5
A4
A3
A2
A1

A0

DQ0

DQ1
DQ2

GND

1

2
3
4

5
6

7
8

9
10

11
12

13

14

15

16

32
31

30
29

28
27

26
25

24
23

22
21

20

19

18

17

DS1386 32k x 8

32-Pin Encapsulated Package

V

CC

SQW

V

CC

WE

11

OE

10

CE

DQ7

DQ6

DQ5

DQ4

DQ3

INTB

INTB

NC
NC

PFO

V

CC

WE

OE
CE

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

X2

34
33
32
31
30
29
28

27
26
25
24
23
22
21
20
19
18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

X1 GND V
16
17

BAT

DS1386 8k x 8

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

INTA
SQW
NC
NC

12
11

10

8

6
5

3

1
0

INTB

INTB

NC
NC

PFO

V

CC

WE

OE
CE

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

X1 GND V
16
17

BAT

X2

34
33
32
31
30
29
28

27
26
25
24
23
22
21
20
19
18

DS1386 32k x 8

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

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INTA
SQW

14
13
12

11
10

8

6
5

3

1
0

ORDERING INFORMATION

DS1386 XX-120 32-pin DIP Module

08 8k x 8 NV SRAM

32 32k x 8 NV SRAM

*DS1386P XX-120 34-pin PowerCap® Module Board

08 8k x 8 NV SRAM

32 32k x 8 NV SRAM

*DS9034PCX PowerCap required

(must be ordered separately)

PIN DESCRIPTION

INTA - Interrupt Output A (open drain)
INTB (INTB) - Interrupt Output B (open drain)

A0-A14 - Address Inputs
DQ0-DQ7 - Data Input/Output

CE - Chip Enable
OE - Output Enable
WE - Write Enable

VCC - +5V
GND - Ground
SQW - Square Wave Output
NC - No Connection
X1, X2 - Crystal Connection
V

- Battery Connection

BAT

DS1386/DS1386P

DESCRIPTION

The DS1386 is a nonvolatile static RAM with a full-function Real Time Clock (RTC), alarm, watchdog
timer, and interval timer which are all accessible in a byte-wide format. The DS1386 contains a lithium
energy source and a quartz crystal, which eliminates the need for any external circuitry. Data contained
within 8k or 32k by 8-bit memory and the timekeeping registers can be read or written in the same
manner as bytewide static RAM. The timekeeping registers are located in the first 14 bytes of memory
space. Data is maintained in the RAMified Timekeeper by intelligent control circuitry, which detects the
status of VCC and write protects memory when VCC is out of tolerance. The lithium energy source can
maintain data and real time for over ten years in the absence of VCC. Timekeeper information includes
hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the
month is automatically adjusted for months with less than 31 days, including correction for leap year.
The RAMified Timekeeper operates in either 24-hour or 12-hour format with an AM/PM indicator. The
watchdog timer provides alarm interrupts and interval timing between 0.01seconds and 99.99 seconds.
The real time alarm provides for preset times of up to one week. Interrupts for both watchdog and RTC
will operate when system is powered down. Either can provide system “wake-up” signals.

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DS1386/1386P

PACKAGES

The DS1386 is available in two packages (32-pin DIP module and 34-pin PowerCap module). The 32-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1386P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.

OPERATION - READ REGISTERS

The DS1386 executes a read cycle whenever WE (Write Enable) is inactive (High), CE (Chip Enable)

and OE (Output Enable) are active (Low). The unique address specified by the address inputs (A0-A14)
defines which of the registers is to be accessed. Valid data will be available to the eight data output

drivers within t

(Access Time) after the last address-input signal is stable, providing that CE and OE

ACC

access times are also satisfied. If OE and CE access times are not satisfied, then data access must be

measured from the latter occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or

tOE for OE rather than address access.

OPERATION - WRITE REGISTERS

The DS1386 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in

the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE

or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state
for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data
bus with sufficient Data Set-Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of

CE or WE . The OE control signal should be kept inactive (High) during write cycles to avoid bus

contention. However, if the output bus has been enabled ( CE and OE active), then WE will disable the
outputs in t

from its falling edge.

ODW

DATA RETENTION

The RAMified Timekeeper provides full functional capability when VCC is greater than 4.5 volts and
write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of VCC without
any additional support circuitry. The DS1386 constantly monitors V
the RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become

“don’t care.” The two interrupts INTA and INTB (INTB) and the internal clock and timers continue to run
regardless of the level of V

. However, it is important to insure that the pull-up resistors used with the

CC

interrupt pins are never pulled up to a value that is greater than VCC + 0.3V. As VCC falls below
approximately 3.0 volts, a power switching circuit turns the internal lithium energy source on to maintain
the clock and timer data and functionality. It is also required to insure that during this time (battery

backup mode), the voltage present at INTA and INTB (INTB) never exceeds 3.0V. During power-up,
when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC and
disconnects the internal lithium energy source. Normal operation can resume after V
for a period of 200 ms.

. Should the supply voltage decay,

CC

exceeds 4.5 volts

CC

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DS1386/1386P

RAMIFIED TIMEKEEPER REGISTERS

The RAMified Timekeeper has 14 registers, which are 8 bits wide that contain all of the timekeeping,
alarm, and watchdog and control information. The clock, calendar, alarm, and watchdog registers are
memory locations, which contain external (user-accessible) copies of the timekeeping data. The external
copies are independent of internal functions except that they are updated periodically by the simultaneous
transfer of the incremented internal copy (see Figure 1). The Command Register bits are affected by both
internal and external functions. This register will be discussed later. The 8 or 32 kbytes of RAM and the
14 external timekeeping registers are accessed from the external address and data bus. Registers 0, 1, 2,
4, 6, 8, 9, and A contain time of day and date information (see Figure 2). Time of day information is
stored in BCD. Registers 3, 5, and 7 contain the Time of Day Alarm information. Time of Day Alarm
information is stored in BCD. Register B is the Command Register and information in this register is
binary. Registers C and D are the Watchdog Alarm Registers and information, which is stored in these
two registers, is in BCD. Registers E through 1FFF or 7FFF are user bytes and can be used to maintain
data at the user’s discretion.

CLOCK ACCURACY (DIP MODULE)

The DS1386 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1386P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.

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BLOCK DIAGRAM Figure 1

DS1386/1386P

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DS1386/1386P

TIME OF DAY REGISTERS

Registers 0, 1, 2, 4, 6, 8, 9, and A contain time of day data in BCD. Ten bits within these eight registers
are not used and will always read 0 regardless of how they are written. Bits 6 and 7 in the Months

Register (9) are binary bits. When set to logic 0, EOSC (Bit 7) enables the Real Time Clock oscillator.
This bit is set to logic 1 as shipped from Dallas Semiconductor to prevent lithium energy consumption
during storage and shipment (DIP Module only). This bit will normally be turned on by the user during
device initialization. However, the oscillator can be turned on and off as necessary by setting this bit to
the appropriate level. Bit 6 of this same byte controls the square wave output. When set to logic 0, the
square wave output pin will output a 1024 Hz square wave signal. When set to logic 1 the square wave
output pin is in a high impedance state. Bit 6 of the Hours Register is defined as the 12- or 24-hour select
bit. When set to logic 1, the 12-hour format is selected. In the 12-hour format, bit 5 is the AM/PM bit
with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). The Time of
Day Registers are updated every 0.01 seconds from the Real Time Clock, except when the TE bit (bit 7 of
Register B) is set low or the clock oscillator is not running. The preferred method of synchronizing data
access to and from the RAMified Timekeeper is to access the Command Register by doing a write cycle
to address location 0B and setting the TE bit (transfer enable bit) to a logic 0. This will freeze the
External Time of Day Registers at the present recorded time, allowing access to occur without danger of
simultaneous update. When the watch registers have been read or written, a second write cycle to location
0B, setting the TE bit to a logic 1, will put the Time of Day Registers back to being updated every
.01 second. No time is lost in the Real Time Clock because the internal copy of the Time of Day Register
buffers is continually incremented while the external memory registers are frozen. An alternate method of
reading and writing the Time of Day Registers is to ignore synchronization. However, any single read
may give erroneous data as the Real Time Clock may be in the process of updating the external memory
registers as data is being read. The internal copies of seconds through years are incremented, and the
time of day alarm is checked during the period that hundreds of seconds reads 99 and are transferred to
the external register when hundredths of seconds roll from 99 to 00. A way of making sure data is valid is
to do multiple reads and compare. Writing the registers can also produce erroneous results for the same
reasons. A way of making sure that the write cycle has caused proper update is to do read verifies and re­execute the write cycle if data is not correct. While the possibility of erroneous results from reads and
write cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a
minimum due to the redundant structure of the RAMified Timekeeper.

TIME OF DAY ALARM REGISTERS

Registers 3, 5, and 7 contain the Time of Day Alarm Registers. Bits 3, 4, 5, and 6 of Register 7 will
always read 0 regardless of how they are written. Bit 7 of Registers 3, 5, and 7 are mask bits (Figure 3).
When all of the mask bits are logic 0, a Time of Day Alarm will only occur when Registers 2, 4, and 6
match the values stored in Registers 3, 5, and 7. An alarm will be generated every day when bit 7 of
Register 7 is set to a logic 1. Similarly, an alarm is generated every hour when bit 7 of Registers 7 and 5
is set to a logic 1. When bit 7 of Registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute
when Register 1 (seconds) rolls from 59 to 00.

Time of Day Alarm Registers are written and read in the same format as the Time of Day Registers. The
Time of Day Alarm Flag and Interrupt are always cleared when Alarm Registers are read or written.

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