Dallas Semiconductor DS1350YP-70-IND, DS1350YP-70, DS1350YP-100, DS1350ABP-70-IND, DS1350ABP-70 Datasheet

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FEATURES

 10 years minimum data retention in the

absence of external power



Data is automatically protected during power loss

 Power supply monitor resets processor when

VCC power loss occurs and holds processor in
reset during VCC ramp-up

 Battery monitor checks remaining capacity

daily

 Read and write access times as fast as 70 ns
 Unlimited write cycle endurance
 Typical standby current 50 µA
 Upgrade for 512k x 8 SRAM, EEPROM or

Flash

 Lithium battery is electrically disconnected to

retain freshness until power is applied for the
first time

 Full ±10% VCC operating range (DS1350Y)

or optional ±5% VCC operating range
(DS1350AB)

 Optional industrial temperature range of

-40°C to +85°C, designated IND

 New PowerCap Module (PCM) package

- Directly surface-mountable module

- Replaceable snap-on PowerCap provides

lithium backup battery

- Standardized pinout for all nonvolatile

SRAM products

- Detachment feature on PowerCap allows

easy removal using a regular screwdriver

PIN ASSIGNMENT

PIN DESCRIPTION

A0 - A18 - Address Inputs
DQ0 - DQ7 - Data In/Data Out

CE - Chip Enable
WE - Write Enable
OE - Output Enable
RST - Reset Output
BW - Battery Warning

V

CC

- Power (+5V)
GND - Ground
NC - No Connect

DESCRIPTION

The DS1350 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as
524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors V

CC

for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. Additionally, the DS1350 devices have dedicated circuitry for monitoring the
status of VCC and the status of the internal lithium battery. DS1350 devices in the PowerCap Module
package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a
complete Nonvolatile SRAM module. The devices can be used in place of 512k x 8 SRAM, EEPROM or
Flash components.

DS1350Y/AB

4096k Nonvolatile SRAM

with Battery Monito

r

www.dalsemi.com

1

BW

2
3

A15
A16

RST

V

CC

WE

OE

CE
DQ7
DQ6
DQ5
DQ4
DQ3

DQ2
DQ1
DQ0

GND

4
5
6
7
8
9
10
11
12
13
14
15
16
17

A17A

14

33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

A

13

A

12

A11A10A9A8A7A

6

A

5

A4A

3

A

2

A1A

0

34

A

18

GND

V

BAT

34-Pin POWERCAP MODULE (PCM)

(USES DS9034PC POWERCAP)

DS1350Y/AB

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READ MODE

The DS1350 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified b y the 19 address inputs

(A0 -A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t

ACC

(Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.

WRITE MODE

The DS1350 devices execute a write c ycle whenever the WE and CE signals ar e in the active (low) state
after address inputs are stable. The later-occurrin g falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t

ODW

from its falling edge.

DATA RETENTION MODE

The DS1350AB provides full functional capability for VCC greater than 4.75 volts and write protects by

4.5 volts. The DS1350Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high­impedance. As VCC falls below approximately 2.7 volts, the power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.7 volts,
the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1350AB and 4.5 volts for the
DS1350Y.

SYSTEM POWER MONITORING

DS1350 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power

failure by asserting RST . On power-up, RST is held active for 200 ms nominal to prevent system
operation during power-on transients and to allow t

REC

to elapse. RST has an open drain output driver.

BATTERY MONITORING

The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within t

REC

after VCC rises above VTP and is suspended when power

failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ=test resistor for one

second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output

BW is asserted. Once asserted, BW remains active until the module is replaced.

The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open drain output driver.

DS1350Y/AB

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FRESHNESS SEAL

Each DS1350 is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.

PACKAGES

The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC PowerCap. The PowerCap Module pack age design
allows a DS1350 PCM device to be surface mounted without subjecting its lithium backup battery to
destructive high-temperature reflow soldering. After a DS1350 PCM is reflow soldered, a DS9034PC is
snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to
prevent improper attachment. DS1350 PowerCap Modules and DS9034PC PowerCaps are ordered
separately and shipped in separate containers. See the DS9034PC data sheet for further information.

DS1350Y/AB

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

DS1350AB Power Supply Voltage V

CC

4.75 5.0 5.25 V

DS1350Y Power Supply Voltage V

CC

4.5 5.0 5.5 V

Logic 1 V

IH

2.2 V

CC

V

Logic 0 V

IL

0.0 0.8 V

DC ELECTRICAL (VCC=5V ±=5% for DS1350AB)
CHARACTERISTICS (t

A

: See Note 10) (VCC=5V ±=10% for DS1350Y)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current I

IL

-1.0 +1.0

µA

I/O Leakage Current CE ≥ VIH ≤ V

CC

I

IO

-1.0 +1.0

µA

Output Current @ 2.4V I

OH

-1.0 mA 14

Output Current @ 0.4V I

OL

2.0 mA 14

Standby Current CE =2.2V

I

CCS1

200 600

µA

Standby Current CE =VCC-0.5V

I

CCS2

50 150

µA

Operating Current I

CCO1

85 mA

Write Protection Voltage (DS1350AB) V

TP

4.50 4.62 4.75 V

Write Protection Voltage (DS1350Y) V

TP

4.25 4.37 4.5 V

CAPACITANCE (tA=25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C

IN

510pF

Input/Output Capacitance C

I/O

510pF

DS1350Y/AB

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AC ELECTRICAL (VCC=5V ±=5% for DS1350AB)
CHARACTERISTICS (t

A

: See Note 10) (VCC=5V ±=10% for DS1350Y)

DS1350AB-70

DS1350Y-70

DS1350AB-100

DS1330Y-100

PARAMETER SYMBOL

MIN MAX MIN MAX

UNITS NOTES

Read Cycle Time t

RC

70 100 ns

Access Time t

ACC

70 100 ns

OE to Output Valid

t

OE

35 50 ns

CE to Output Valid

t

CO

70 100 ns

OE or CE to Output Active

t

COE

5 5 ns 5

Output High Z from Deselection t

OD

25 35 ns 5

Output Hold from Address
Change

t

OH

55 ns

Write Cycle Time t

WC

70 100 ns

Write Pulse Width t

WP

55 75 ns 3

Address Setup Time t

AW

00 ns

Write Recovery Time

t

WR1

t

WR2

5

12

5

12

ns

12
13

Output High Z from WE

t

ODW

25 35 ns 5

Output Active from WE

t

OEW

5 5 ns 5

Data Setup Time t

DS

30 40 ns 4

Data Hold Time

t

DH1

t

DH2

0
7

0
7

ns

12
13

READ CYCLE

SEE NOTE 1

DS1350Y/AB

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WRITE CYCLE 1

SEE NOTES 2, 3, 4, 6, 7, 8, and 12

WRITE CYCLE 2

SEE NOTES 2, 3, 4, 6, 7, 8, and 13

DS1350Y/AB

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POWER-DOWN/POWER-UP CONDITION

BATTERY WARNING DETECTION

SEE NOTE 14

DS1350Y/AB

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POWER-DOWN/POWER-UP TIMING (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VCC Fail Detect to CE and WE Inactive

t

PD

1.5

µs

11

VCC slew from VTP to 0V t

F

150

µs

VCC Fail Detect to RST Active

t

RPD

15

µs

14

VCC slew from 0V to V

TP

t

R

150

µs

VCC Valid to CE and WE Inactive

t

PU

2ms

VCC Valid to End of Write Protection t

REC

125 ms

VCC Valid to RST Inactive

t

RPU

150 200 350 ms 14

VCC Valid to BW Valid

t

BPU

1s14

BATTERY WARNING TIMING (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Battery Test Cycle t

BTC

24 hr

Battery Test Pulse Width t

BTPW

1s

Battery Test to BW Active

t

BW

1s

(tA=25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Expected Data Retention Time t

DR

10 years 9

WARNING:

Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.

NOTES:

1. WE is high for a Read Cycle.

2.

OE = V

IH

or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.

3. t

WP

is specified as the logical A ND of CE and WE . tWP is measured from the latter of CE or WE

going low to the earlier of CE or WE going high.

4. t

DS

are measured from the earlier of CE or WE going high.

5. These parameters are sampled with a 5 pF load and are not 100% tested.

6. If the

CE low transition occurs simultaneously with or latter than the WE low transition, the output

buffers remain in a high-impedance state during this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

buffers remain in high-impedance state during this period.

8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,

the output buffers remain in a high-impedance state during this period.

DS1350Y/AB

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9. Each DS1230Y has a built-in switch that disconnects the lithium source until VCC is first applied by

the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.

10. All AC and DC electrical characteristics are valid over the full operating temperature range. For

commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.

11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.

12. t

WR1

and t

DH1

are measured from WE going high.

13. t

WR2

and t

DH2

are measured from CE going high.

14. RST and BW are open drain outputs and cannot source current. External pullup resistors should be

connected to these pins for proper operation. Both pins will sink 10 mA.

DC TEST CONDITIONS AC TEST CONDITIONS

Outputs Open Output Load: 100 pF + 1TTL Gate
Cycle = 200 ns for operating current Input Pulse Levels: 0 - 3.0V
All voltages are referenced to ground Timing Measurement Reference Levels

Input: 1.5V
Output: 1.5V

Input pulse Rise and Fall Times: 5 ns

ORDERING INFORMATION

DS1350 TTP - SSS - III

Operating Temperature Range
blank: 0° to 70°
IND: -40° to +85°C

Access Speed
70: 70 ns
100: 100 ns

Package Type
P: 34-pin PowerCap Module

VCC Tolerance
AB: ±5%
Y: ±10%

DS1350Y/AB

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DS1350Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE

INCHES

PKG

DIM

MIN NOM MAX

A

0.920 0.925 0.930

B

0.980 0.985 0.990

C

- - 0.080

D

0.052 0.055 0.058

E

0.048 0.050 0.052

F

0.015 0.020 0.025

G

0.020 0.025 0.030

DS1350Y/AB

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DS1350Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP

INCHES

PKG

DIM

MIN NOM MAX

A

0.920 0.925 0.930

B

0.955 0.960 0.965

C

0.240 0.245 0.250

D

0.052 0.055 0.058

E

0.048 0.050 0.052

F

0.015 0.020 0.025

G

0.020 0.025 0.030

ASSEMBLY AND USE

Reflow soldering
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented label-side up (live-bug).

Hand soldering and touch-up
Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the
lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a
solder wick.

LPM replacement in a socket
To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module
base then insert the complete module into the socket one row of leads at a time, pushing only on the
corners of the cap. Never appl y force to the center of the device. To remove from a socket, use a PLCC
extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use
any other tool for extraction.

DS1350Y/AB

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RECOMMENDED POWERCAP MODULE LAND PATTERN

INCHES

PKG

DIM

MIN NOM MAX

A

- 1.050 -

B

- 0.826 -

C

- 0.050 -

D

- 0.030 -

E

- 0.112 -

RECOMMENDED POWERCAP MODULE SOLDER STENCIL

INCHES

PKG

DIM

MIN NOM MAX

A

- 1.050 -

B

- 0.890 -

C

- 0.050 -

D

- 0.030 -

E

- 0.080 -