dallas semiconductor DS1330Y, DS1330AB service manual
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DS1330Y/AB
256k Nonvolatile SRAM
with Battery Monito
FEATURES
§ 10 years minimum data retention in the
absence of external power
§ Data is automatically protected during power loss
§ Power supply monitor resets processor when
VCC power loss occurs and holds processor in
reset during VCC ramp-up
§ Battery monitor checks remaining capacity
daily
§ Read and write access times as fast as 70ns
§ Unlimited write cycle endurance
§ Typical standby current 50mA
§ Upgrade for 32k x 8 SRAM, EEPROM or
Flash
§ Lithium battery is electrically disconnected to
retain freshness until power is applied for the
first time
§ Full ±10% VCC operating range (DS1330Y)
or optional ±5% VCC operating range
(DS1330AB)
§ Optional industrial temperature range of
-40°C to +85°C, designated IND
§ PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
Standardized pinout for all nonvolatile (NV)
SRAM products
- Detachment feature on PowerCap allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
BW
NC
NC
RST
V
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
CC
5
6
7
8
9
10
11
12
13
14
15
16
17
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
GND
V
BAT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
PIN DESCRIPTION
A0 – A14 - Address Inputs
DQ0 – DQ7 - Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable
RST - Reset Output
BW - Battery Warning
V
- Power (+5V)
CC
GND - Ground
NC - No Connect
NC
NC
14
12
10
9
8
5
3
1
0
DESCRIPTION
The DS1330 256k NV SRAMs are 262,144-bit, fully static, NV SRAMs organized as 32,768 words by 8
bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly
monitors V
is automatically switched on and write protection is unconditionally enabled to prevent data corruption.
Additionally, the DS1330 devices have dedicated circuitry for monitoring the status of VCC and the status
of the internal lithium battery. DS1330 devices in the PowerCap module package are directly surface
mountable and are normally paired with a DS9034PC PowerCap to form a complete NV SRAM module.
The devices can be used in place of 32k x 8 SRAM, EEPROM, or Flash components.
for an out-of-tolerance condition. When such a condition occurs, the lithium energy source
CC
1 of 11 110201
DS1330Y/AB
READ MODE
The DS1330 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A0 – A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
(Access Time) after the last address input signal is stable, providing
ACC
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1330 devices execute a write cycle whenever the WE and CE signals are in the active (low) state
after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE
active) then WE will disable the outputs in t
from its falling edge.
ODW
DATA RETENTION MODE
The DS1330AB provides full-functional capability for VCC greater than 4.75V and write protects by
4.5V. The DS1330Y provides full-functional capability for VCC greater than 4.5V and write protects by
4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The NV
SRAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 2.7V, the power switching circuit
connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation
can resume after VCC exceeds 4.75V for the DS1330AB and 4.5V for the DS1330Y.
SYSTEM POWER MONITORING
DS1330 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting RST . On power-up, RST is held active for 200ms nominal to prevent system
operation during power-on transients and to allow t
to elapse. RST has an open drain output driver.
REC
BATTERY MONITORING
The DS1330 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within t
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MW test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open drain output driver.
after VCC rises above VTP and is suspended when power
REC
2 of 11
DS1330Y/AB
PACKAGES
The 34-pin PowerCap module integrates SRAM memory and NV control along with contacts for
connection to the lithium battery in the DS9034PC PowerCap. The PowerCap module package design
allows a DS1330 PCM device to be surface mounted without subjecting its lithium backup battery to
destructive high-temperature reflow soldering. After a DS1330 PCM is reflow soldered, a DS9034PC is
snapped on top of the PCM to form a complete NV SRAM module. The DS9034PC is keyed to prevent
improper attachment. DS1330 PowerCap modules and DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature Range 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature Range -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1330AB Power Supply Voltage V
DS1330Y Power Supply Voltage V
Logic 1 V
Logic 0 V
CC
CC
IH
IL
DC ELECTRICAL (V
CHARACTERISTICS (t
: See Note 10) (V
A
4.75 5.0 5.25 V
4.5 5.0 5.5 V
2.2 V
CC
V
0.0 0.8 V
= 5V ± 5% for DS1330AB)
CC
= 5V ± 10% for DS1330Y)
CC
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
I/O Leakage Current CE ³ VIH £ V
CC
Output Current @ 2.2V I
Output Current @ 0.4V I
Standby Current CE =2.2V
Standby Current CE =VCC-0.5V
I
I
Operating Current I
Write Protection Voltage (DS1330AB) V
Write Protection Voltage (DS1330Y) V
IL
I
IO
OH
OL
CCS1
CCS2
CCO1
TP
TP
-1.0 +1.0
-1.0 +1.0
mA
mA
-1.0 mA 14
2.0 mA 14
200 600
50 150
mA
mA
85 mA
4.50 4.62 4.75 V
4.25 4.37 4.5 V
3 of 11
DS1330Y/AB
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Input/Output Capacitance C
IN
I/O
AC ELECTRICAL (V
CHARACTERISTICS (t
PARAMETER SYMBOL
Read Cycle Time t
Access Time t
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High Z from Deselection t
Output Hold from Address
Change
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time
Output High Z from WE
t
: See Note 10) (V
A
DS1330AB-70
DS1330Y-70
MIN MAX MIN MAX
RC
ACC
t
OE
t
CO
t
COE
OD
t
OH
WC
WP
AW
t
WR1
t
WR2
ODW
70 100 ns
5 5 ns 5
55 ns
70 100 ns
55 75 ns 3
00 ns
5
12
70 100 ns
45 50 ns
70 100 ns
25 35 ns 5
25 35 ns 5
510pF
510pF
= 5V ± 5% for DS1330AB)
CC
= 5V ± 10% for DS1330Y)
CC
DS1330AB-100
DS1330Y-100
UNITS NOTES
5
ns
12
12
13
Output Active from WE
Data Setup Time t
Data Hold Time
READ CYCLE
SEE NOTE 1
t
OEW
t
DH1
t
DH2
DS
5 5 ns 5
30 40 ns 4
0
7
4 of 11
0
7
ns
12
13
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