Dallas Semiconductor DS1321S, DS1321E, DS1321 Datasheet
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FEATURES
Converts CMOS SRAM into nonvolatile
memory
Unconditionally write-protects SRAM when
VCC is out of tolerance
Automatically switches to battery backup
supply when VCC power failure occurs
Flexible memory organization
- Mode 0: 4 banks with 1 SRAM each
- Mode 1: 2 banks with 2 SRAMs each
- Mode 2: 1 bank with 4 SRAMs each
Monitors voltage of a lithium cell and
provides advanced warning of impending
battery failure
Signals low-battery condition on active low
Battery Warning output signal
Resets processor when power failure occurs
and holds processor in reset during system
power-up
Optional -5% or -10% power-fail detection
16-pin DIP, 16-pin SOIC and 20-pin TSSOP
packages
Industrial temperature range of -40°C to
+85°C
PIN DESCRIPTION
V
CCI
- +5V Power Supply Input
V
CCO
- SRAM Power Supply Output
V
BAT
- Backup Battery Input
A, B - Address Inputs
CEI1 - CEI4 - Chip Enable Inputs
CEO1 - CEO4 - Chip Enable Outputs
TOL - V
CC
Tolerance Select
BW - Battery Warning Output (Open
Drain)
RST - Reset Output (Open Drain)
MODE - Mode Input
GND - Ground
NC - No Connection
PIN ASSIGNMENT
DS1321
Flexible Nonvolatile Controller with
Lithium Battery Monitor
www.dalsemi.com
1
2
3
4
20
19
18
17
5
6
7
8
9
10 11
12
13
14
15
16
NC
DS1321E 20-Pin TSSOP
V
CCI
RST
BW
CEO1
CEO2
NC
CEO3
CEO4
NC
MODE
V
CCO
V
BAT
TOL
CEI1
CEI2
NC
A
/CEI3
B/CEI4
GND
1
2
3
4
16
15
14
13
5
6
7
89
10
11
12
V
CCI
RST
BW
CEO1
CEO2
CEO3
CEO4
MODE
V
CCO
V
BAT
TOL
CEI1
CEI2
A
/CEI3
B/CEI4
GND
DS1321 16-Pin DIP
(300-mil)
1
2
3
4
16
15
14
13
5
6
7
89
10
11
12
V
CCI
RST
BW
CEO1
CEO2
CEO3
CEO4
MODE
V
CCO
V
BAT
TOL
CEI1
CEI2
A
/CEI3
B/CEI4
GND
DS1321S 16-Pin SOIC
(150-mil)
DS1321
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DESCRIPTION
The DS1321 Flexible Nonvolatile Controller with Lithium Battery Monitor is a CMOS circuit which
solves the application problem of converting CMOS SRAMs into nonvolatile memory. Incoming power
is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable outputs are
inhibited to accomplish write protection and the battery is switched on to supply the SRAMs with
uninterrupted power. Special circuitry uses a low-leakage CMOS process which affords precise voltage
detection at extremely low battery consumption. One DS1321 can support as many as four SRAMs
arranged in any of three memory configurations.
In addition to battery-backup support, the DS1321 performs the important function of monitoring the
remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life.
Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority
of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1321
performs such measurement by periodically comparing the voltage of the battery as it supports an internal
resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference
voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning
pin is activated to signal the need for battery replacement.
MEMORY BACKUP
The DS1321 performs all the circuit functions required to provide battery-backup for as many as four
SRAMs. First, the device provides a switch to direct power from the battery or the system power supply
(V
CCI
). Whenever V
CCI
is less than the V
CCTP
trip point and V
CCI
is less than the battery voltage V
BAT
, the
battery is switched in to provide backup power to the SRAM. This switch has voltage drop of less than
0.2 volts.
Second, the DS1321 handles power failure detection and SRAM write-protection. V
CCI
is constantly
monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and
inhibits the four chip enable outputs in order to write-protect the SRAMs. This is accomplished by
holding CEO1 through CEO4 to within 0.2 volts of V
CCO
when V
CCI
is out of tolerance. If any CEI is
active (low) at the time that power failure is detected, the corresponding CEO signal is kept low until the
CEI signal is brought high again. Once the CEI signal is brought high, the CEO signal is taken high and
held high until after V
CCI
has returned to its nominal voltage level. If the CEI signal is not brought high
by 1.5 µs after power failure is detected, the corresponding CEO is forced high at that time. This specific
scheme for delaying write protection for up to 1.5 µs guarantees that any memory access in progress
when power failure occurs will complete properly. Power failure detection occurs in the range of 4.75 to
4.5 volts (5% tolerance) when the TOL pin is wired to GND or in the range of 4.5 to 4.25 volts (10%
tolerance) when TOL is connected to V
CCO
.
DS1321
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MEMORY CONFIGURATIONS
The DS1321 can be configured via the MODE pin for three different arrangements of the four attached
SRAMs. The state of the MODE pin is latched at V
CCI
= V
CCTP
on power up. See Figure 1 for details.
MEMORY CONFIGURATIONS Figure 1
MODE = GND (4 BANKS WITH 1 SRAM EACH):
MODE = V
CCO
(2 BANKS WITH 2 SRAM EACH):
MODE FLOATING (1 BANK WITH 4 SRAMs):
DS1321
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BATTERY VOLTAGE MONITORING
The DS1321 automatically performs periodic battery voltage monitoring at a factory-programmed time
interval of 24 hours. Such monitoring begins within t
REC
after V
CCI
rises above V
CCTP
and is suspended
when power failure occurs.
After each 24-hour period (t
BTCN
) has elapsed, the DS1321 connects V
BAT
to an internal 1 MΩ=test
resistor (R
INT
) for one second (t
BTPW
). During this one second, if V
BAT
falls below the factory-
programmed battery voltage trip point (V
BTP
), the battery warning output BW is asserted. While BW is
active, battery testing will be performed with period t
BTCW
to detect battery removal and replacement.
Once asserted, BW remains active until the battery is physically removed and replaced by a fresh cell.
The battery is still retested after each VCC power-up, however, even if BW was active on power-down. If
the battery is found to be higher than V
BTP
during such testing, BW is deasserted and regular 24-hour
testing resumes. BW has an open-drain output driver.
Battery replacement following BW activation is normally done with V
CCI
nominal so that SRAM data is
not lost. During battery replacement, the minimum time duration between old battery detachment and
new battery attachment (t
BDBA
) must be met or BW will not deactivate following attachment of the new
battery. Should BW not deactivate for this reason, the new battery can be detached for t
BDBA
and then re-
attached to clear BW .
NOTE: The DS1321 cannot constantly monitor an attached battery because such monitoring would
drastically reduce the life of the battery. As a result, the DS1321 only tests the battery for one second out
of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that
has not been previously flagged with BW ) is removed between battery tests, the DS1321 may not
immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery
is then reattached to the DS1321, the battery may not be tested until the next scheduled test.
NOTE: Battery monitoring is only a useful technique when testing can be done regularly over the entire
life of a lithium battery. Because the DS1321 only performs battery monitoring when V
CC
is nominal,
systems which are powered-down for excessively long periods can completely drain their lithium cells
without receiving any advanced warning. To prevent such an occurrence, systems using the DS1321
battery monitoring feature should be powered-up periodically (at least once every few months) in order to
perform battery testing. Furthermore, anytime
BW is activated on the first battery test after a power-up,
data integrity should be checked via checksum or other technique.
POWER MONITORING
The DS1321 automatically detects out-of-tolerance power supply conditions and warns a processor-based
system of impending power failure. When V
CCI
falls below the trip point level defined by the TOL pin
(V
CCTP
), the V
CCI
comparator activates the reset signal RST . Reset occurs in the range of 4.75 to 4.5 volts
(5% tolerance) when the TOL pin is connected to GND or in the range of 4.5 to 4.25 volts (10%
tolerance) when TOL is connected to V
CCO
.
RST also serves as a power-on reset during power-up. After V
CCI
exceeds V
CCTP
, RST will be held active
for 200 ms nominal (t
RPU
). This reset period is sufficiently long to prevent system operation during
power-on transients and to allow t
REC
to expire. RST has an open-drain output driver.
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