Dallas Semiconductor DS1306N, DS1306EN, DS1306E, DS1306 Datasheet

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DS1306

Serial Alarm Real Time Clock (RTC)

FEATURES

 Real time clock counts seconds, minutes,

hours, date of the month, month, day of the
week, and year with leap year compensation
valid up to 2100

 96-byte nonvolatile RAM for data storage
 Two Time of Day Alarms - programmable on

combination of seconds, minutes, hours, and
day of the week

 1 Hz and 32.768 kHz clock outputs
 Serial interface supports Motorola Serial

Peripheral Interface (SPI) serial data ports or
standard 3-wire interface

 Burst Mode for reading/writing successive

addresses in clock/RAM

 Dual power supply pins for primary and

backup power supplies

 Optional trickle charge output to backup

supply

 2.0 - 5.5V operation
 Optional industrial temperature range

-40°C to +85°C

 Available in space-efficient 20-pin TSSOP

package

 Recognized by Underwriters Laboratory

ORDERING INFORMATION

DS1306 16-Pin DIP
DS1306N 16-Pin DIP (Industrial)
DS1306E 20-Pin TSSOP
DS1306EN 20-Pin TSSOP (Industrial)

PIN ASSIGNMENT

V

CC2

V

BAT

X1

NC

X2

NC
INT0
INT1

1 Hz

GND

1
2
3
4
5
6
7
8
9
10

DS1306 20-Pin TSSOP (173 mil)

CC2

BAT

X1
X2

1
2

3
4

5
6

7
8

V
V

INT0
INT1

1 Hz

GND

DS1306 16-Pin DIP (300 mil)

20
19
18
17
16
15
14
13
12
11

16
15

14
13

12
11

10

9

V

CC1

NC
32 kHz
V

CCIF

SDO
SDI
SCLK
NC
CE
SERMODE

V

CC1

32 kHz
V

CCIF

SDO
SDI

SCLK
CE
SERMODE

PIN DESCRIPTION

V

– Primary Power Supply

CC1

V

– Backup Power Supply

CC2

– +3V Battery Input

V

BAT

V

– Interface Logic Power Supply

CCIF

Input
GND – Ground
X1, X2 – 32.768 kHz Crystal Connection

INT0 – Interrupt 0 Output

INT1 – Interrupt 1 Output
SDI – Serial Data In
SDO – Serial Data Out
CE – Chip Enable
SCLK – Serial Clock
SERMODE – Serial Interface Mode
1 Hz - 1 Hz Output
32 kHz - 32.768 kHz Output

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DS1306

DESCRIPTION

The DS1306 Serial Alarm Real Time Clock provides a full BCD clock calendar which is accessed via a
simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically adjusted for months with less than 31 days,
including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with
AM/PM indicator. In addition 96 bytes of nonvolatile RAM are provided for data storage.

An interface logic power supply input pin (V

) allows the DS1306 to drive SDO and 32 kHz pins to a

CCIF

level that is compatible with the interface logic. This allows an easy interface to 3-volt logic in mixed
supply systems. The DS1306 offers dual power supplies as well as a battery input pin. The dual power
supplies support a programmable trickle charge circuit which allows a rechar geable energy source (such
as a super cap or rechargeable battery) to be used for a backup supply. The V

pin allows the device to

BAT

be backed up by a non-rechargeable battery. The DS1306 is fully operational from 2.0 to 5.5 volts.

Two programmable time of day alarms are provided by the DS1306. Each alarm can generate an
interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. A 1 Hz and
a 32 kHz clock output are also available.

The DS1306 supports a direct interface to Motorola SPI serial data ports or standard 3-wir e interfac e. An
easy-to-use address and data format is implemented in which data transfers can occur 1 byte at a time or
in multiple-byte burst mode.

OPERATION

The block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The following
paragraphs describe the function of each pin.

DS1306 BLOCK DIAGRAM Figure 1

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SIGNAL DESCRIPTIONS

V

- DC power is provided to the device on this pin. V

CC1

V

- This is the secondar y power supply pin. In systems using the trickle charger, the rechargeable

CC2

energy source is connected to this pin.

V

- Battery input for any standard 3-volt lithium cell or other energy source.

BAT

is the primary power supply.

CC1

DS1306

(Interface Logic Power Supply Input) - The V

V

CCIF

pin allows the DS1306 to drive SDO and

CCIF

32 kHz output pins to a level that is compatible with the i nterface l o gic, thus all owin g an easy interface to
3-volt logic in mixed supply systems. This pin is physically connected to the sou rce connection of the p­channel transistors in the output buffers of the SDO and 32 kHz pins.

SERMODE (Serial Interface Mode Input) - The SERMODE pin offers the flexibility to choose
between two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to VCC, Motorola SPI communication is selected.

SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface for
either the SPI or 3-wire interface.

SDI (Serial Data Input) - When SP I communication is selected, the SDI pin is the serial data input for
the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).

SDO (Serial Data Output) - W hen SPI communication is selected, the SDO pin is the serial dat a output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI
and SDO pins function as a single I/O pin when tied together).

CE (Chip Enable) - The Chip Enable signal must be asserted high during a read or a write for both
3-wire and SPI communication. This pin has an internal 55k pull-down resistor (typical).

INT0 (Interrupt 0 Output) - The INT0 pin is an active low output of the DS1306 that c an be used as an

interrupt input to a processor. The

INT0 pin can be programmed to be asserted by Alarm 0. The INT0

pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt
enable bit is set. The

INT0 pin operates when the DS1306 is powered by V

CC1

, V

CC2

, or V

. The INT0

BAT

pin is an open drain output and requires an external pullup resistor.
1 Hz (1 Hz Clock Output) - The 1 Hz pin provides a 1 Hz squarewave output. This output is active

when the 1 Hz bit in the control register is a logic 1.

Both

INT0 and 1 Hz pins are open drain outputs. The interrupt, 1 Hz signal, and the internal clock

continue to run regardless of the level of VCC (as long as a power source is present).

INT1 (Interrupt 1 Output) - The INT1 pin is an active high output of the DS1306 that can be used as an
interrupt input to a processor. The INT1 pin can be programmed to be asserted by alarm 1. When an
alarm condition is present, the INT1 pin generates a 62.5 ms active high pulse. The INT1 pin operates
only when the DS1306 is powered by V
V

CC2

or V

. When inactive, the INT1 pin is internally pulled low.

BAT

CC2

or V

. When active, the INT1 pin is internally pulled up to

BAT

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DS1306

32 kHz (32.768 kHz Clock Output) - The 32 kHz pin provides a 32.768 kHz output. This signal is
always present.

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6 pF. For more information on crystal
selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations
with Dallas Real Time Clocks.” The DS1306 can also be driven by an external 32.768 kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

RTC AND RAM ADDRESS MAP

The address map for the RTC and RAM registers of the DS1306 is shown in Figure 2. Data is written to
the RTC by writing to address locations 80h to 9Fh and is written to the RAM by writing to address
locations A0h to FFh. RTC data is read by reading address locations 00h to 1Fh and RAM data is read by
reading address locations 20h to 7Fh.

ADDRESS MAP Figure 2

00H

1FH
20H

7FH
80H

9FH
A0H

FFH

CLOCK/CALENDAR

READ ADDRESSES ONLY

96-BYTES USER RAM

READ ADDRESSES ONLY

CLOCK/CALENDAR

WRITE ADDRESSES ONLY

96-BYTES USER RAM

WRITE ADDRESSES ONLY

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DS1306

CLOCK, CALENDAR, AND ALARM

The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time, calendar, and alarm are set or initialized by writing
the appropriate register bytes. Note that some bits are set to 0. These bits will always read 0 regardless
of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh ar e reserved.
These registers will always read 0 regardless of how they are written. The contents of the time, calendar,
and alarm registers are in the Binary-Coded Decimal (BCD) format.

RTC REGISTERS Figure 3
RTC REGISTERS DS1306

HEX ADDRESS

READ WRITE

00H 80H 0 10 SEC SEC 00-59
01H 81H 0 10 MIN MIN 00-59

03H 83H 0 0 0 0 0 DAY 01-07
04H 84H 0 0 10 DATE DATE 1-31
05H 85H 0 0 10 MONTH MONTH 01-12
06H 86H 10 YEAR YEAR 00-99

07H 87H M 10 SEC ALARM SEC ALARM 00-59
08H 88H M 10 MIN ALARM MIN ALARM 00-59

0AH 8AH M 0 0 0 0 DAY ALARM 01-07

0BH 8BH M 10 SEC ALARM SEC ALARM 00-59
0CH 8CH M 10 MIN ALARM MIN ALARM 00-59

0EH 8EH M 0 0 0 0 DAY ALARM 01-07

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RANGE

10 01-12 + P/A02H 82H 0 12/2

10 HR HOURS

4

P/A

Alarm 0

10 01-12 + P/A09H 89H M 12/2

10 HR HOUR ALARM

4

P/A

Alarm 1

10 01-12 + P/A0DH 8DH M 12/2

10 HR HOUR ALARM

4

P/A

00-23

00-23

00-23

0FH 8FH CONTROL REGIST ER
10H 90H STATUS REGISTER
11H 91H TRICKLE CHARGER REGISTER

12-1FH 92-9FH RESERVED

NOTE:

Range for alarm registers does not include mask’m’ bits.

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DS1306

The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).

The DS1306 contains two time of day alarms. Time of Day Alarm 0 can be set by writing to registers
87h to 8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. Bit 7 of each of the time
of day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time of day alarm
will only occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when bit 7 of the
day alarm register is set to a logic 1. An alarm will be generated every hour when bit 7 of the day and
hour alarm registers is set to a logic 1. Similarly, an alarm will be generated every minute when bit 7 of
the day, hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and
seconds alarm registers is set to a logic 1, an alarm will occur every second.

TIME OF DAY ALARM MASK BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

SECONDS MINUTES HOURS DAYS

1 1 1 1 Alarm once per second
0 1 1 1 Alarm when seconds match
0 0 1 1 Alarm when minutes and seconds match
0 0 0 1 Alarm when hours, minutes, and seconds match
0 0 0 0 Alarm when day, hours, minutes, and seconds

match

SPECIAL PURPOSE REGISTERS

The DS1306 has three additional registers (Control Register, Status Register, and Trickle Charger
Register) that control the real time clock, interrupts, and trickle charger.

CONTROL REGISTER (READ 0FH, WRITE 8FH)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0 WP 0 0 0 1 Hz AIE1 AIE0

WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the
control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should
be cleared before attempting to write to the device.

1 Hz (1 Hz output enable) - This bit controls the 1 Hz output. When this bit is a logic 1, the 1 Hz output
is enabled. When this bit is a logic 0, the 1 Hz output is high Z.

AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag
(IRQF0) bit in the status register to assert INT0. When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the

AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag
(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does
not initiate an interrupt signal, and the INT1 pin is set to a logic 0 state.

INT0 signal.

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