Dallas Semiconductor DS1305N, DS1305EN, DS1305E, DS1305 Datasheet

www.dalsemi.com

N

N

N

N

DS1305

Serial Alarm Real Time Clock (RTC)

FEATURES

 Real time clock counts seconds, minutes,

hours, date of the month, month, day of the
week and year with leap year compensation
valid up to 2100

 96-byte nonvolatile RAM for data storage
 Two time-of-day alarms programmable on

combination of seconds, minutes, hours and
day of the week

 Serial interface supports Motorola serial

peripheral interface (SPI) serial data ports or
standard 3-wire interface

 Burst mode for reading/writing successive

addresses in clock/RAM

 Dual power supply pins for primary and

backup power supplies

 Optional trickle charge output to backup

supply

 2.0 - 5.5V operation
 Optional industrial temperature range

-40°C to +85°C

 Available in space-efficient, 20-pin TSSOP

package

 Recognized by Underwriters Laboratory

ORDERING INFORMATION

DS1305 16-Pin DIP
DS1305N 16-Pin DIP (Industrial)
DS1305E 20-Pin TSSOP
DS1305EN 20-Pin TSSOP (Industrial)

PIN ASSIGNMENT

V

CC2

V

BAT

X1 3 18 PF

C4 17V

X2 5 16 SD0

C6 15SDI

INT0 7 14 SCLK

C8 13NC
INT1 9 12 CE
GND 10 11 SERMODE

DS1305 20-Pin TSSOP (173 mil)

V
V
X1 3 14 V
X2 4 13 SDO

INT0 6 11 SCLK
INT1 7 10 CE
GND 8 9 SERMODE

120V
219NC

CC2

BAT

C5 12SDI

1 16 V
215PF

CC1

CCIF

CC1

CCIF

DS1305 16-Pin DIP (300 mil)

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DS1305

PIN DESCRIPTION

V

CC1

V

- Backup Power Supply

CC2

V

- +3V Battery Input

BAT

V

- Interface Logic Power Supply Input

CCIF

GND - Ground
X1, X2 - 32.768 kHz Crystal Connection

INT0 - Interrupt 0 Output

INT1 - Interrupt 1 Output

SDI - Serial Data In
SDO - Serial Data Out
CE - Chip Enable
SCLK - Serial Clock
SERMODE - Serial Interface Mode

PF - Power Fail Output

- Primary Power Supply

DESCRIPTION

The DS1305 Serial Alarm Real Time Clock provides a full BCD clock calendar which is accessed via a
simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month and year
information. The end of the month date is automatically adjusted for months with less than 31 days,
including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with
AM/PM indicator. In addition 96 bytes of nonvolatile RAM are provided for data storage.

An interface logic power supply input pin (V

) allows the DS1305 to drive SDO and PF pins to a level

CCIF

that is compatible with the interface logic. This allows an easy interface to 3-volt logic in mixed suppl y
systems.

The DS1305 offers dual power supplies as well as a battery input pin. The dual power supplies support a
programmable trickle charge circuit which allows a rechargeable energy source (such as a super cap or
rechargeable battery) to be used for a backup supply. The V

pin allows the device to be backed up b y

BAT

a non-rechargeable battery. The DS1305 is fully operational from 2.0 to 5.5 volts.

Two programmable time of day alarms are provided by the DS1305. Each alarm can generate an
interrupt on a programmable combination of seconds, minutes, hours and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. The time of
day alarms can be programmed to assert two different interrupt outputs or to assert one common interrupt
output. Both interrupt outputs operate when the device is powered by V

CC1

, V

CC2

, or V

BAT

.

The DS1305 supports a direct interface to Motorola SPI serial data ports or standard 3-wir e interface. A
straightforward address and data format is implemented in which data transfers can occur 1 byte at a time
or in multiple-byte burst mode.

OPERATION

The block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The following
paragraphs describe the function of each pin.

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DS1305 BLOCK DIAGRAM Figure 1

DS1305

SIGNAL DESCRIPTIONS

V

- DC power is provided to the device on this pin. V

CC1

V

- This is the secondary power supply pin. In systems using the trickle charger, the rechargeable

CC2

energy source is connected to this pin.

V

- Battery input for any standard 3-volt lithium cell or other energy source.

BAT

V

(Interface Logic Power Supply Input) - The V

CCIF

out-put pins to a level that is compati ble with th e interface lo gic, thus allo wing an eas y interface t o 3-volt
logic in mixed supply systems. This pin is physically connected to the source connection of the p-channel

transistors in the output buffers of the SDO and PF pins.
SERMODE (Serial Interface Mode Input) - The SERMODE pin offers the flexibility to choose

between two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to V

, Motorola SPI communication is selected.

CC

SCLK (Serial Clock Input) - SC LK is used to synchronize data movement on the serial interface for
either the SPI or 3-wire interface.

SDI (Serial Data Input) - When SPI communication is selected, the SDI pin is the serial data input for
the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).

is the primary power supply.

CC1

pin allows the DS1305 to drive SDO and PF

CCIF

SDO (Serial Data Output) - When SP I communication is selected, the SDO pin is the serial data output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI
and SDO pins function as a single I/O pin when tied together).

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DS1305

CE (Chip Enable) - The Chip Enable signal must be asserted high during a read or a write for both 3-
wire and SPI communication. This pin has an internal 55K pull-down resistor (typical).

INT0 (Interrupt 0 Output) - The INT0 pin is an active low output of the DS1305 that can be used as an

interrupt input to a processor. The INT0 pin can be programmed to be asserted by only Alarm 0 or can be
programmed to be asserted by either Alarm 0 or Alarm 1. The INT0 pin remains low as long as the status
bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT0 pin
operates when the DS1305 is powered by V

CC1

CC2

, or V

. The INT0 pin is an open drain output and

BAT

, V

requires an external pull-up resistor.

INT1(Interrupt 1 Output) - The INT1 pin is an active low output of the DS1305 that can be used as an

interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1 only. The

INT1 pin remains low as long as the status bit causing the interrupt is present and the corresponding

interrupt enable bit is set. The INT1 pin operates when the DS1305 is powered by V

CC1

, V

CC2

, or V

BAT

The INT1 pin is an open drain output and requires an external pull-up resistor.

Both INT0 and INT1 are open drain outputs. The two interrupts and the internal clock continue to run
regardless of the level of V

(as long as a power source is present).

CC

.

PF (Power Fail Output) - The PF pin is used to indicate loss of the primary power supply (V

When V

is less than V

CC1

or is less than V

CC2

, the PF pin will be driven low.

BAT

CC1

X1, X2 - Connections for a standard 32.768 kHz quartz cr ystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6 pF. For more information on crystal
selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations
with Dallas Real Time Clocks.” The DS1305 can also be driven by an external 32.768 kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

).

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DS1305

RTC AND RAM ADDRESS MAP

The address map for the RTC and RAM registers of the DS1305 is shown in Figure 2. Data is written to
the RTC by writing to address locations 80h to 9Fh and is written to the RAM by writing to address
locations A0h to FFh. RTC data is read by reading address locations 00h to 1Fh and RAM data is read by
reading address locations 20h to 7Fh.

ADDRESS MAP Figure 2

00H

CLOCK/CALENDAR

1FH
20H

7FH
80H

9FH

A0H

FFH

READ ADDRESSES ONLY

96-BYTES USER RAM

READ ADDRESSES ONLY

CLOCK/CALENDAR

WRITE ADDRESSES ONLY

96-BYTES USER RAM

WRITE ADDRESSES ONLY

CLOCK, CALENDAR AND ALARM

The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time, calendar and alarm are set or initialized by writing
the appropriate register bytes. Note that some bits are set to zero. These bits will always read 0
regardless of how they are written. Also note that registers 12h to 1Fh (read) and r e gisters 92h to 9Fh are
reserved. These registers will always read 0 regardless of how they are written. The contents of the time,
calendar and alarm registers are in the binary-coded decimal (BCD) format.

Please note that the initial power on state of all registers in not defined. Therefore it is important to
enable the oscillator (EOSC = 0) and disable write protect (WP = 0) during initial configuration.

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RTC REGISTERS Figure 3
RTC Registers DS1305

DS1305

HEX ADDRESS
READ WRITE

00H 80H 0 10 SEC SEC 00-59
01H 81H 0 10 MIN MIN 00-59

03H 83H 0 0 0 0 DAY 01-07
04H 84H 0 0 10 DATE DATE 1-31
05H 85H 0 0 10 MONTH MONTH 01-12
06H 86H 10 YEAR YEAR 00-99

07H 87H M 10 SEC ALARM SEC ALARM 00-59
08H 88H M 10 MIN ALARM MIN ALARM 00-59

0AH 8AH M 0 0 0 DAY ALARM 01-07

0BH 8BH M 10 SEC ALARM SEC ALARM 00-59
0CH 8CH M 10 MIN ALARM MIN ALARM 00-59

0EH 8 EH M 0 0 0 DAY ALARM 01-07
0FH 8FH CONTROL REGIST ER
10H 90H STATUS REGISTER
11H 91H TRICKLE CHARGER REGISTER

12-1FH 92-9FH RESERVED

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RANGE

10 01-12 + P/A02H 82H 0 12/2

4

P/A

10 01-12 + P/A09H 89H M 12/2

4

P/A

10 01-12 + P/A0DH 8DH M 12/2

4

P/A

10 HR HOURS

00-23

Alarm 0

10 HR HOUR ALARM

00-23

Alarm 1

10 HR HOUR ALARM

00-23

Range For Alarm Registers Does Not Include Mask’m’ Bits.

The DS1305 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).

The DS1305 contains two time of day alarms. Time of Day Alarm 0 can be set by writing to re gisters
87h to 8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. The alarms can be
programmed (by the INTCN bit of the Control Register) to operate in two different modes - each al arm
can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of
each of the time of day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a
time of day alarm will only occur once per week when the values stored in timekeeping registers 00h to
03h match the values stored in the time of day alarm registers. An alarm will be generated every day
when bit 7 of the day alarm register is set to a logic 1. An alarm will be generated every hour when bit 7
of the day and hour alarm registers is set to a logic 1. Similarly, an alarm will be generated every minute
when bit 7 of the day, hour and minute alarm registers is set to a logic 1. When bit 7 of the da y, hour,
minute and seconds alarm registers is set to a logic 1, alarm will occur every second.

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DS1305

TIME OF DAY ALARM MASK BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

SECONDS MINUTES HOURS DAYS

1 1 1 1 Alarm once per second
0 1 1 1 Alarm when seconds match
0 0 1 1 Alarm when minutes and seconds match
0 0 0 1 Alarm hours, minutes and seconds match
0 0 0 0 Alarm day, hours, minutes and seconds match

SPECIAL PURPOSE REGISTERS

The DS1305 has three additional registers (Control Register, Status Register and Trickle Charger
Register) that control the real time clock, interrupts and trickle charger.

CONTROL REGISTER (READ 0FH, WRITE 8FH)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

EOSC

EOSC (Enable oscillator) - This bit when set to logic 0 will start the oscillator. When this bit is set to a

WP 0 0 0 INTCN AIE1 AIE0

logic 1, the oscillator is stopped and the DS1305 is placed into a low-power standb y mode with a cu rrent
drain of less than 100 nanoamps when power is supplied by V

BAT

or V

. The initial power on state is

CC2

not defined.

WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, 2 and 7 of the
control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should
be cleared before attempting to write to the device.

INTCN (Interrupt Control) - This bit controls the relationship between the two time of day alarms and
the interrupt output pins. When the INTCN bit is set to a logic 1, a match between the timekeeping

registers and the Alarm 0 registers will activate the
match between the timekeeping registers and the Alarm 1 registers will activate the

INT0 pin (provided that the alarm is enabled) and a

INT1 pin (provided

that the alarm is enabled). When the INTCN bit is set to a logic 0, a match between the timekeeping
registers and either Alarm 0 or Alarm 1 will activate the

INT1 has no function when INTCN is set to a logic 0.

INT0 pin (provided that the alarms are enabled).

AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag
(IRQF0) bit in the status register to assert INT0 . When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the

INT0 signal.

AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag
(IRQF1) bit in the status register to assert INT1 (when INTCN=1) o r to assert INT0 (when INTCN=0).

When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal.

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