Dallas Semiconductor DS12887 Datasheet

NC

DS12887

Real Time Clock

www.dalsemi.com

FEATURES

§ Drop–in replacement for IBM AT computer

clock/calendar

§ Pin-compatible with the MC146818B and

DS1287

§ Totally nonvolatile with over 10 years of

operation in the absence of power

§ Self–contained subsystem includes lithium,

quartz, and support circuitry

§ Counts seconds, minutes, hours, days, day of

the week, date, month, and year with leap
year compensation valid up to 2100

§ Binary or BCD representation of time,

calendar, and alarm

§ 12– or 24–hour clock with AM and PM in

12–hour mode

§ Daylight Savings Time option

§ Selectable between Motorola and Intel bus

timing

§ Multiplex bus for pin efficiency

§ Interfaced with software as 128 RAM

locations
– 14 bytes of clock and control registers
– 114 bytes of general purpose RAM

§ Programmable square wave output signal

§ Bus–compatible interrupt signals ( IRQ )

§ Three interrupts are separately software–

maskable and testable
– Time–of–day alarm once/second to

once/day
– Periodic rates from 122 ms to 500 ms
– End of clock update cycle

PIN ASSIGNMENT

PIN DESCRIPTION

AD0–AD7 – Multiplexed Address/Data Bus
NC – No Connection
MOT – Bus Type Selection

CS – Chip Select

AS – Address Strobe
R/ W – Read/Write Input

DS – Data Strobe

RESET – Reset Input

IRQ – Interrupt Request Output

SQW – Square Wave Output
VCC – +5 Volt Supply
GND – Ground

DESCRIPTION

The DS12887 Real Time Clock plus RAM is designed to be a direct replacement for the DS1287. The
DS12887 is identical in form, fit, and function to the DS1287, and has an additional 64 bytes of general
purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6
during the address portion of an access cycle. A lithium energy source, quartz crystal, and write–
protection circuitry are contained within a 24–pin dual in-line package. As such, the DS12887 is a
complete subsystem replacing 16 components in a typical application. The functions include a nonvolatile
time–of–day clock, an alarm, a one-hundred–year calendar, programmable interrupt, square wave

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generator, and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time–of–day
and memory are maintained even in the absence of power.

OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS12887. The following paragraphs describe the function of each pin.

BLOCK DIAGRAM DS12887 Figure 1

POWER–DOWN/POWER–UP CONSIDERATIONS

The Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the V

input. When VCC is applied to the

CC

DS12887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200 ms,
provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A).
This time period allows the system to stabilize after power is applied. When V

falls below 4.25 volts,

CC

the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin.
The DS12887 is, therefore, write–protected. When the DS12887 is in a write–protected state, all inputs
are ignored and all outputs are in a high impedance state. When V
3 volts, the external V

supply is switched off and an internal lithium energy source supplies power to

CC

falls below a level of approximately

CC

the Real Time Clock and the RAM memory.

SIGNAL DESCRIPTIONS

GND, V
applied within normal limits, the device is fully accessible and data can be written and read. When V
below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues

– DC power is provided to the device on these pins. VCC is the +5 volt input. When 5 volts are

CC

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CC

is

DS12887

unaffected by the lower input voltage. As V

falls below 3 volts typical, the RAM and timekeeper are

CC

switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of ±1
minute per month at 25°C regardless of the voltage input on the VCC pin.

MOT (Mode Select) – The MOT pin offers the flexibility to choose between two bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel
bus timing is selected. The pin has an internal pulldown resistance of approximately 20 kΩ.

SQW (Square Wave Output) – The SQW pin can output a signal from one of 13 taps provided by the
15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE
bit in Register B. The SQW signal is not available when V

is less than 4.25 volts, typically.

CC

PERIODIC INTERRUPT RATE AND SQUARE
WAVE OUTPUT FREQUENCY Table 1

SELECT BITS REGISTER A

RS3 RS2 RS1 RS0

0 0 0 0 None None
0 0 0 1 3.90625 ms 256 Hz
0 0 1 0 7.8125 ms 128 Hz
0 0 1 1
0 1 0 0

0 1 0 1
0 1 1 0
0 1 1 1 1.953125 ms 512 Hz
1 0 0 0 3.90625 ms 256 Hz
1 0 0 1 7.8125 ms 128 Hz
1 0 1 0 15.625 ms 64 Hz
1 0 1 1 31.25 ms 32 Hz
1 1 0 0 62.5 ms 16 Hz
1 1 0 1 125 ms 8 Hz
1 1 1 0 250 ms 4 Hz
1 1 1 1 500 ms 2 Hz

tPI PERIODIC

INTERRUPT RATE

122.070 µs

244.141 µs

488.281 µs

976.5625 µs

SQW OUTPUT

FREQUENCY

8.192 kHz

4.096 kHz

2.048 kHz

1.024 kHz

AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS12887 since the
bus change from address to data occurs during the internal RAM access time. Addresses must be valid
prior to the falling edge of AS/ ALE, at which time the DS12887 latches the address from AD0 to AD6.

Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a
read cycle the DS12887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read

cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of
Motorola timing or as RD transitions high in the case of Intel timing.

AS (Address Strobe Input) – A positive-going address strobe pulse serves to demultiplex the bus. The
falling edge of AS/ALE causes the address to be latched within the DS12887. The next rising edge that

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occurs on the AS bus will clear the address regardless of whether CS is asserted. Access commands
should be sent in pairs.

DS (Data Strobe or Read Input) – The DS/ RD pin has two modes of operation depending on the level
of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this mode
DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read
cycles, DS signifies the time that the DS12887 is to drive the bidirectional bus. In write cycles the trailing
edge of DS causes the DS12887 to latch the written data. When the MOT pin is connected to GND, Intel

bus timing is selected. In this mode the DS pin is called Read ( RD ).RD identifies the time period when
the DS12887 drives the bus with read data. The RD signal is the same definition as the Output Enable
(OE ) signal on a typical memory.

R/W (Read/Write Input) – The R/ W pin also has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/ W is at a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on R/ W while DS is high. A write cycle is
indicated when R/ W is low during DS.

When the MOT pin is connected to GND for Intel timing, the R/ W signal is an active low signal called
WR. In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic RAMs.

CS (Chip Select Input) – The Chip Select signal must be asserted low for a bus cycle in the DS12887 to

be accessed. CS must be kept in the active state during DS and AS for Motorola timing and during RD
and WR for Intel timing. Bus cycles which take place without asserting CS will latch addresses but no

access will occur. When VCC is below 4.25 volts, the DS12887 internally inhibits access cycles by
internally disabling the CS input. This action protects both the real time clock data and RAM data during

power outages.

IRQ (Interrupt Request Output) – The IRQ pin is an active low output of the DS12887 that can be

used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the
interrupt is present and the corresponding interrupt–enable bit is set. To clear the IRQ pin the processor
program normally reads the C register. The RESET pin also clears pending interrupts.

When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an

external pullup resistor.

RESET (Reset Input) – The RESET pin has no effect on the clock, calendar, or RAM. On power–up the

RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time

that RESET is held low is dependent on the application. However, if RESET is used on power–up, the
time RESET is low should exceed 200 ms to make sure that the internal timer that controls the DS12887
on power-up has timed out. When RESET is low and VCC is above 4.25 volts, the following occurs:

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A. Periodic Interrup t Enable (PEI) bit is cleared to 0.
B. Alarm Interrupt Enable (AIE) bit is cleared to 0.
C. Update Ended Interrupt Flag (UF) bit is cleared to 0.
D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.
E. Periodic Interrupt Flag (PF) bit is cleared to 0.

F. The device is not accessible until RESET is returned high.
G. Alarm Interrupt Flag (AF) bit is cleared to 0.

H. IRQ pin is in the high impedance state.
I. Square Wave Output Enable ( SQWE ) bit is cleared to 0.

J. Update Ended Interrupt Enable (UIE) is cleared to 0.

In a typical application RESET can be connected to VCC. This connection will allow the DS12887 to go in
and out of power fail without affecting any of the control registers.

ADDRESS MAP

The address map of the DS12887 is shown in Figure 2. The address map consists of 114 bytes of user
RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used
for control and status. All 128 bytes can be directly written or read except for the following:

1. Registers C and D are read–only.

2. Bit 7 of Register A is read–only.

3. The high order bit of the seconds byte is read–only.

The contents of four registers (A,B,C, and D) are described in the “Registers” section.

ADDRESS MAP DS12887 Figure 2

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DS12887

TIME, CALENDAR AND ALARM LOCATIONS

The time and calendar information is obtained by reading the appropriate memory bytes. The time,
calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10
time, calendar, and alarm bytes can be either Binary or Binary–Coded Decimal (BCD) format. Before
writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a
logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10
time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of
Register B must be set to the appropriate logic level. All 10 time, calendar, and alarm bytes must use the
same data mode. The set bit in Register B should be cleared after the data mode bit has been written to
allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock
makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 10
data bytes. Table 2 shows the binary and BCD formats of the 10 time, calendar, and alarm locations. The
24–12 bit cannot be changed without reinitializing the hour locations. When the 12–hour format is
selected, the high order bit of the hours byte represents PM when it is a logic 1. The time, calendar, and
alarm bytes are always accessible because they are double buffered. Once per second the 10 bytes are
advanced by 1 second and checked for an alarm condition. If a read of the time and calendar data occurs
during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability
of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect
time and calendar reads are covered later in this text.

The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate
hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day
if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of
the three alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The two most
significant bits of each byte set the “don’t care” condition when at logic 1. An alarm will be generated
each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every
minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three
alarm bytes create an interrupt every second.

TIME, CALENDAR AND ALARM DATA MODES Table 2

LOCATION

0 Seconds 0-59 00-3B 00-59
1 Seconds Alarm 0-59 00-3B 00-59
2 Minutes 0-59 00-3B 00-59
3 Minutes Alarm 0-59 00-3B 00-59

6 Day of the Week

7 Date of the Month 1-31 01-1F 01-31
8 Month 1-12 01-0C 01-12
9 Year 0-99 00-63 00-99

FUNCTION

Hours-12-hr Mode 1-12 01-0C AM, 81-8C PM 01-12AM, 81-92PM4
Hours-24-hr Mode 0-23 00-17 00-23
Hours Alarm-12-hr 1-12 01-0C AM, 81-8C PM 01-12AM, 81-92PM5
Hours Alarm-24-hr 0-23 00-17 00-23

Sunday = 1

DECIMAL

RANGE BINARY DATA MODE BCD DATA MODE

1-7 01-07 01-07

RANGEADDRESS

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