Dallas Semiconductor DS1245YP-70-IND, DS1245YP-70, DS1245YP-100, DS1245Y-85, DS1245Y-70-IND Datasheet

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FEATURES

 10 years minimum data retention in the

absence of external power

 Data is automatically protected during power

loss

 Replaces 128k x 8 volatile static RAM,

EEPROM or Flash memory

 Unlimited write cycles
 Low-power CMOS
 Read and write access times as fast as 70 ns
 Lithium energy source is electrically

disconnected to retain freshness until power is
applied for the first time

 Full ±10% VCC operating range (DS1245Y)
 Optional ±5% VCC operating range

(DS1245AB)

 Optional industrial temperature range of

-40°C to +85°C, designated IND

 JEDEC standard 32-pin DIP package
 New PowerCap Module (PCM) package

- Directly surface-mountable module

- Replaceable snap-on PowerCap provides

lithium backup battery

- Standardized pinout for all nonvolatile

SRAM products

- Detachment feature on PowerCap allows

easy removal using a regular screwdriver

PIN ASSIGNMENT

PIN DESCRIPTION

A0 - A16 - Address Inputs
DQ0 - DQ7 - Data In/Data Out

CE - Chip Enable
WE - Write Enable
OE - Output Enable

V

CC

- Power (+5V)
GND - Ground
NC - No Connect

DS1245Y/AB

1024k Nonvolatile SRAM

www.dalsemi.com

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31

32-PIN ENCAPSULATED PACKAGE

740 MIL EXTENDED

A14

A7

A5
A4
A3
A2
A1

A0

DQ1

DQ0

V

A

15
NC
WE

A

13

A8A

9

A

11
OE

A

10
CE

DQ7

DQ5

DQ6

32

30
29

28
27

26
25

24
23

22
21

19

20

A16

A12

A6

NC

DQ2

GND

15
16

18
17

DQ4
DQ3

1

NC

2
3

A15
A16

NC

V

CC

WE

OE

CE
DQ7
DQ6
DQ5
DQ4
DQ3

DQ2
DQ1
DQ0

GND

4
5
6
7
8
9
10
11
12
13
14
15
16
17

NC

A

14

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32
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30
29
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27
26
25
24
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22
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20
19
18

A

13

A

12

A11A10A9A8A7A

6

A

5

A4A

3

A

2

A1A

0

34

NC

GND

V

BAT

34-PIN POWERCAP MODULE (PCM)

(USES DS9034PC POWERCAP)

DS1245Y/AB

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DESCRIPTION

The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, nonvolatile SRAMs organized as
131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1245 devices can be used in place of existing 128k x
8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245 devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

READ MODE

The DS1245 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique address specified b y the 17 address inputs (A0 -

A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the eight
data output drivers within t

ACC

(Access Time) after the last address input signal is stable, providin g that

CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied,

then data access must be measured from the later occurring signal (CE or OE ) and the limiting parameter
is either tCO for CE or tOE for OE rather than address access.

WRITE MODE

The DS1245 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE

will disable the outputs in t

ODW

from its falling edge.

DATA RETENTION MODE

The DS1245AB provides full functional capability for VCC greater than 4.75 volts and write protects by

4.5 volts. The DS1245Y provides full functional capability for V

CC

greater than 4.5 volts and write-

protects by 4.25 volts. Data is maintained in the absence of V

CC

without any additional support circuitry.

The nonvolatile static RAMs constantly monitor V

CC

. Should the supply voltage decay, the NV SRAMs
automatically write-protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As V

CC

falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V

CC

exceeds 4.75 volts for the DS1245AB and 4.5 volts for the

DS1245Y.

FRESHNESS SEAL

Each DS1245 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacit y. When V

CC

is first applied at a level greater than 4.25 volts, the lithium

energy source is enabled for battery back-up operation.

DS1245Y/AB

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PACKAGES

The DS1245 devices are available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM).
The 32-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a
single package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1245 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1245 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1245 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See the DS9034PC data sheet for further information.

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C, -40°C to +85°C for Ind parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for Ind parts
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

DS1245AB Power Supply Voltage V

CC

4.75 5.0 5.25 V

DS1245Y Power Supply Voltage V

CC

4.5 5.0 5.5 V

Logic 1 V

IH

2.2 V

CC

V

Logic 0 V

IL

0.0 0.8 V

DC ELECTRICAL (VCC=5V ±=5% for DS1245AB)
CHARACTERISTICS (t

A

: See Note 10) (VCC=5V ±=10% for DS1245Y)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current I

IL

-1.0 +1.0

µA

I/O Leakage Current CE ≥ VIH ≤ V

CC

I

IO

-1.0 +1.0

µA

Output Current @ 2.4V I

OH

-1.0 mA

Output Current @ 0.4V I

OL

2.0 mA

Standby Current CE =2.2V

I

CCS1

5.0 10.0 mA

Standby Current CE =VCC-0.5V

I

CCS2

3.0 5.0 mA

Operating Current I

CCO1

85 mA

Write Protection Voltage (DS1245AB) V

TP

4.50 4.62 4.75 V

Write Protection Voltage (DS1245Y) V

TP

4.25 4.37 4.5 V

DS1245Y/AB

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CAPACITANCE (tA=25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C

IN

510pF

Input/Output Capacitance C

I/O

510pF

AC ELECTRICAL (VCC=5V ±=5% for DS1245AB)
CHARACTERISTICS (t

A

: See Note 10) (VCC=5V ±=10% for DS1245Y)

DS1245AB-70

DS1245Y-70

DS1245AB-85

DS1245Y-85

PARAMETER SYMBOL

MIN MAX MIN MAX

UNITS NOTES

Read Cycle Time t

RC

70 85 ns

Access Time t

ACC

70 85 ns

OE to Output Valid

t

OE

35 45 ns

CE to Output Valid

t

CO

70 85 ns

OE or CE to Output Active

t

COE

5 5 ns 5

Output High Z from Deselection t

OD

25 30 ns 5

Output Hold from Address Change t

OH

55ns

Write Cycle Time t

WC

70 85 ns

Write Pulse Width t

WP

55 65 ns 3

Address Setup Time t

AW

00ns

Write Recovery Time t

WR1

t

WR2

5

15

5

15

ns
ns

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Output High Z from WE

t

ODW

25 30 ns 5

Output Active from WE

t

OEW

5 5 ns 5

Data Setup Time t

DS

30 35 ns 4

Data Hold Time t

DH1

t

DH2

0

10

0

10

ns
ns

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