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DS1245Y/AB
1024k Nonvolatile SRAM
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Replaces 128k x 8 volatile static RAM,
EEPROM or Flash memory
Unlimited write cycles
Low-power CMOS
Read and write access times as fast as 70 ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Full ±10% VCC operating range (DS1245Y)
Optional ±5% VCC operating range
(DS1245AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
JEDEC standard 32-pin DIP package
New PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
NC
A15
A16
NC
V
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
NC
A16
A14
A12
DQ0
DQ1
DQ2
GND
32-PIN ENCAPSULATED PACKAGE
CC
34-PIN POWERCAP MODULE (PCM)
1
2
3
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
12
A0
13
14
15
16
740 MIL EXTENDED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
(USES DS9034PC POWERCAP)
GND
V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
BAT
15
NC
WE
13
9
11
OE
10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
14
13
12
6
5
3
2
0
PIN DESCRIPTION
A0 - A16 - Address Inputs
DQ0 - DQ7 - Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable
- Power (+5V)
V
CC
GND - Ground
NC - No Connect
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DS1245Y/AB
DESCRIPTION
The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, nonvolatile SRAMs organized as
131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1245 devices can be used in place of existing 128k x
8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245 devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1245 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique address specified b y the 17 address inputs (A0 -
A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the eight
data output drivers within t
CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied,
then data access must be measured from the later occurring signal (CE or OE ) and the limiting parameter
is either tCO for CE or tOE for OE rather than address access.
(Access Time) after the last address input signal is stable, providing that
ACC
WRITE MODE
The DS1245 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in t
from its falling edge.
ODW
DATA RETENTION MODE
The DS1245AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1245Y provides full functional capability for V
protects by 4.25 volts. Data is maintained in the absence of V
The nonvolatile static RAMs constantly monitor V
. Should the supply voltage decay, the NV SRAMs
CC
CC
automatically write-protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As V
falls below approximately 3.0 volts, a power switching circuit connects the lithium
CC
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
exceeds 4.75 volts for the DS1245AB and 4.5 volts for the
CC
DS1245Y.
greater than 4.5 volts and write-
CC
without any additional support circuitry.
FRESHNESS SEAL
Each DS1245 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacit y. When V
energy source is enabled for battery back-up operation.
is first applied at a level greater than 4.25 volts, the lithium
CC
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DS1245Y/AB
PACKAGES
The DS1245 devices are available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM).
The 32-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a
single package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1245 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1245 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1245 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C, -40°C to +85°C for Ind parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for Ind parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1245AB Power Supply Voltage V
DS1245Y Power Supply Voltage V
Logic 1 V
Logic 0 V
CC
CC
IH
IL
4.75 5.0 5.25 V
4.5 5.0 5.5 V
2.2 V
CC
V
0.0 0.8 V
DC ELECTRICAL (VCC=5V ±=5% for DS1245AB)
CHARACTERISTICS (t
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
I/O Leakage Current CE ≥ VIH ≤ V
Output Current @ 2.4V I
Output Current @ 0.4V I
Standby Current CE =2.2V
Standby Current CE =VCC-0.5V
CC
: See Note 10) (VCC=5V ±=10% for DS1245Y)
A
I
OH
OL
I
CCS1
I
CCS2
IL
IO
-1.0 +1.0
-1.0 +1.0
-1.0 mA
2.0 mA
5.0 10.0 mA
3.0 5.0 mA
µA
µA
Operating Current I
Write Protection Voltage (DS1245AB) V
Write Protection Voltage (DS1245Y) V
CCO1
TP
TP
85 mA
4.50 4.62 4.75 V
4.25 4.37 4.5 V
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DS1245Y/AB
CAPACITANCE (tA=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Input/Output Capacitance C
IN
I/O
510pF
510pF
AC ELECTRICAL (VCC=5V ±=5% for DS1245AB)
CHARACTERISTICS (t
PARAMETER SYMBOL
Read Cycle Time t
Access Time t
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High Z from Deselection t
Output Hold from Address Change t
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t
Output High Z from WE
ACC
t
t
t
COE
OD
OH
WC
WP
AW
WR1
t
WR2
t
ODW
: See Note 10) (VCC=5V ±=10% for DS1245Y)
A
RC
DS1245AB-70
DS1245Y-70
MIN MAX MIN MAX
70 85 ns
DS1245AB-85
DS1245Y-85
UNITS NOTES
70 85 ns
OE
CO
35 45 ns
70 85 ns
5 5 ns 5
25 30 ns 5
55ns
70 85 ns
55 65 ns 3
00ns
5
15
5
15
ns
ns
25 30 ns 5
12
13
Output Active from WE
Data Setup Time t
Data Hold Time t
t
OEW
DH1
t
DH2
DS
5 5 ns 5
30 35 ns 4
0
10
0
10
ns
ns
12
13
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