Dallas Semiconductor DS1243Y-150, DS1243Y-120, DS1243Y Datasheet

DS1243Y

64K NV SRAM with Phantom Clock

www.dalsemi.com

A7A5A3

A2

A1

A0

DQ0

DQ1

GND

DQ2

V

CC

NCA8A9

A11OEA10CEDQ7

DQ6

DQ5

DQ3

DQ4

12345

678910111214132827262524232221201918171516

A12A6A4

RST

FEATURES

§ Real time clock keeps track of hundredths of

seconds, seconds, minutes, hours, days, date
of the month, months, and years

§ 8K x 8 NV SRAM directly replaces volatile

static RAM or EEPROM

§ Embedded lithium energy cell maintains

calendar operation and retains RAM data

§ Watch function is transparent to RAM

operation

§ Month and year determine the number of days

in each month; valid up to 2100

§ Lithium energy source is electrically

disconnected to retain freshness until power is
applied for the first time

§ Standard 28–pin JEDEC pinout

§ Full ±10% operating range

§ Operating temperature range 0°C to 70°C

§ Accuracy is better than ±1 minute/month @

25°C

§ Over 10 years of data retention in the absence

of power

§ Available in 120, 150 and 200 ns access time

ORDERING INFORMATION

DS1243Y–XXX

–120 120 ns access
–150 150 ns access

DS1243Y 200 ns access

PIN ASSIGNMENT

WE

28-Pin Encapsulated Package

720-Mil Extended

PIN DESCRIPTION

A0–A12 – Address Inputs

CE

GND – Ground
DQ0–DQ7 – Data In/Data Out
VCC – Power (+5V)

WE

– Output Enable

OE

NC – No Connect

RST

– Chip Enable

– Write Enable

– Reset

DESCRIPTION

The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192
words by 8 bits) with a built–in real time clock. The DS1243Y has a self–contained lithium energy source
and control circuitry which constantly monitors VCC for an out–of–tolerance condition. When such a
condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent corrupted data in both the memory and real time clock.

1 of 13 080299

DS1243Y

The Phantom Clock provides timekeeping information including hundredths of seconds, seconds,
minutes, hours, day, date, month, and year information. The date at the end of the month is automatically
adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock
operates in either 24–hour or 12–hour format with an AM/PM indicator.

RAM READ MODE

The DS1243Y executes a read cycle whenever

(Write Enable) is inactive (high) and CE (Chip

WE

Enable) is active (low). The unique address specified by the 13 address inputs (A0–A12) defines which of
the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers

within t

(Access Time) after the last address input signal is stable, providing that

ACC

and OE (Output

CE

Enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data
access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either
t

CO

for

CE

or t

OE

for

rather than address access.

OE

RAM WRITE MODE

The DS1243Y is in the write mode whenever the
address inputs are stable. The latter occurring falling edge of CE or
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must
be kept valid throughout the write cycle.

must return to the high state for a minimum recovery time

WE

(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then

will disable the outputs in t ODW from its falling edge.

WE

and CE signals are in the active (low) state after

WE

will determine the start of the

WE

DATA RETENTION MODE

The DS1243Y provides full functional capability for V
volts. Data is maintained in the absence of V

without any additional support circuitry. The nonvolatile

CC

static RAM constantly monitors VCC. Should the supply voltage decay, the RAM automatically write
protects itself. All inputs to the RAM become “don’t care” and all outputs are high impedance. As V
falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power–up, when V
switching circuit connects external V
RAM operation can resume after V

to the RAM and disconnects the lithium energy source. Normal

CC

exceeds 4.5 volts.

CC

CC

greater than VTP and write protects by 4.25

CC

CC

rises above approximately 3.0 volts, the power

FRESHNESS SEAL

Each DS1243Y is shipped from Dallas Semiconductor with its lithium energy source disconnected,
insuring full energy capacity. When V

is first applied at a level greater than V

CC

, the lithium energy

TP

source is enabled for battery backup operation.

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.

2 of 13

DS1243Y

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable (CE), Output Enable (OE), and Write Enable (WE). Initially, a read cycle to any memory
location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by

moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and

control of the SmartWatch. These 64 write cycles are used only to gain

WE

access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable.
However, the write cycles generated to gain access to the Phantom Clock are also writing data to a
location in the mated RAM. The preferred way to manage this requirement is to set aside just one address
location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared
to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the next location
of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not
advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern
recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the
Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64
cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of

the OE pin or the

cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom

CE

pin. Cycles to other locations outside the memory block can be interleaved with

WE

Clock.

PHANTOM CLOCK
REGISTER INFORMATION

The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64–bit pattern recognition sequence has been completed. When updating
the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.

Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.

3 of 13

PHANTOM CLOCK REGISTER DEFINITION Figure 1

DS1243Y

NOTE:

The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Clock is less than 1 in 1019. This
pattern is sent to the Phantom Clock LSB to MSB.

4 of 13