Dallas Semiconductor DS1232SN, DS1232S, DS1232N, DS1232 Datasheet

www.dalsemi.com

DS1232

MicroMonitor Chip

FEATURES

 Halts and restarts an out-of-control

microprocessor

 Holds microprocessor in check during power

transients

 Automatically restarts microprocessor after

power failure

 Monitors pushbutton for external override
 Accurate 5% or 10% microprocessor power

supply monitoring

 Eliminates the need for discrete components
 Space-saving, 8-pin mini-DIP
 Optional 16-pin SOIC surface mount package
 Industrial temperature -40°C to +85°C

available, designated N

PIN ASSIGNMENT

TD

1
2

3
4

1
2

3
4
5
6
7
8

PBRST

TOL

GND

DS1232 8-Pin DIP (300-mil)
See Mech. Drawings Section

NC

PBRST

NC

TD

NC

TOL

NC

GND

DS1232S 16-Pin SOIC (300-mil)

See Mech. Drawings Section

16
15

14
13
12
11
10

VCC

8

ST

7

RST

6

RST

5

NC
VCC

NC
ST
NC
RST
NC
RST

9

PIN DESCRIPTION

PBRST - Pushbutton Reset Input

TD - Time Delay Set
TOL - Selects 5% or 10% VCC Detect
GND - Ground
RST - Reset Output (Active High)

RST - Reset Output (Active Low, open

drain)

ST - Strobe Input

VCC - +5 Volt Power
NC - No Connections

DESCRIPTION

The DS1232 MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply,
software execution, and external override. First, a precision temperature-compensated reference and
comparator circuit monitors the status of V
power fail signal is generated which forces reset to the active state. When VCC returns to an in-tolerance
condition, the reset signals are kept in the active state for a minimum of 250 ms to allow the power supply
and processor to stabilize.

. When an out-of-tolerance condition occurs, an internal

CC

1 of 7 111899

DS1232/DS1232S

The second function the DS1232 performs is pushbutton reset control. The DS1232 debounces the
pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a
watchdog timer. The DS1232 has an internal timer that forces the reset signals to the active state if the
strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on
timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds.

OPERATION - POWER MONITOR

The DS1232 detects out-of-tolerance power supply conditions and warns a processor-based system of
impending power failure. When VCC falls below a preset level as defined by TOL (Pin 3), the V

CC

comparator outputs the signals RST (Pin 5) and RST (Pin 6). When TOL is connected to ground, the RST
and RST signals become active as VCC falls below 4.75 volts. When TOL is connected to VCC, the RST
and RST signals become active as VCC falls below 4.5 volts. The RST and RST are excellent control

signals for a microprocessor, as processing is stopped at the last possible moments of valid VCC. On
power-up, RST and

RST are kept active for a minimum of 250 ms to allow the power supply and

processor to stabilize.

OPERATION - PUSHBUTTON RESET

The DS1232 provides an input pin for direct connection to a pushbutton (Figure 2). The pushbutton reset
input requires an active low signal. Internally, this input is debounced and timed such that RST and RST

signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is
released from low level.

OPERATION - WATCHDOG TIMER

A watchdog timer function forces RST and RST signals to the active state when the ST input is not
stimulated for a predetermined time period. The time period is set by the TD input to be t ypically 150 ms
with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to

VCC. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive.
If a high-to-low transition occurs on the ST input pin prior to timeout, the watchdog timer is reset and
begins to timeout again. If the watchdog timer is allowed to timeout, then the RST and RST signals are
driven to the active state for 250 ms minimum. The

address signals, data signals, and/or control signals. When the microprocessor is functioning normally,
these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To guarantee
that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum
shown in Table 1. A typical circuit example is shown in Figure 3.

ST input can be derived from microprocessor

2 of 7

MICROMONITOR BLOCK DIAGRAM Figure 1

PUSHBUTTON RESET Figure 2

DS1232/DS1232S

WATCHDOG TIMER Figure 3

3 of 7