Dallas Semiconductor DS1231S, DS1231 Datasheet
DS1231/S
DS1231/S
Power Monitor Chip
FEATURES
• Warns processor of an impending power failure
• Provides time for an orderly shutdown
• Prevents processor from destroying nonvolatile
memory during power transients
• Automatically restarts processor after power is
restored
• Suitable for linear or switching power supplies
• Adjusts to hold time of the power supply
• Supplies necessary signals for processor interface
• Accurate 5% or 10% V
monitoring
CC
• Replaces power-up reset circuitry
• No external capacitors required
• Optional 16-pin SOIC surface mount package
DESCRIPTION
The DS1231 Power Monitor Chip uses a precise temperature-compensated reference circuit which provides
an orderly shutdown and an automatic restart of a processor-based system. A signal warning of an impending
power failure is generated well before regulated DC
voltages go out of specification by monitoring high voltage inputs to the power supply regulators. If line isolation is required a UL-approved opto-isolator can be directly interfaced to the DS1231. The time for processor
PIN ASSIGNMENT
1
8
IN
2
MODE
3
TOL
4
GND
DS1231 8–Pin DIP
(300 MIL)
See Mech. Drawings
Section
1
NC
2
IN
3
NC
MODE
GND
4
5
NC
6
TOL
7
NC
8
DS1231S 16–Pin SOIC
See Mech. Drawings
(300 MIL)
Section
VCC
NMI
7
RST
6
5
RST
NC
16
15
VCC
NC
14
13
NMI
NC
12
RST
11
10
NC
9
RST
PIN DESCRIPTION
IN – Input
MODE – Selects input pin characteristics
TOL – Selects 5% or 10% V
GND – Ground
RST – Reset (Active High)
RST
NMI
V
CC
– Reset (Active Low, open drain)
– Non–Maskable Interrupt
– +5V Supply
NC – No Connections
shutdown is directly proportional to the available
hold-up time of the power supply. Just before the
hold-up time is exhausted, the Power Monitor unconditionally halts the processor to prevent spurious cycles
by enabling Reset as V
falls below a selectable 5 or
CC
10 percent threshold. When power returns, the processor is held inactive until well after power conditions have
stabilized, safeguarding any nonvolatile memory in the
system from inadvertent data changes.
CC
detect
022698 1/9
DS1231/S
OPERATION
The DS1231 Power Monitor detects out-of-tolerance
power supply conditions and warns a processor-based
system of impending power failure. The main elements
of the DS1231 are illustrated in Figure 1. As shown, the
DS1231 actually has two comparators, one for monitoring the input (Pin 1) and one for monitoring V
The VCC comparator outputs the signals RST (Pin 5)
and RST (Pin 6) when VCC falls below a preset trip level
as defined by TOL (Pin 3).
When TOL is connected to ground, the RST and RST
signals will become active as VCC goes below 4.75
volts. When TOL is connected to VCC, the RST and RST
signals become active as VCC goes below 4.5 volts. The
RST and RST signals are excellent control signals for a
microprocessor, as processing is stopped at the last
possible moments of valid V
. On power-up, RST and
CC
RST are kept active for a minimum of 150 ms to allow the
power supply to stabilize (see Figure 2).
The comparator monitoring the input pin produces the
NMI
signal (Pin 7) when the input threshold voltage
(VTP) falls to a level as determined by Mode (Pin 2).
When the Mode pin is connected to V
CC
curs at VTP-. In this mode Pin 1 is an extremely high impedance input allowing for a simple resistor voltage divider network to interface with high voltage signals.
When the Mode pin is connected to ground, detection
occurs at V
+. In this mode Pin 1 sources 30 µA of cur-
TP
rent allowing for connection to switched inputs, such as
a UL-approved opto-isolator. The flexibility of the input
pin allows for detection of power loss at the earliest point
in a power supply system, maximizing the amount of
time allotted between NMI
and RST . On power-up, NMI
is released as soon as the input threshold voltage (VTP)
is achieved and VCC is within nominal limits. In both
(Pin 8).
CC
, detection oc-
modes of operation the input pin has hysteresis for
noise immunity (Figure 3).
APPLICATION – MODE PIN
CONNECTED TO V
When the Mode pin is connected to VCC, pin 1 is a high
impedance input. The voltage sense point and the level
of voltage at the sense point are dependent upon the
application (Figure 4). The sense point may be developed from the AC power line by rectifying and filtering
the AC. Alternatively, a DC voltage level may be selected which is closer to the AC power input than the
regulated +5-volt supply , so that ample time is provided
for warning before regulation is lost.
Proper operation of the DS1231 requires a maximum
voltage of 5 volts at the input (Pin 1), which must be
derived from the maximum voltage at the sense point.
This is accomplished with a simple voltage divider network of R1 and R2. Since the IN trip point V
volts (using the -20 device), and the maximum allowable
voltage on pin 1 is 5 volts, the dynamic range of voltage
at the sense point is set by the ratio of 2.3/5.0=.46 min.
This ratio determines the maximum deviation between
the maximum voltage at the sense point and the actual
voltage which will generate NMI
Having established the desired ratio, and confirming
that the ratio is greater than .46 and less than 1, the
proper values for R1 and R2 can be determined by the
equation as shown in Figure 4. A simple approach to
solving this equation is to select a value for R2 which is
high enough impedance to keep power consumption
low, and solve for R1. Figure 5 illustrates how the
DS1231 can be interfaced to the AC power line when
the mode pin is connected to V
CC
CC
- is 2.3
TP
.
.
022698 2/9
POWER MONITOR BLOCK DIAGRAM Figure 1
30A
IN
1
GND
4
V
CC
8
TOL
3
V
CC
TOLERANCE
BIAS
T.C. REFERENCE
NMI
MODE
SELECTION
DIGITAL
SAMPLER
DIGITAL
DELAY
DS1231/S
MODE
2
NMI
7
RST
6
RST
5
POWER-UP RESET Figure 2
DS1231
IN
MODE
TOL
GND
(-5% VCC THRESHOLD)
V
NMI
RST
RST
CC
+5V
NC
MICROPROCESSOR
RST
8051
µP
022698 3/9
Loading...