Dallas Semiconductor DS1230WP-150, DS1230WP-100, DS1230W-150, DS1230W-100 Datasheet

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FEATURES

 10 years minimum data retention in the

absence of external power

 Data is automatically protected during power

loss

 Replaces 32k x 8 volatile static RAM,

EEPROM or Flash memory

 Unlimited write cycles
 Low-power CMOS
 Read and write access times as fast as 150 ns
 Lithium energy source is electrically

disconnected to retain freshness until power is
applied for the first time

 Optional industrial temperature range of

-40°C to +85°C, designated IND

 JEDEC standard 28-pin DIP package
 New PowerCap Module (PCM) package

- Directly surface-mountable module

- Replaceable snap-on PowerCap provides

lithium backup battery

- Standardized pinout for all nonvolatile

SRAM products

- Detachment feature on PowerCap allows

easy removal using a regular screwdriver

PIN ASSIGNMENT

PIN DESCRIPTION

A0 - A14 - Address Inputs
DQ0 - DQ7 - Data In/Data Out

CE - Chip Enable
WE - Write Enable
OE - Output Enable

V

CC

- Power (+3.3V)
GND - Ground
NC - No Connect

DS1230W

3.3V 256k Nonvolatile SRAM

www.dalsemi.com

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2

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4

5
6

7
8

9
10

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27

28-Pin ENCAPSULATED PACKAGE

740-mil EXTENDED

A7

A5

A3
A2
A1
A0

DQ0
DQ1

GND

DQ2

V

CC

WE

A13A

8

A

9

A

11

OE

A

10
CE
DQ7
DQ6

DQ5

DQ3

DQ4

28

26
25

24
23

22
21

20
19

18
17

15

16

A12

A6

A4

A14

1

NC

2
3

NC
NC
NC

V

CC

WE

OE
CE

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

4
5
6
7
8
9
10
11
12
13
14
15
16
17

NC

A

14

33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

A13A

12

A11A

10

A9A

8

A7A6A

5

A

4

A

3

A2A

1

A

0

34

NC

GND

V

BAT

34-Pin POWERCAP MODULE (PCM)

(USES DS9034PC POWERCAP)

DS1230W

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DESCRIPTION

The DS1230W 3.3V 256k Nonvolatile SRAM is a 262,144-bit, fully static, nonvolatile SRAM organized
as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230W devices can be us ed in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230W
devices in the PowerCap Module package are directly surface mountable and are normally paired with a
DS9034PC PowerCap to form a complete Nonvolatile SRAM Module. There is no limit on the number of
write cycles that can be executed and no additional support circuitry is required for microprocessor
interfacing.

READ MODE

The DS1230W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs

(A0 – A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t

ACC

(Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.

WRITE MODE

The DS1230W executes a write cycle whenever the WE and CE signals are active (low) after addr ess
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE

will disable the outputs in t

ODW

from its falling edge.

DATA RETENTION MODE

The DS1230W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V

CC

without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As V

CC

falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external V

CC

to RAM and disconnects the lithium energy source. Normal

RAM operation can resume after VCC exceeds 3.0 volts.

FRESHNESS SEAL

Each DS1230W device is shipped from Dallas Semiconductor with its lithium energy source
disconnected, guaranteeing full energy capacity. When V

CC

is first applied at a level greater than 3.0

volts, the lithium energy source is enabled for battery back-up operation.

DS1230W

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PACKAGES

The DS1230W is available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM). The 28­pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1230W to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230W module base is reflow soldered, a DS9034PC PowerCap is snapped on top
of the base to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230W module bases and DS9034PC PowerCaps are ordered separately and shipped in
separate containers. See the DS9034PC data sheet for further information.

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +4.6V
Operating Temperature 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Power Supply Voltage V

CC

3.0 3.3 3.6 V

Logic 1 V

IH

2.2 V

CC

V

Logic 0 V

IL

0.0 0.4 V

DC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=3.3V ±=3.0V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current I

IL

-1.0 +1.0 V

I/O Leakage Current CE ≥ VIH ≤ V

CC

I

IO

-1.0 +1.0

µA

Output Current @ 2.2V I

OH

-1.0 mA

Output Current @ 0.4V I

OL

2.0 mA

Standby Current CE =2.2V

I

CCS1

50 250

µA

Standby Current CE =VCC-0.2V

I

CCS2

30 150

µA

Operating Current I

CCO1

50 mA

Write Protection Voltage V

TP

2.8 2.9 3.0 V

DS1230W

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CAPACITANCE (tA=25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C

IN

510pF

Input/Output Capacitance C

I/O

510pF

AC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=3.3V ±=3.0V)

DS1230W-150

PARAMETER SYMBOL MIN MAX TYPE UNITS NOTES

Read Cycle Time t

RC

150 ns

Access Time t

ACC

150 ns

OE to Output Valid t

OE

70 ns

CE to Output Valid t

CO

150 ns

OE or CE to Output Active t

COE

5ns5

Output High Z from Deselection t

OD

35 ns 5

Output Hold from Address Change t

OH

5ns

Write Cycle Time t

WC

150 ns

Write Pulse Width t

WP

100 ns 3

Address Setup Time t

AW

0ns

Write Recovery Time

t

WR1

t

WR2

5

20

ns
ns

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Output High Z from WE

t

ODW

35 ns 5

Output Active from WE

t

OEW

5ns5

Data Setup Time t

DS

60 ns 4

Data Hold Time t

DH1

t

DH2

0

20

ns
ns

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