Dallas Semiconductor DS1220AD-120, DS1220AD-100-IND, DS1220AD-100, DS1220AB-200-IND, DS1220AB-200 Datasheet
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FEATURES
§ 10 years minimum data retention in the
absence of external power
§ Data is automatically protected during power
loss
§ Directly replaces 2k x 8 volatile static RAM
or EEPROM
§ Unlimited write cycles
§ Low-power CMOS
§ JEDEC standard 24-pin DIP package
§ Read and write access times as fast as 100 ns
§ Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
§ Full ±10% V
CC
operating range (DS1220AD)
§ Optional ±5% VCC operating range
(DS1220AB)
§ Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10 - Address Inputs
DQ0-DQ7 - Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable
V
CC
- Power (+5V)
GND - Ground
DESCRIPTION
The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs
organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs
directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of
the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance.
There is no limit on the number of write cycles that can be executed and no additional support circuitry is
required for microprocessor interfacing.
DS1220AB/AD
16k Nonvolatile SRAM
www.maxim-ic.com
14
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
24
15
23
22
21
20
19
18
17
16
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
A6
A4
A8A
9
OE
A
10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
DS1220AB/AD
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READ MODE
The DS1220AB and DS1220AD execute a read cycle whenever WE (Write Enable) is inactive (high) and
CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11
address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within t
ACC
(Access Time) after the last address input signal is
stable, providing that the
CE and OE access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either t
CO
for CE or tOE for OE rather than address access.
WRITE MODE
The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low)
after address inputs are stable. The latter occurring falling edge of
CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of
CE or WE . All address inputs
must be kept valid throughout the write cycle.
WE must return to the high state for a minimum recovery
time (t
WR
) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (
CE and OE
active) then
WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1220AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5V. The DS1220AD provides full functional capability for V
CC
greater than 4.5 volts and write protects
by 4.25V. Data is maintained in the absence of V
CC
without any additional support circuitry. The
nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1220AB and 4.5 volts for the
DS1220AD.
FRESHNESS SEAL
Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level of greater than VTP, the lithium
energy source is enabled for battery backup operation.
DS1220AB/AD
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C; -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1220AB Power Supply Voltage V
CC
4.75 5.0 5.25 V
DS1220AD Power Supply Voltage V
CC
4.50 5.0 5.50 V
Logic 1 V
IH
2.2 V
CC
V
Logic 0 V
IL
0.0 +0.8 V
(TA: See Note 10)
(V
CC
=5V ± 5% for DS1220AB)
DC ELECTRICAL CHARACTERISTICS (V
CC
=5V ± 10% for DS1220AD)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current
I
IL
-1.0
+1.0
mA
I/O Leakage Current
CE ³ VIH £ V
CC
I
IO
-1.0
+1.0
mA
Output Current @ 2.4V I
OH
-1.0 mA
Output Current @ 0.4V I
OL
2.0 mA
Standby Current CE = 2.2V
I
CCS1
5.0 10.0 mA
Standby Current CE = VCC-0.5V
I
CCS2
3.0 5.0 mA
Operating Current
(Commercial)
I
CC01
75 mA
Operating Current
(Industrial)
I
CCO1
85 mA
Write Protection Voltage
(DS1220AB)
V
TP
4.5 4.62 4.75 V
Write Protection Voltage
(DS1220AD)
V
TP
4.25 4.37 4.5 V
CAPACITANCE (TA =25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
IN
510 pF
Input/Output Capacitance C
I/O
512 pF
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