Dallas Semiconductor DS1216H, DS1216F, DS1216E, DS1216D, DS1216C Datasheet

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FEATURES

§ Keeps track of hundredths of seconds,

seconds, minutes, hours, days, date of the month, months, and years

§ Converts standard 2k x 8 up to 512k x 8

CMOS static RAMs into nonvolatile memory

§ Embedded lithium energy cell maintains

watch information and retains RAM data

§ Watch function is transparent to RAM

operation

§ Month and year determine the number of days

in each month; leap-year compensation valid up to 2100

ORDERING INFORMATION

DS1216B, DS1216C, DS1216D, DS1216E, DS1216F, DS1216H (See Figure 2 for letter suffix

marking identification.)

DS1216

SmartWatch RAM DS1216B/C/D/H

SmartWatch ROM DS1216E/F

§ Lithium energy source is electrically

disconnected to retain freshness until power is applied for the first time

§ Proven gas-tight socket contacts

§ Full ±10% operating range

§ Operating temperature range: 0°C to +70°C

§ Accuracy is better than ±1 minute/month @

+25°C

RST 1 28 V

PIN DESCRIPTION

RST - RESET

DQ0 - Data Input/Output 0 [RAM] A2 - Address Bit 2 (Read/Write [ROM]) A0 - Address Bit 0 (Data Input [ROM]) GND - Ground

CE - Conditioned Chip Enable

OE - Output Enable

WE - Write Enable

Vcc - Switched V VCCB - Switched VCC for 24-Pin RAM V

D - Switched VCC for 28-Ppin RAM

PART RAM/ROM RAM DENSITY

DS1216B RAM 16k/64k No/Yes DS1216C RAM 64k/256k No DS1216D RAM 256k/1M No/Yes DS1216E ROM 64k/256k No

DS1216F ROM 64k/256k/1M No

DS1216H RAM 1M/4M No

for 28-/32-Pin RAM

DS1216B/C/D/E

28-Pin Intelli

PCB MODIFICATION REQUIRED

FOR DENSITY UPGRADE?

ent Socket

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RST

[A2] 10

[A0] 12 DQ0

GND

1 2 3 4

5 6 7 8 9

13 14 15 16

DS1216D/E/F/H

32-Pin Intelli

32 31 30 29 28 27 26 25

23 22 21 20 19 18 17

ent Socket

DS1216

TYPICAL OPERATING CIRCUIT

DESCRIPTION

The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600mil-wide DIP sockets with a built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source. The sockets provide an NV RAM solution for memory sized from 2k x 8 to 512k x 8 with package sizes from 26 pins to 32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to problems associated with memory volatility and uses a common energy source to maintain time and date. The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A key feature of the SmartWatch is that the watch function remains transparent to the RAM. The SmartWatch monitors V lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent loss of watch and RAM data.

Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM take up no more area than the memory alone. The SmartWatch uses the V for RAM and watch control. All other pins are passed straight through to the socket receptacle.

The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes, hours, days, date, months, and years. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either 24-hour or 12-hour format with an AM/PM indicator.

for an out-of-tolerance condition. When such a condition occurs, an internal

, data I/O 0, CE , OE , and WE

OPERATION

Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

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DS1216

After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match sequence.

PATTERN MATCH—RAM

Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control

of chip enable (

CE ), output enable ( OE ), and write enable ( WE). Initially, a read cycle to any memory

location using the

CE and OE control of the SmartWatch starts the pattern recognition sequence by

moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are

executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain access to the SmartWatch are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch

to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to

other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the SmartWatch.

PATTERN MATCH—ROM

Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above, until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on the level of /WRITE READ (A2).

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SMARTWATCH COMPARISON REGISTER DEFINITION Figure 1

HEX VALUE

BYTE 0

7 0 110001 01

DS1216

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

001110 10

101000 11

010111 00

110001 01

001110 10

101000 11

010111 00

Note: The pattern recognition in Hex is C5, 3A, 5C, C5, 3A, A3, 5C. The odds of this pattern accidentally duplicating and causing inadvertent entry to the SmartWatch are less than 1 in 1019. This pattern is sent to the SmartWatch LSB to MSB.

After power-up, the controller could be in the 64-bit clock register read/write sequence (from an incomplete access prior to power-down). Therefore, it is recommended that a 64-bit read be performed upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to the RAM would otherwise be expected.

NONVOLATILE CONTROLLER OPERATION

The DS1216 SmartWatch performs circuit functions required to make a CMOS RAM nonvolatile. First, a switch is provided to direct power from the battery or V

supply, depending on which voltage is greater.

This switch has a voltage drop of less than 0.2V. The second function that the SmartWatch provides is power-fail detection, which occurs at VTP. The DS1216 constantly monitors the VCC supply. When V

goes out of tolerance, a comparator outputs a power-fail signal to the chip-enable logic. The third function accomplishes write protection by holding the chip-enable signal to the memory within 0.2V of VCC or battery. During nominal power-supply conditions, the memory chip-enable signal will track the chipenable signal sent to the socket with a maximum propagation delay of 7ns for the 5V and 12ns for the

3.3V version.

FRESHNESS SEAL

Each DS1216 is shipped from Dallas Semiconductor with its lithium energy source disconnected, ensuring full energy capacity. When VCC is first applied at a level greater than the lithium energy source is enabled for battery-backup operation.

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