Dallas Semiconductor DS1210SN, DS1210S, DS1210N, DS1210 Datasheet

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FEATURES

 Converts CMOS RAMs into nonvolatile

memories

 Unconditionally write protects when VCC is

out of tolerance

 Automatically switches to battery when

power-fail occurs

 Space saving 8-pin DIP
 Consumes less than 100 nA of battery current
 Tests battery condition on power up
 Provides for redundant batteries
 Optional 5% or 10% power-fail detection
 Low forward voltage drop on the VCC switch
 Optional 16-pin SOIC surface mount package
 Optional industrial temperature range of

-40°C to +85°C

PIN ASSIGNMENT

PIN DESCRIPTION

V

CCO

- RAM Supply

V

BAT1

- + Battery 1
TOL - Power Supply Tolerance
GND - Ground

CE - Chip Enable Input
CEO - Chip Enable Output

V

BAT2

- + Battery 2
V

CCI

- + Supply
NC - No Connect

DESCRIPTION

The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of
converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance
condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and
the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a low­leakage CMOS process which affords precis e voltage detection at extremely low battery consumption.
The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the
DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation
can be achieved.

DS1210

Nonvolatile Controller Chip

www.dalsemi.com

VCCO

VBAT1

TOL

GND

123

4

VCCI
VBAT2
CEO
CE

8

7

6

5

DS1210 8-pin DIP (300-mil)

See Mech. Drawin

g

s Section

NC

VCCO

NC

VBAT1

NC

TOL

NC

GND

NC
VCCI
NC
VBAT2
NC
CEO
NC
CE

123

4
5
6
7
8

16
15
14
13
12
11
10

9

DS1210S 16-pin SOIC (300-mil)

See Mech. Drawings Section

DS1210

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OPERATION

The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM.
First, a switch is provided to direct power from the battery or the incoming supply (V

CCI

) depending on
which is greater. This switch has a voltage drop of less than 0.3V. The second function which the
nonvolatile controller provides is power-fail detection. The DS1210 constantly monitors the incoming
supply. When the supply goes out of tolerance a precision comparator detects power-fai l and inhibits chip

enable (CEO ). The third function of write protection is accomplished by holding the CEO output signal to
within 0.2 volts of the V

CCI

or battery supply. If CE input is low at the time power-fail detection occurs,

the CEO output is kept in its present state until CE is returned high. The delay of write protection until
the current memory cycle is completed prevents the corruption of data. Powe r-fail detect ion occurs in the
range of 4.75 volts to 4.5 volts with the tolerance Pin 3 grounded. If Pin 3 in connected to V

CCO

, then

power-fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions

CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210

performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is
powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than

2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by
performing a read cycle after power-up to any location in memory, verifying that memory location
content. A subsequent write cycle can then be executed to the same memory location altering the data. If
the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in
danger of being corrupted. The fifth function of the nonvolatile controller provides for battery
redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to
use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which
allows the connection of two batteries. During battery backup operation the battery with the highest
voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a
redundant battery is transparent to circuit operation and to the user. A battery status warnin g will occur
when the battery in use falls below 2.0 volts. A grounded V

BAT2

pin will not activate a battery-fail
warning. In applications where battery redundancy is not required, a single battery should be connected to
the BAT1 pin. The BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to
turn off the battery backup. This is to maintain the battery(s) at its highest capacity until the equipment is

powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and V

CCO

will be forced to VOL. When the batteries are first attached to one o r both of the V

BAT

pins, V

CCO

will not

provide battery back-up until V

CCI

exceeds V

CCTP

, as set by the T

OL

pin, and then falls below V

BAT

.

Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section
A shows the connections necessary to write protect the RAM when V

CC

is less than 4.75 volts and to back
up the supply with batteries. Section B shows the use of the DS1210 to halt the pro cessor when VCC is
less than 4.75 volts and to delay its restart on power-up to prevent spurious writes.