Dallas Semiconductor DS1100Z-75, DS1100Z-60, DS1100Z-500, DS1100Z-50, DS1100Z-45 Datasheet

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µ

DS1100

5-Tap Economy Timing

Element (Delay Line)

FEATURES

§ All-Silicon Timing Circuit

§ Five Taps Equally Spaced

§ 5V Operation

§ Delays are Stable and Precise

§ Both Leading- and Trailing-Edge Accuracy

§ Improved Replacement for DS1000

§ Low-Power CMOS

§ TTL/CMOS-Compatible

§ Vapor-Phase, IR, and Wave Solderable

§ Custom Delays Available

§ Fast-Turn Prototypes

§ Delays Specified Over Both Commercial and

Industrial Temperature Ranges

PIN ASSIGNMENT

IN

TAP 2

TAP 4

GND

1

2

3

4

DS1100M DIP (300mil)

DS1100Z SO (150mil)

DS1100U

8

7

6

5

SOP

V

CC

TAP 1

TAP 3

TAP 5

PIN DESCRIPTION

TAP 1 to TAP 5 - TAP Output Number
V

CC

GND - Ground
IN - Input

- +5V

DESCRIPTION

The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These
devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and
superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line
and industry-standard DIP and SO packaging. The DS1100 5-tap silicon delay line reproduces the input­logic state at the output after a fixed delay as specified by the extension of the part number after the dash.
The DS1100 is designed to reproduce both leading and trailing edges with equal precision. Each tap is
capable of driving up to ten 74LS loads.

Dallas Semiconductor can customize standard products to meet special needs.

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Figure 1. LOGIC DIAGRAM

Table 1. DS1100 PART NUMBER DELAY TABLE (All Values in ns)

PART

DS1100-XXX

-20 4 8 12 16 20

-25 5 10 15 20 25

-30 6 12 18 24 30

-35 7 14 21 28 35

-40 8 16 24 32 40

-45 9 18 27 36 45

-501020304050

-601224364860

-751530456075

-100 20 40 60 80 100

-125 25 50 75 100 125

-150 30 60 90 120 150

-175 35 70 105 140 175

-200 40 80 120 160 200

-250 50 100 150 200 250

-300 60 120 180 240 300

-500 100 200 300 400 500

TAP 1 TAP 2 TAP 3 TAP 4 TAP 5

NOMINAL DELAYS

DS1100

Figure 2. TIMING DIAGRAM: SILICON DELAY LINE

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