Dallas Semiconductor DS1077Z-66, DS1077Z-133, DS1077Z-125, DS1077Z-120, DS1077Z-100 Datasheet

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DS1077

EconOscillator/Divide

FEATURES

§ Processor-controlled or standalone solid-

state oscillator

§ Frequency changes on-the-fly

§ Dual low-jitter, synchronous fixed

frequency outputs

§ 2-wire serial interface

§ Frequency outputs 8.1kHz to 133MHz

§ ±0.5% variation over temp (+25°C to

+70°C)

§ ±0.5% initial tolerance

§ Nonvolatile (NV) frequency settings

§ Single 5V supply

§ No external components

§ Power-down mode

§ Synchronous output gating

STANDARD FREQUENCY OPTION

Note: x denotes package option
DS1077x-133 133.333MHz to 16.2kHz
DS1077x-125 125.000MHz to 15.2kHz
DS1077x-120 120.000MHz to 14.6kHz
DS1077x-100 100.000MHz to 12.2kHz
DS1077x-66 66.666MHz to 8.1kHz

PIN ASSIGNMENT

OUT1

OUT012

V

GN

V

3

D

CC

4

150mil SO

118mil µSOP Package

8

7

6

5

SCL

SDA

CTRL1

CTRL0

PIN DESCRIPTION

OUT1 - Main Oscillator Output
OUT0 - Reference Output
V

CC

- Power Supply Voltage
GND - Ground
CTRL1 - Control Pin for OUT1
CTRL0 - Control Pin for OUT0
SDA - 2-Wire Serial Data

Input/Output

SCL - 2-Wire Serial Clock

ORDERING INFORMATION

Note: XXX denotes frequency option
DS1077Z-XXX 8-Pin 150mil SO
DS1077U-XXX 8-Pin 118mil µSOP

DESCRIPTION

The DS1077 is a dual-output, programmable, fixed-frequency oscillator requiring no external
components for operation. The DS1077 can be used as a processor-controlled frequency synthesizer or
as a standalone oscillator. The two synchronous output operating frequencies are user-adjustable in
submultiples of the master frequency through the use of two on-chip programmable prescalers and a
divider. The specific output frequencies chosen are stored in NV (EEPROM) memory. The DS1077
defaults to these values upon power-up.

The DS1077 features a 2-wire serial interface that allows in-circuit on-the-fly programming of the
programmable prescalers (P0 & P1) and divider (N) with the desired values being stored in NV
(EEPROM) memory. Design changes can be accommodated in-circuit on-the-fly by simply
programming different values into the device (or reprogramming previously programmed devices).
Alternatively, for fixed frequency applications, previously programmed devices can be used and no
connection to the serial interface is required. Pre-programmed devices can be ordered in customer­requested frequencies.

The DS1077 is available in 8-pin SO or µSOP packages, allowing the generation of a clock signal
easily, economically, and using minimal board area. Chip-scale packaging is also available on request.

EconOscillator is a trademark of Dallas Semiconductor.

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BLOCK DIAGRAM 1077 Figure1

(

)

DS1077

DIV1

0M1

0M0

1M1

1M0

EN0

SEL0

PDN0

PDN1

CONTROL

REGISTERS

INTERNAL

OSCILLATOR

MCLK

P0 PRESCALER

(M DIVIDER)

0M00M1

P1 PRESCALER

M DIVIDER

MUX

SEL0

EN0

PDN0

Select

CONTROL

LOGIC

(TABLE 1)

Power-Down

DIV1

PROGRAMMABLE

“N” DIVIDER

CTRL0

Enable

OUT0

OUT1

2-WIRE

INTERFACE

1M01M1

Power-Down

PDN1

CONTROL

LOGIC

Enable

CTRL1

(TABLE 2)

SCLSDA

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DS1077

OVERVIEW

A block diagram of the DS1077 is shown in Figure 1. The DS1077 consists of four major components:

1) Internal Master Oscillator, 2) Prescalers, 3) Programmable Divider, and 4) Control Registers.

The internal oscillator is factory-trimmed to provide a master frequency (Master CLK) that can be routed
directly to the outputs (OUT0 & OUT1) or through separate prescalers (P0 & P1). OUT1 can also be
routed through an additional divider (N).

The Prescaler (P0) divides the Master Clock by 1, 2, 4, or 8 to be routed directly to the OUT0 pin.

The Prescaler (P1) divides the Master Clock by 1, 2, 4, or 8, which can be routed directly to the OUT1 pin
or to the Divider (N) input, which is then routed to the OUT1 pin.

The Programmable Divider (N) divides the Prescaler Output (P1) by any number selected between 2 and
1025 to provide the Main Output (OUT1) or it can be bypassed altogether by use of the DIV1 register bit.
The value of N is stored in the DIV register.

The Control Registers are user-programmable through a 2-wire serial interface to determine operating
frequency (values of P0, P1, & N) and modes of operation. The register values are stored in EEPROM
and therefore only need to be programmed to alter frequencies and operating modes.

PIN DESCRIPTIONS

Output 1 (OUT1)—This pin is the main oscillator output; its frequency is determined by the control
register settings for the prescaler P1 (mode bits 1M1 & 1M0) and divider N (DIV word).

Output 0 (OUT0)—A reference output, OUT0, is taken from the output of the reference select Mux. Its
frequency is determined by the control register settings for CTRL0 and values of Prescaler P0 (mode bits
0M1 & 0M0) (see Table 1).

Control Pin 0 (CTRL0)—A multifunctional input pin that can be selected as a MUX SELECT,
OUTPUT ENABLE and/or a POWER-DOWN. Its function is determined by the user-programmable
control register values EN0, SEL0, and PDN0 (see Table 1).

Control Pin 1 (CTRL1)—A multifunctional input pin that can be selected as a OUTPUT ENABLE
and/or a POWER-DOWN. Its function is determined by the user-programmable control register value of
PDN1 (see Table 2).

Serial Data Input/Output (SDA)—Input/Output pin for the 2-wire serial interface used for data transfer.

Serial Clock Input (SCL)—Input pin for the 2-wire serial interface used to synchronize data movement

on the serial interface.

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DEVICE MODE USING OUT0 Table 1

EN0

(BIT)

SEL0
(BIT)

PDN0

(BIT)

CTRL0

(PIN)

OUT0

(PIN)

CTRL0

FUNCTION

DS1077

DEVICE

MODE

1 HI-Z POWER-DOWN

000

0HI-Z

1MCLK/M

010

0MCLK
1HI-Z

100

0MCLK
1HI-Z

110

0MCLK/M
1 HI-Z POWER-DOWN

X01

0MCLK
1 HI-Z POWER-DOWN

X11

0MCLK/M

*This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.
**Default Condition

POWER-

DOWN*

MUX SELECT ACTIVE

OUTPUT
ENABLE

OUTPUT
ENABLE

POWER-

DOWN

POWER-

DOWN

ACTIVE

ACTIVE

ACTIVE**

ACTIVE

ACTIVE

DEVICE MODE USING OUT1 Table 2

PDN1
(BIT)

CTRL1

(PIN)

CTRL1

FUNCTION

OUT1 DEVICE MODE

0 0 OUTPUT ENABLE OUT CLK ACTIVE**

0 1 OUTPUT ENABLE HI-Z ACTIVE**

1 0 POWER-DOWN OUT CLK ACTIVE

1 1 POWER-DOWN HI-Z POWER-DOWN

**Default Condition

NOTE:

Both CTRL0 and CTRL1 can be configured as power-downs. They are internally “OR” connected so that
either of the control pins can be used to provide a power-down function for the whole device, subject to
appropriate settings of the PDN0 and PDN1 register bits (see Table 3).

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DS1077

SHUTDOWN CONTROL WITH PDN0 AND PDN1 Table 3

PDN0
(BIT)

0 0 NONE*
0 1 CTRL1
1 0 CTRL0
1 1 CTRL0 OR CTRL1

*CTRL0 performs a power-down if SEL0 and EN0 are both 0 (see Table 1).

PDN1

(BIT)

SHUTDOWN CONTROL

REGISTER FUNCTIONS

The user programmable registers can be programmed by the user to determine the mode of operation
(MUX), operating frequency (DIV), and bus settings (BUS). Details of how these registers are
programmed can be found in a later section; in this section the functions of the registers are described.
The register settings are nonvolatile, the values being stored automatically or as required in EEPROM
when the registers are programmed via the SDA and SCL pins.

MUX WORD

MSB LSB MSB LSB

Name * PDN1 PDN0 SEL0 EN0 0M1 0M0 1M1 1M0 DIV1 - - - - - -

Default
setting

*This bit must be set to zero.

00 0 1 10000 0xxxxxx

first data byte second data byte

DIV1 (bit)

This bit allows the output of the Prescaler P1 to be routed directly to the OUT1 pin (DIV1 = 1). The N
divider is bypassed so the programmed value of N is ignored. If DIV1 = 0 (default) the N divider
functions normally.

0M1, 0M0, 1M1, 1M0 (bits)

These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8 (see Table 4).

PRESCALER DIVISOR M SETTINGS Table 4

Prescaler

0M1 0M0

00

012012

104104

118118

**Default Condition

P0 Divisor

“M”

1**

1M1 1M0

00

Prescaler

P1 Divisor

“M”

1**

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DS1077

EN0 (bit) (Default EN0 = 1)

1) If EN0 = 1 and PDN0 = 0 the CTRL0 pin functions as an Output Enable for OUT0, the frequency of

the output being determined by the SEL0 bit.

2) If PDN0 = 1, the EN0 bit is ignored, CTRL0 will function as a power-down, and output OUT0 will

always be enabled on power-up, its frequency being determined by the SEL0 bit.

3) If EN0 = 0 the function of CTRL0 is determined by the SEL0 and PDN0 bits (see Table 1).

SEL0 (Default SEL0 = 1)

1) If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines the state of the MUX (i.e., the output

frequency of OUT0).

2) If CTRL0 = 0 the output will be the Master clock frequency.

3) If CTRL0 = 1 the output will be the output frequency of the M prescaler.

4) If either EN0 or PDN0 = 1 then SEL0 determines the frequency of OUT0 when it is enabled.

5) If SEL0 = 0 the output will be the Master clock frequency.

6) If SEL0 = 1 the output will be the output frequency of the M prescaler (see Table 1).

PDN0 (Default PDN0 = 0)

1) This bit (if set to 1) causes CTRL0 to perform a power-down function, regardless of the setting of the

other bits.

2) If PDN0 = 0 the function of CTRL0 is determined by the values of EN0 and SEL0.

NOTE:

When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case where all
the OUT0 circuitry is disabled even when the device is powered up for power to saving when OUT0 is
not used (see Table 1).

PDN1 (Default PDN1 = 0)

1) If PDN1 = 1, CTRL1 will function as a power-down.

2) If PDN1 = 0, CTRL1 functions as an output enable for OUT1 only (see Table 2.)

NOTE (ON OUTPUT ENABLE AND POWER-DOWN):

1) Both enables are “smart” and wait for the output to be low before going to Hi-Z.

2) Power-down sequence first disables both outputs before powering down the device.

3) On power-up the outputs are disabled until the clock has stabilized (~8000 cycles).

4) In power-down mode, the device cannot be programmed.

5) A power-down command must persist for at least two cycles of the lowest output frequency plus 10ms.

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DS1077

DIV WORD

MSB LSB MSB LSB

N9N8N7N6N5N4N3N2N1N0XXXXXX

first data byte second data byte

N

These ten bits determine the value of the programmable divider (N). The range of divisor values is from 2
to 1025, and is equal to the programmed value of N plus 2 (see Table 5).

PROGRAMMABLE DIVISOR N VALUES Table 5

BIT VALUE DIVISOR (N)

0 000 000 000** 2

0 000 000 001 3

--

--

--

--

1 111 111 111 1025

**Default Condition

BUS WORD

Name ----WCA2A1A0
Factory Default0*0*0*0* 0 0 0 0

*These bits are reserved and must be set to zero.

A0, A1, A2 (Default Setting = 000)

These are the device select bits that determine the address of the device.

WC (Default Setting WC = 0)

This bit determines when/if the EEPROM is written to after register contents have been changed.
If WC = 0 the EEPROM is written automatically after a write register command.
If WC = 1 the EEPROM is only written when the “WRITE ” command is issued.
Regardless of the value of the WC bit, the value of the BUS Register (A0, A1, A2) is always written
immediately to the EEPROM.

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