dallas semiconductor DS1075-IND service manual

DS1075-IND

EconOscillator/Divider

www.dalsemi.com

I/O

V

GND

OSCIN

2348765

1

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FEATURES

PIN ASSIGNMENT

§ Dual Fixed frequency outputs (30 kHz - 100

MHz)

§ User-programmable on-chip dividers (from 1

- 513)

§ User-programmable on-chip prescaler (1, 2,

4)

§ No external components

OUT0

OE
PDN/SELX

DS1075Z 150-mil SOIC

DS1075M-IND 300-mil DIP

§ ±0.5% initial tolerance

§ ±3% variation over temperature and voltage

§ Internal clock, external clock or crystal

reference options

§ Single 5V supply

§ Power-down mode

§ Synchronous output gating

FREQUENCY OPTIONS

Part No. Max O/P freq.
DS1075-100 IND 100.000
DS1075-80 IND 80.000
DS1075-66 IND 66.667
DS1075-60 IND 60.000

DESCRIPTION

The DS1075-IND EconOscillator/Divider is a fixed frequency oscillator requiring no external
components for operation. Numerous operating frequencies are possible in the range of approximately
30kHz to 100 MHz through the use of an on-chip programmable prescaler and divider.

The DS1075-IND features a master oscillator followed by a prescaler and then a programmable divider.
The prescaler and programmable divider are user-programmable with the desired values being stored in
non-volatile memory. This allows the user to buy an off the shelf component and program it on-site prior
to board production. Design changes can be accommodated on the fly by simply programming different
values into the device (or reprogramming previously programmed devices).

The DS1075-IND is shipped from the factory configured for half the maximum operating frequency.
Contact the factory for specially programmed devices. As alternatives to the on-board oscillator an
external clock signal or a crystal may be used as a reference. The choice of reference source (internal or
external) is user-selectable at the time of programming (or on the fly if the SEL mode is chosen).

The DS1075-IND features a dual-purpose Input/Output pin. If the device is powered up in Program
mode this pin can be used to input serial data to the on chip registers. After a Write command this data is
stored in non-volatile memory. When the chip is subsequently powered up in operating mode these
values are automatically restored to the on-chip registers and the Input/ Output pin becomes the oscillator
output.

The DS1075-IND is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal
easily, economically and using minimal board area.

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BLOCK DIAGRAM Figure 1

DS1075-IND

PART

NO.

SUFFIX

-100
080

-66

-60

INTOSC

FREQUENCY

100.000 MHz

80.000 MHz

66.667 MHz

60.000 MHz

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DS1075-IND

PIN DESCRIPTIONS

Input/Output Pin (IN/OUT): This pin is the main oscillator output, with a frequency determined by
clock reference, M and N dividers. Except in programming mode this pin is always an output and will be
referred to as “OUT.” In programming mode this pin will be referred to as “IN.”

External Oscillator Input (OSCIN): This pin can be used to supply an external reference frequency to
the device.

Crystal Oscillator Connection (XTAL): A crystal can be connected between this pin and OSCIN to
provide an alternative frequency reference. The crystal must be operated in fundamental mode. If a
crystal is not used this pin should be left open.

Output Enable Function (OE pin): The DS1075-IND also features a “synchronous” output enable.
When OE is at a high logic level the oscillator free runs. When this pin is taken low OUT is held low,
immediately if OUT is already low, or at its next high-to-low transition if OUT is high. This prevents any
possible truncation of the output pulse width when the enable is used. While the output is disabled the

master oscillator continues to run (producing an output at OUT0, if the EN0 bit = 0) but the internal
counters (/N) are reset. This results in a constant phase relationship between OE’s return to a high level
and the resulting OUT signal. When the enable is released OUT will make its first transition within one
to two clock periods of the master clock.

Power-Down/Select Function (PDN /SELX pin): The Power-Down/Select (PDN /SELX ) pin has a user-
selectable function determined by one bit (PDN bit) of the user-programmable memory. According to

which function is selected, this pin will be referred to as PDN or SELX .

If the Power-Down function is selected (PDN bit = 1) a low logic level on this pin can be used to make
the device stop oscillating (active low) and go into a reduced power consumption state. The “Enabling
Sequencer” circuitry will first disable OUT in the same way as when OE is used. Next OUT0 will be
disabled in a similar fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs
will go into a high impedance state. The power consumption in the power-down state is much less than if
OE is used because the internal oscillator (if used) is completely powered down. Even if an external
reference or a crystal is used all of the on-chip buffers are powered down to minimize current drain.
Consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a
power-down condition than if the OE is used.

If the Select function is chosen (PDN bit = 0) this pin can be used to switch between the internal
oscillator and an external reference (or crystal) on the fly. When this mode is chosen the E/I select bit is
overridden, a high logic level on SELX will select the internal oscillator, a low logic level will select the
external reference (or crystal oscillator).

Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the
reference select mux. This output is especially useful as a buffered output of a crystal defined master
frequency. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is

powered down. If this output is not required it can be permanently disabled by setting the EN0 bit to one,
and there will be a corresponding reduction in overall power consumption.

USER-PROGRAMMABLE REGISTERS

The following registers can be programmed by the user to determine operating frequency and mode of
operation. Details of how these registers are programmed can be found in a later section; in this section

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DS1075-IND

I

I

I

the function of the registers are described. The register settings are nonvolatile, the values being stored
automatically in EEPROM when the registers are programmed.

Note: The register bits cannot be used to make mode or frequency changes on the fly. Changes can only
be made by powering the device up in “Programming” mode. For them to be become effective the device
must then be powered down and powered up again in “Operation” mode.

For programming purposes the register bits are divided into two 9-bit words. The “MUX” word
determines mode of operation and prescaler values. The “DIV” word sets the value of the programmable
divider.

MUX WORD Figure 2

(MSB) (LSB)

0* 0* 0*

EN0

PDN M

MSEL

DIV1

E/

*These bits must be set to 0

E/

This bit selects either the internal oscillator or the external/ crystal reference.

1=External/Crystal
0=Internal Oscillator

However, if the PDN bit is set to 0 the E/I bit will be overridden by the logic level on the PDN /SELX
pin.

Table 1

PDN

BIT E/

0 X 0 EXTERNAL/CRYSTAL
0 X 1 INTERNAL
1 X 0 POWER-DOWN
1 0 1 INTERNAL
1 1 1 EXTERNAL/CRYSTAL

PDN /SELX

PIN

OSCILLATOR

MODE

DIV1

This bit allows the master clock to be routed directly to the output (DIV1=1). The N programmable
divider is bypassed so the programmed value of N is ignored. The frequency of the output (f

) will be

OUT

INTCLK or EXTCLK depending on which reference has been selected. If the internal clock is selected
the M prescaler is also bypassed (the bit values of MSEL and M are ignored), so in this case
f

=INTOSC (which also equals MCLK and INTCLK). If DIV1=0 the prescaler and programmable

OUT

divider function normally.

MSEL

This bit determines whether or not the M prescaler is bypassed. MSEL =1 will bypass the prescaler.

MSEL =0 will switch in the prescaler (unless overridden by DIV1=1), with a divide-by number

determined by the M bit.

M

This bit sets the divide-by number for the prescaler. M=0 results in divide-by-4, M=1 results in divide­by-2. The setting of this bit is irrelevant if either DIV1=1 or MSEL =1.

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DS1075-IND

I

Table 2

DIV1

BIT

E/

BIT*

MSEL

BIT

0 0 0 0 INTERNAL OSCILLATOR DIVIDED BY 4*N
0 0 0 1 INTERNAL OSCILLATOR DIVIDED BY 2*N
0 0 1 X INTERNAL OSCILLATOR DIVIDED BY N
0 1 X X EXTERNAL OSCILLATOR DIVIDED BY N
1 0 X X INTERNAL OSCILLATOR DIVIDED BY 1
1 1 X X EXTERNAL OSCILLATOR DIVIDED BY 1

*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN /SELX pin.

M

BIT

OPERATION

DIV WORD Figure 3

(MSB) (LSB)

N (9 BITS)

PDN

This bit is used to determine the function of the PDN /SELX pin. If PDN=0, the PDN /SELX pin can be
used to determine the timing reference (either the internal oscillator or an external reference/crystal). If

PDN=1, the PDN /SELX pin is used to put the device into power-down mode.

EN0

This bit is used to determine whether the OUT0 pin is active or not. If EN0 =1, OUT0 is disabled (High­impedance). If EN0=0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no

effect on OUT0, but OUT0 is disabled as part of the power-down sequence.

N

These 9 bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:

Table 3

BIT

VALUES

000000000 2
000000001 3

. .
. .
. .
. .
. .

111111111 513

DIVISOR (N)

VALUE

NOTE:

INTOSC/(M*N) must be greater than f
greater than f

. (If DIV1=1, then INTOSC or EXTCLK, as applicable, must exceed f

OUTmin

; if the external clock is selected, EXTCLK/N must be

OUTmin

OUTmin

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).

DS1075-IND

OPERATION OF OUTPUT ENABLE

Since the output enable, internal master oscillator and/or external master oscillator are likely all
asynchronous there is the possibility of timing difficulties in the application. To minimize these
difficulties the DS1075-IND features an “enabling sequencer” to produce predictable results when the
device is enabled and disabled. In particular the output gating is configured so that truncated output
pulses can never be produced.

ENABLE TIMING

The output enable function is produced by sampling the OE input with the output from the prescaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (tSU) from a transition on the OE input to the rising edge
of MCLK. If the actual setup time is less than t

then one more complete cycle of MCLK will be

SUEM

required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE.

FIGURE 4

DISABLE TIMING

If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If
OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE
and the rising edge of MCLK. If tSU < t
output before disabling occurs.

If the device is in divide-by-1 mode, the disabling occurs slightly differently. In this case if tSU > t
one additional output pulse will appear, if tSU < t

The following diagrams illustrate the timing in each of these cases.

the result will be one additional pulse appearing on the

SUEM

then two additional output pulses will appear.

SUEM

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SUEM