dallas semiconductor DS1045 service manual
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DS1045
4-Bit Dual Programmable Delay Line
FEATURES
All-silicon time delay
Two programmable outputs from a single
input produce output-to-output delays
between 9 and 84 ns depending on device
type
Programmable via four input pins
Programmable increments of 3 to 5 ns with a
minimum of 9 ns and a maximum of 84 ns
Output pulse is a reproduction of input pulse
after
Delay with both leading and trailing edge
accuracy
Standard 16-pin DIP or surface mount 16-pin
SOIC
Auto-insertable
Low-power CMOS design is TTL-compatible
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
Section
16
15
14
13
12
11
10
9
V
CC
EB
OUTB
B0
B1
B2
B3
OUTA
IN
1
V
2
CC
EA
3
4
A0
5
A1
6
A2
7
A3
GND
8
DS1045S 16-Pin SOIC (300-mil)
See Mech. Drawings
Section
16
15
14
13
12
11
10
V
CC
EB
OUTB
B0
B1
B2
B3
OUTA
9
IN
V
CC
EA
A0
A1
A2
A3
GND
DS1045 16-Pin DIP
See Mech. Drawings
PIN DESCRIPTION
IN - Delay Line Input
OUTA, OUTB - Delay Line Outputs
A0-A3 - Parallel Program Inputs
for OUT1
B0-B3 - Parallel Program Inputs
for OUT2
EA , EB - Enable A and B Inputs
V
CC
GND - Ground
- +5V Input
DESCRIPTION
The DS1045 is a programmable silicon delay line having one input and two 4-bit programmable delay
outputs. Each 4-bit programmable output offers the user 16 possible delay values to select from, starting
with a minimum inherent DS1045 delay of 9 ns and a maximum achievable delay in the standard DS1045
family of 84 ns. The standard DS1045 product line provides the user with three devices having uniform
delay increments of 3, 4, and 5 ns, depending on the device. Table 1 presents standard device family and
delay capability. Additionally, custom delay increments are available for special order through Dallas
Semiconductor.
The DS1045 is TTL and CMOS-compatible and capable of driving ten 74LS-type loads. The output
produced by the DS1045 is both rising and falling edge precise. The DS1045 programmable silicon
delay line has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is
offered in a standard 16-pin auto-insertable DIP and a space-saving surface mount 16-pin SOIC package.
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DS1045
PARALLEL PROGRAMMING
Parallel programming of the DS1045 is accomplished via the set of parallel inputs A0-A3 and B0-B3 as
shown in Figure 1. Parallel input A0-A3 and B0-B3 accept TTL levels and are used to set the delay
values of outputs OUTA and OUTB, respectively. Sixteen possible delay values between the minimum
9 ns delay and the maxi-mum delay of the DS1045-x device version can be selected using the parallel
programming inputs A0-A3 or B0-B3 (see Table 2, “Delay vs. Programmed Input”). For example, the
DS1045-3 outputs OUTA or OUTB and can be programmed to produce 16 possible d elays between the
9 ns (minimum) and the 54 ns (maximum) in 3 ns increment levels.
For applications that do not require frequent reprogramming, the parallel inputs can be set using fixed
logic levels, as would be produced by jumpers, DIP switches, or TTL levels as produced by computer
systems. Maximum flexibility in parallel programming can be achieved when inputs are set by computergenerated data. By using the enable input pins for each respective programmed output and observin g the
input setup (t
) and hold time (t
DSE
) requirements, data can be latched on an 8-bit bus. If the ena ble
DHE
pins, EA and EB , are not used to latch data, they should be set to a logic level 1. After each change in
the programmed delay value, a settling time (t
EDV
) or (t
) is required before the delayed output signal is
PDV
reliably produced. Since the DS1045 is a CMOS design, undefined input pins should be connected to
well defined logic levels and not left floating.
PART NUMBER TABLE Table 1
MAX DELAY
PART NUMBER STEP ZERO DELAY MAX DELAY TIME
TOLERANCE
DS1045-3
DS1045-4
DS1045-5
9 ±=1 ns
9 ±=1 ns
9 ±=1 ns
54 ns
69 ns
84 ns
±2.5 ns
±3.3 ns
±4.1 ns
NOTE:
Additional delay step times are available from Dallas Semiconductor by special order. Consult factory
for availability.
BLOCK DIAGRAM Figure 1
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