dallas semiconductor DS1020 service manual

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DS1020

Programmable 8-Bit

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FEATURES

 All-silicon time delay  Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns,

and 2 ns steps

 Programmable using 3-wire serial port or

8-bit parallel port

 Leading and trailing edge accuracy  Standard 16-pin DIP or 16-pin SOIC  Economical  Auto-insertable, low profile  Low-power CMOS  TTL/CMOS-compatible  Vapor phase, IR and wave solderable

Silicon Dela

PIN ASSIGNMENT

P2 P3 P4

3 4 5 6 7 8

Q/PO

GND

DS1020 16-pin DIP (300-mil) See Mech. Drawin

PIN DESCRIPTION

IN - Delay Input P0-P7 - Parallel Program Pins GND - Ground OUT - Delay Output V

S - Mode Select E- Enable C - Serial Port Clock Q - Serial Data Output D - Serial Data Input

16 15 14 13 12

s Section

- +5 Volts

OUT

P7 P6

Q/PO

P1 P2 P3 P4

GND

DS1020S 16-pin SOIC (300-mil)

See Mech. Drawin

Line

16 15 14 13 12

V OUT

P7 P6

s Section

1 2 3 4 5 6 7 89

DESCRIPTION

The DS1020 Programmable 8-Bit Silicon Delay Line consists of an 8-bit, user-programmable CMOS silicon integrated circuit. Delay values, programmed using either the 3-wire serial port or the 8-bit parallel port, can be varied over 256 equal steps. The fastest model (-15) offers a maximum delay of

48.25 ns with an incremental delay of 0.15 ns, while the slowest model (-200) has a maximum delay of 520 ns with an incremental delay of 2 ns. All models have an inherent (step-zero) delay of 10 ns. After the user-determined delay, the input logic state is reproduced at the output without inversion. The DS1020 is TTL- and CMOS-compatible, capable of driving 10 74LS-type loads, and features both rising and falling edge accuracy.

The all-CMOS DS1020 integrated circuit has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space-saving surface mount 16-pin SOIC.

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DS1020

PARALLEL MODE (S=1)

In the PARALLEL programming mode, the output of the DS1020 will reproduce the logic state of the input after a delay determined by the state of the eight program input pins P0 - P7. The parallel inputs can be programmed using DC levels or computer-generated data. For infrequent modification of the delay value, jumpers may be used to connect the input pins to VCC and ground. For applications requiring frequent timing adjustment, DIP switches should be used. The enable pin (E) must be at a logic 1 in hardwired implementations.

Maximum flexibility is obtained when the eight parallel programming bits are set using computergenerated data. When the data setup (t

) and data hold (t

DSE

) requirements are observed, the enable pin

DHE

can be used to latch data supplied on an 8-bit bus. Enable must be held at a logic 1 if it is not used to latch the data. After each change in delay value, a settling time (t

EDV

or t

) is required before input logic

PDV

levels are accurately delayed.

Since the DS1020 is a CMOS design, unused input pins (D and C) must be connected to well-defined logic levels; they must not be allowed to float.

SERIAL MODE (S = 0)

In the SERIAL programming mode, the output of the DS1020 will reproduce the logic state of the input after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup (t

) and data hold (t

DSC

the serial clock (C). The enable pin (E) must be at a logic 1 to load or read the internal 8-bit input register, during which time the delay is determined by the last value activated. Data transfer ends and the new delay value is activated when enable (E) returns to a logic 0. After each change, a settling time (t required before the delay is accurate.

) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of

DHC

EDV

) is

As timing values are shifted into the serial data input (D), the previous contents of the 8-bit input register are shifted out of the serial output pin (Q) in MSB-to-LSB order. By connecting the serial output of one DS1020 to the serial input of a second DS1020, multiple devices can be daisy-chained (cascaded) for programming purposes (Figure 3). The total number of serial bits must be eight times the number of units daisy-chained and each group of 8 bits must be sent in MSB-to-LSB order.

Applications can read the setting of the DS1020 delay line by connecting the serial output pin (Q) to the serial input (D) through a resistor with a value of 1k to 10k ohms (Figure 2). Since the read process is destructive, the resistor restores the value read and provides isolation when writing to the device. The resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a daisy-chain (Figure 3). For serial readout with automatic restoration through a resistor, the device used to write serial data must go to a high impedance state.

To initiate a serial read, enable (E) is taken to a logic 1 while serial clock (C) is at a logic 0. After a waiting time (t the serial clock (C), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time t

), bit 7 (MSB) appears on the serial output (Q). On the first rising (0 → 1) transition of

EQV

. To restore

CQV

the input register to its original state, this clocking process must be repeated 8 times. In the case of a daisy-chain, the process must be repeated 8 times per package. If the value read is restored before enable (E) is returned to logic 0, no settling time (t

) is required and the programmed delay remains

EDV

unchanged.

Since the DS1020 is a CMOS design, unused input pins (P1 - P7) must be connected to well-defined logic levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused.

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FUNCTIONAL BLOCK DIAGRAM Figure 1

DS1020

SERIAL READOUT Figure 2

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