Dallas Semiconductor DS10004Z-2-T-R, DS1004Z-5-T-R, DS1004Z-5, DS1004Z-4-T-R, DS1004Z-4 Datasheet
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FEATURES
All-silicon timing circuit
Five equally delayed clock phases per input
Precise tap-to-tap delay tolerances of ±0.5,
±0.75, or ±1 ns
Input-to-tap 1 delay of 5 ns
Delay tolerances of ±1.5 ns over temperature
and voltage
Leading and trailing edge precision preserves
the input symmetry
CMOS design with TTL compatibility
Standard 8-pin DIP and 150 mil 8-pin SOIC
Vapor phase, IR and wave solderable
Available in Tape and Reel
PIN ASSIGNMENT
PIN DESCRIPTION
TAP 1-5 - TAP Output Number
V
CC
- +5 Volt Supply
GND - Ground
IN - Input
DESCRIPTION
The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a
standard part family. The device is Dallas Semiconductor’s fastest 5-tap delay line. It is available in a
standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing ed ge
accuracies and has the inherent reliability of an all-silicon delay line solution.
The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum inputto-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns. See
Table 1 for details. Tolerance over temperature and voltage is ±1.5 ns. Nominal tap-to-tap tolerances
range from ±0.5 ns to ±1.0 ns. Each output is capable of driving up to 10 LS loads.
For customers needing non-standard delay values, the Late Package Program (LPP) is available.
Customers may contact Dallas Semiconductor at (972) 371–4348 for further details.
DS1004
5-Tap High Speed
Silicon Delay Line
www.dalsemi.com
IN
TAP 2
TAP 4
GND
V
CC
TAP 1
TAP 3
TAP 5
1
2
3
4
6
5
8
7
DS1004M 8-Pin DIP (300-mil)
See Mech. Drawings Sectio
n
IN
TAP 2
TAP 4
GND
V
CC
TAP 1
TAP 3
TAP 5
1
2
3
4
6
5
8
7
DS1004Z 8-Pin SOIC (150-mil)
See Mech. Drawings Sectio
n
DS1004
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PART NUMBER TOLERANCE TABLE Table 1
INPUT-TO-TAP TAP-TO-TAP
PART
NUMBER
TOLERANCE
NOMINAL
VARIATION
OVER TEMP
& VOLTAGE
INCREMENT TOLERANCE
NOMINAL
VARIATION
OVER TEMP
& VOLTAGE
DS1004M-2 5 ± 1.5 ns ±1.5 ns 2 ns ±0.5 ns ±0.75 ns
DS1004M-3 5 ± 1.5 ns ±1.5 ns 3 ns ±0.75 ns ±0.75 ns
DS1004M-4 5 ± 1.5 ns ±1.5 ns 4 ns ±1.0 ns ±0.75 ns
DS1004M-5 5 ± 1.5 ns ±1.5 ns 5 ns ±1.0 ns ±0.75 ns
DS1004Z-2 5 ± 1.5 ns ±1.5 ns 2 ns ±0.5 ns ±0.75 ns
DS1004Z-3 5 ± 1.5 ns ±1.5 ns 3 ns ±0.75 ns ±0.75 ns
DS1004Z-4 5 ± 1.5 ns ±1.5 ns 4 ns ±1.0 ns ±0.75 ns
DS1004Z-5 5 ± 1.5 ns ±1.5 ns 5 ns ±1.0 ns ±0.75 ns
NOTES:
1. Nominal conditions are +25°C and VCC = +5.0 volts.
2. Temperature and voltage variations cover the range from VCC=5.0 volts ±=5% and temperature range
from 0°C to +70°C.
3. Delay accuracy for both leading and trailing edges.
PART NUMBER DELAY TABLE Table 2
NOMINAL VALUES (FOR REFERENCE ONLY)
PART
NUMBER
INPUT-TO-TAP1 INPUT-TO-TAP2 INPUT-TO-TAP3 INPUT-TO-TAP4 INPUT-TO-TAP5
DS1004M-2 5 ns 7 ns 9 ns 11 ns 13 ns
DS1004M-3 5 ns 8 ns 11 ns 14 ns 17 ns
DS1004M-4 5 ns 9 ns 13 ns 17 ns 21 ns
DS1004M-5 5 ns 10 ns 15 ns 20 ns 25 ns
DS1004Z-2 5 ns 7 ns 9 ns 11 ns 13 ns
DS1004Z-3 5 ns 8 ns 11 ns 14 ns 17 ns
DS1004Z-4 5 ns 9 ns 13 ns 17 ns 21 ns
DS1004Z-5 5 ns 10 ns 15 ns 20 ns 25 ns
LOGIC DIAGRAM
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