Dallas Semiconductor DS1000-75, DS1000-60, DS1000-500, DS1000-50, DS1000-45 Datasheet
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www.dalsemi.com
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DS1000
5-Tap Silicon Delay Line
FEATURES
All-silicon time delay
5 taps equally spaced
Delays are stable and precise
Both leading and trailing edge accuracy
Delay tolerance ±5% or ±2 ns, whichever is
greater
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom delays available
Fast turn prototypes
Extended temperature range available
(DS1000-IND)
PIN ASSIGNMENT
IN
1
NC
2
NC
3
TAP 2
TAP 4
GND
NC
4
5
6
7
DS1000 14-Pin DIP (300-mil)
See Mech. Drawings Section
12
14
13
11
10
V
CC
NC
TAP 1
NC
TAP 3
NC
9
8
TAP 5
PIN DESCRIPTION
TAP 1-TAP 5 - TAP Output Number
V
CC
GND - Ground
NC - No Connection
IN - Input
- +5 Volts
TAP 2
TAP 4
GND
IN
1
2
3
4
V
8
CC
TAP 1
7
TAP 3
6
5
TAP 5
DS1000M 8-Pin DIP (300-mil)
See Mech. Drawings Sectio
TAP 2
TAP 4
GND
IN
1
2
3
4
8
V
CC
7
TAP 1
6
TAP 3
5
TAP 5
DS1000Z 8-Pin SOIC (150-mil)
See Mech. Drawings Sectio
DESCRIPTION
The DS1000 series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. These
devices are offered in a standard 14-pin DIP that is pin-compatible with hybrid delay lines. Alternatively,
8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superior
reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and
industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP
packages are available with hybrid lead configurations. The DS1000 series delay lines provid e a nominal
accuracy of ±5% or ±2 ns, whichever is greater. The DS1000 5-Tap Silicon Dela y Line reproduces the
input logic state at the output after a fixed delay as specified by the extension of the part number afte r the
dash. The DS1000 is designed to reproduce both leading and trailing edges with equal precision. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call 972-371-4348.
1 of 5 111799
DS1000
LOGIC DIAGRAM Figure 1
DS1000
PART NUMBER DELAY TABLE (all values in ns) Table 1
PART #
DS1000-
-100 20 2 1 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3
-125 25 2 1 50 2.5 1.5 75 3.8 2.3 100 5 3 125 6.3 3.8
-150 30 2 1 60 3 1.8 90 4.5 2.7 120 6 3.6 150 7.5 4.5
-175 35 2 1.1 70 3.5 2.1 105 5.3 3.2 140 7 4.2 175 8.8 5.3
-200 40 2 1.2 80 4 2.4 120 6 3.6 160 8 4.8 200 10 6
-250 50 2.5 1.5 100 5 3 150 7.5 4.5 200 10 6 250 12.5 7.5
-500 100 5 3 200 10 6 300 15 9 400 20 12 500 25 15
Nom
-2042 1 8 2 1122 1162 12021
-25 5 2 1 10 2 1 15 2 1 20 2 1 25 2 1
-30 6 2 1 12 2 1 18 2 1 24 2 1 30 2 1
-35 7 2 1 14 2 1 21 2 1 28 2 1 35 2 1.1
-40 8 2 1 16 2 1 24 2 1 32 2 1 40 2 1.2
-45 9 2 1 18 2 1 27 2 1 36 2 1.1 45 2.3 1.4
-50102 1 202 1302 14021.2502.51.5
-60122 1 242 13621.1482.41.56031.8
-75152 1 302 1452.31.46031.8753.82.3
TAP 1TAP 2TAP 3TAP 4TAP 5
TOLERANCE TOLERANCE TOLERANCE TOLERANCE TOLERANCE
Init Temp
Nom
Init Temp
Nom
Init Temp
Nom
Init Temp
Nom
Init Temp
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER SYM TEST
CONDITION
Supply Voltage V
High Level Input
V
CC
IH
Voltage
Low Level Input
V
IL
Voltage
Input Leakage
I
I
0.0V ≤ VI ≤ V
Current
Active Current I
CC
VCC=Max;
Period=Min.
High Level Output
Current
Low Level Output
Current
I
OH
I
OL
VCC=Min.
=4
V
OH
VCC=Min.
VOL=0.5
CC
MIN TYP MAX UNITS NOTES
4.75 5.00 5.25 V 6
2.2 VCC + 0.5 V 6
-0.5 0.8 V 6
-1.0 1.0 uA
35 75 mA 7, 9
-1 mA
12 mA
AC ELECTRI CAL CHARACT ERI STI CS (TA = 25°C; VCC = 5V ± 5%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Pulse Width t
Input to Tap Delay
t
PLH
WI
(leading edge)
Input to Tap Delay
t
PHL
(trailing edge)
Power-up Time t
PU
Input Period Period 4 (tWI)ns8
40% of Tap 5 t
PLH
ns 8
Table 1 ns 1, 2, 3, 4,
5, 10
Table 1 ns 1, 2, 3, 4,
5, 10
100 ms
2 of 5
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