OSD language-TXT Model : English,French,German,Italian,Spanish
-Non-TXT Model : English,French,German,Italian,Spanish, Russian
1
Safety Instruction
WARNING: Only competent service personnel may carry out work involving the testing or repair of
this equipment.
X-RAY RADIATION PRECAUTION
1. Excessive high voltage can produce potentially
hazardous X-RAY RADIATION.To avoid such
hazards, the high voltage must not exceed the
specified limit. The nominal value of the high
voltage of this receiver is 22-23at max beam
current. The high voltage must not, under any
circumstances, exceed 27.5 .
Each time a receiver requires servicing, the high
voltage should be checked. It is important to use
an accurate and reliable high voltage meter.
SAFETY PRECAUTION
1. Potentials of high voltage are present when this
receiver is operating. Operation of the receiver
outside the cabinet or with the back board
removed involves a shock hazard from the
receiver.
1) Servicing should not be attempted by anyone
who is not thoroughly familiar with the
precautions necessary when working on highvoltage equipment.
2) Discharge the high potential of the picture tube
before handling the tube. The picture tube is
highly evacuated and if broken, glass
fragments will be violently expelled.
2. The only source of X-RAY Radiation in this TV
receiver is the picture tube.For continued X-RAY
RADIATION protection,the replacement tube
must be exactly the same type tube as specified
in the parts list.
2. If any Fuse in this TV receiver is blown, replace it
with the FUSE specified in the Replacement
Parts List.
3. When replacing a high wattage resistor(oxide
metal film resistor)in circuit board, keep the
resistor 10mm away from circuit board.
4. Keep wires away from high voltage or high
temperature components.
5. This receiver must operate under AC230 volts,
50Hz. NEVER connect to DC supply or any other
power or frequency.
PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in this have
special safety-related characteristics. These
characteristics are often passed unnoticed by a
visual inspection and the X-RAY RADIATION
protection afforded by them cannot necessarily be
obtained by using replacement components rated
for higher voltage,wattage,etc. Replacement parts
which have these special safety characteristics are
identified in this manual and its supplements,
electrical components having such features are
identified by designated symbol on the parts list.
Before replacing any of these components, read the
parts list in this manual carefully. The use of
substitute replacement parts which do not have the
same safety characteristics as specified in the parts
list may create X-RAY Radiation.
3
Circuit block Diagram
4
Alignment Instructions
Remark: A service remocon(R-30SVC) is needed to align the set.
1. AFT
1.1 Standard B/G,D/K,I and L
1) Set a Signal Generator with
- RF FREQUENCY = 38.9 MHz,
- RF OUTPUT LEVEL = 80° 5 dBuV
- System = PAL / SECAM - B/G,
2) Connect the Signal Generator RF Output to P101 (Tuner IF Output).
There must be no signal input to the tuner.
3) Press the “AFT” KEY and wait until the TV screen display “AFT OK”.
1.2 Standard SECAM-L’ (France VHF-Low)
Above mentioned “1.1” adjustment has to be done in advance.
1) Set a Signal Generator with
- RF FREQUENCY = 34.2 MHz,
- RF OUTPUT LEVEL = 80° 5 dBuV
- System = SECAM - L’
2) Connect the Signal Generator RF Output to P101 (Tuner IF Output).
There must be no signal input to the tuner.
3) Press the “L’ AFT” KEY and wait until the TV screen display “L AFT OK”.
2. AGC
1) Set a Pattern Generator with RF LEVEL 63° 2 dBuV .
2) Connect a OSCILLOSCOPE PROBE to P101 (TUNER AGC INPUT).
3) Adjust AGC UP/DOWN KEY the voltage drop 1V dc over below its maximum voltage.
Alternative Method
1) Set a Pattern Generator with
- RF LEVEL 80° 5 dBuV
- PAL CROSSHATCH
( without SOUND CARRIER )
2) Connect a OSCILLOSCOPE
( Bandwidth 100MHz ) PROBE
to P101 (TUNER IF OUTPUT).
3) Use AGC UP/DOWN KEY to obtain
an envelop amplitude 200 + 50 mVp-p.
3. SCREEN
1) Apply a COLOR BAR pattern signal.
2) Set the CONTRAST, BRIGHTNESS Black level
to MAX, COLOR to MIN.
3) Set the R,G,B LEVEL to CENTER (31/63)
with R,G,B UP/DOWN KEY. 130° 5Vdc
4) Connect a OSCILLOSCOPE PROBE
to P906 ( CRT CATHOD R, G, B ).
5) Adjust the SCREEN VOLUME on FBT
such that the highest black level voltage, GND
130° 5Vdc.
5
4. WHITE BALANCE
1) Set the TV to NOR I mode.
2) Set the R,G,B LEVEL to CENTER with R,G,B UP/DOWN KEY .
3) Adjust the R,G,B UP/DOWN KEY of the other color which did not appear
on the screen to obtain WHITE.
5. FOCUS
1) Apply a RETMA PATTERN signal.
2) Adjust the FOCUS VOLUME on FBT to obtain optimal resolution.
6. GEOMETRY
6.1 VERTICAL CENTER
1) Set the TV to NOR I mode.
2) Pressing the V-SIZE UP/DOWN KEY, the
lower half of the screen is blanked.
3) Adjust the border line of blanked picture
coincident with the mechanical center marks
of the CRT using the V-SIZE UP/DOWN KEY.
6.2 VERTICAL SIZE
The VERTICAL CENTER adjustment
has to be done in advance.
1) Apply a RETMA PATTERN signal.
2) Set the TV to NOR I mode.
3) Adjust the upper part of the picture
with the V-SIZE UP/DOWN keys.
6.3 VERTICAL SLOPE
The VERTICAL SIZE adjustment
has to be done in advance.
1) Apply a RETMA PATTERN signal.
2) Adjust the lower part of the picture
with the V-SLOPE UP/DOWN keys.
6.4 VERTICAL S-CORRECTION
1) Apply a CROSSHATCH PATTERN signal.
2) Adjust the S-COR UP/DOWN KEY to obtain
the same distance between horizontal lines.
6.5 HORIZONTAL CENTER
1) Apply a RETMA PATTERN signal.
2) Adjust picture centering with CENTER
LEFT/RIGHT keys.
6
If EEPROM (I703) has been changed ;
- Option data has to be changed and
- all alignment function has to be readjusted .
Option
The TDA5255 contains a slicer for VPS and TTX, an accelerating acquisition hardware module, a display
generator for “LEVEL 1” TTX data and a 8 bit u-controller running at 333 nsec cycle time.
The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX
acquisition , transfers data to/from the external memory interface and receives/transmits data via I2C and
UART user interfaces.
The Slicer combined with dedicated hardware stores TTX data in a VBI 1Kbyte buffer.
The u-controller firmware does the total acquisition task ( hamming- and parity -checks,
page search and evaluation of header control bits) once per field.
(2) Feature
•
Acquisition:
- feature selection via special function register
- simultaneous reception of TTX and VPS
- fixed framing code for VPS and TTX
- programmable framing code window for TTX
- Acquisition during VBI
- direct access to VBI RAM buffer
- Acquisition of packets x/26, x/27, 8/30 (firmware)
- assistance of all relevant checks (firmware)
- 1-bit framing-code error tolerance (switchable)
•
. Display:
- features selectable via special function register
- 50/60 Hz display
- level 1 serial attribute display pages
- blanking and contrast reduction output
- 8 direct addressable display pages
- 12 x 10 character matrix
- 96 character ROM (standard G0 character set)
- 143 national option characters for 11 languages
- 288 characters for X/26 display
- 64 block mosaic graphic characters
- 32 free addressable characters for OSD in expanded character ROM + 32 inside OSD box
- double height (TOP/BOTTOM)
- conceal/reveal
- transparent foreground/background -inside/outside of a box
- cursor (colour changes from foreground to background colour)
- flash (flash rate 1s)
- programmable horizontal und vertical sync delay
- hardware assisted fast display page erase
- full screen background colour in outer screen
•
Synchronization:
display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with startstop-oscillator or
display synchronization to sandcastle or Horizontal Sync and Vertical Sync with external clock
independent clock systems for acquisition, display and controller
8
•
Controller:
- 8 bit configuration
- 18 MHz internal clock
- 0.33 us instruction cycle
- eight 16-bit data pointer registers (DPTR)
- two 16-bit timers
- watchdog timer
- serial interface (UART)
- 256 bytes on-chip RAM
- 1 Kbyte on-chip extended RAM (access via MOVX)
- 8 Kbyte on-chip ACQ-buffer-RAM (access via MOVX)
- 6 channel 8-bit pulse width modulation unit
- 2 channel 14-bit pulse width modulation unit
- 4 multiplexed ADC inputs with 8-bit resolution
- one 8-bit I/O port with open drain output and optional I2C emulation
- two 8-bit multifunctional I/O ports
- one 4-bit port working as digital or analog inputs
- one 2-bit I/O port with optional address latch enable function
•
P-SDIP 52 package
•
5 V supply voltage
(3) Block Diagram
9
DW370M* (Micro-controller for Non-Teletext Model)
=TMS370C08A05 ( TI Type No.)
=TMS370P08A05 (OTP device)
(1) General Description
The TMS370C08A05 devices are members of the cMCU370 family single-chip microcontrollers.
The cMCU370 family provides cost effective real-time system control through use of the PRISM methodology.
The PRISM methodology modular fabrication process integrates analog, digital, linear and power technologies on a
single chip, thereby maximizing the total integration strategy.
The TMS370C08A05 devices are designed with the high-performance 8-bit TMS370C8 CPU.
Features of the ‘C8 CPU and system module as implemented on this device include three CPU registers (stack
pointer, status register, and the program counter), two external interrupts, reset, memory mapped control registers.
(2) Feature
•
Internal Memory Configurations
- 16K-Byte ROM Program Memory
- 512-Byte RAM
•
Operating Features
- Supply Voltage (VCC) 5 V °10%
- Input Clock Frequency 2, 20MHz
- Industrial Temperature Range
•
Device Integrity Features
- Address Out-of-Range Reset
- Stack Overflow Reset
- Parallel Signature Analysis (CRC)
•
Two 16-Bit General Purpose Timer(T8A)
Each Includes:
- 16-Bit Resettable Counters with individual 8-Bit Prescaler
- 2 PWM Channels or
- 2 Input Captures or
- 1 Input Capture and 1 PWM Channel
•
One 14-Bit PWM Module
- 14-Bit Resettable Counters
- 14-Bit PWM Output Port
•
One 8-Bit PWM Module
- 8-Bit Resettable Counters
- 8-Bit PWM Output Port with 12V Open Drain
•
OSD Module
- Blanking/ Contrast reduction out
- Transparent Background
- Transparent Foreground
- Full Screen Background Color
- Controlled Color, Blink, Size, Smoothing, Fringe of Each lines of Character
- Two size of different Font 12x10 and 12x18 by Hard Masking
- OSD Window Display with 40x25 lines
•
8-Bit A/D Converter With 3 Inputs
- Single or Dual Channel Operation
- Single or Continuous Conversion Modes
•
Flexible Interrupt Handling
- Global and Individual Interrupt Masking
10
- 2 S/W Programmable Interrupt Levels
- 2 External Interrupt (1 Non-Maskable)
- Programmable Rising or Falling Edge Detect
•
09 CMOS Compatible I/O Pins
- All Peripheral Function Pins Software Configurable for Digital I/O
- 6 Bidirectionals, 3 Input Pins
•
Plastic 42 YSDP Pins Package
(3) Block Diagram
11
(4) Pin Description
* A : DW5255M*/DW5255RM*, B : DW370M*
PinNameSymbolDescription
A*B*A*B
11P3.1T1IC1/CRSYSSECAM-L’ OUT for switching SAW filter
L9461
- SECAM-L’ : H
- SECAM- L : L
22P0.7/Open DrainA0BUSSTOPI2C BUS STOP IN for Computer
controlled alignment in Factory
( Active Low )
33P0.6/Open DrainA1SDASerial data IN/OUT for I2C
44P0.5/Open DrainA2SCLSerial clock IN/OUT for I2C
55P0.4/Open DrainA3OPTION#5 #6 Teletext
66P0.3/Open DrainA4OPTIONH H West Teletext
L H East Teletext
H L Turkish Teletext
77P0.2/Open DrainA5OPTIONAuto search priority
H : L/L’ priority
L : B/G priority
88P0.1/Open DrainPWM1-0/ Open DrainOPTIONNot Used (Reserved)
99P0.0/Open DrainPWM1-1/ Open DrainLEDLED drive OUT
- Stand-by mode : H
- Operating mode : L
( IR reception : pulse )
1010VSSVSSground
1111VCCVCCPower Supply
1212XTAL1OSCINOSCINInput to inverting osc. Amplifier
1313XTAL2OSCOUTOSCOUTOutput of inverting osc. Amplifier
1414P4.0/ALEPWM1-2/Open DrainNot Used
1515RESETRESET/Open DrainRSTRESET IN (ACTIVE LOW)
1616P1.7/14BIT PWMPWM2-0VTTUNING VOLTAGE OUT
1717P1.6/14BIT PWMPWM2-1SWTV/AV &AM/FM SW.OUT for
STV8225
1818P1.5/8BIT PWMPWM1-3/Open DrainF/SWF/SW IDENT IN for stopping OSD
display in RGB mode
- H : TV /AV mode
- L : RGB mode
1919P1.4/8BIT PWMPWM1-4/Open DrainNot Used
2020P1.3/8BIT PWMPWM1-5/Open DrainMUTEAUDIO MUTE OUT
2121P1.2/8BIT PWMTESTGND(Must be tied 0V for DW370M*)
22P1.1/8BIT PWMNot Used
23P1.0/8BIT PWMNot Used
24VSSAVSSAAnalog GND for Slicer
25FIL3FIL3PLL Loop Filter I/O for Phase Shifting
12
PinNameSymbolDescription
A*B*A*B
26FIL2FIL2PLL Loop Filter I/O for TTX Slicing
27FIL1FIL1PLL Loop Filter I/O for VPS Slicing
28VCCAVCCAAnalog Supply for Slicer
29IREFIREFReference Current for Slicer PLLs
30CVBS CVBS CVBS IN
31P2.3/8 bit ADCNot Used
3222P2.2/8 bit ADCB0/AN0/ADCAGCIF AGC INPUT for Auto Tuning System
3323P2.1/8 bit ADCB1/AN1/ADCKSLocal KEY SCAN IN
3424P2.0/8 bit ADCB2/AN2/ADCS/SWS/SW IDENT IN for Automatic
switching between TV/AV mode
- H : AV / RGB mode
- L : TV mode
3525VSSVSS-OSDVSSGround
3626P3.3/INT1INT1IRREMOTE IR IN
3727VDDVCC-OSDVDDPower Supply
3828LCINOSCIN-OSDLCINCLOCK IN for OSD
3929LCOUTOSCOUT-OSDLCOUTCLOCK OUT for OSD
4030P3.7/TXT I/OT2EVT/PWM2BLBAND VHF-L OUT ( Active High )
4131P3.6/RXDT2IC2/PWM1BHBAND VHF-H OUT ( Active High )
4232P3.5/T1T2IC1/CRBUBAND UHF OUT ( Active High )
4333P3.4/T0T1EVT/PWM2POWERPOWER CONTROL OUT
4434P3.2/INT0INT2Not Used
4535HS/SCHSYNCHSYNCHOR. SYNC. IN(Active High)
4636P4.7/VSVSYNCVSYNCVERT. SYNC. IN (Active High)
4737RRRED OUT
4838GGGREEN OUT
4939BBBLUE OUT
5040BLANKBLBLANK OUT
5141CORCORNot Used
(CONTRAST REDUCTION OUT)
5242P3.0T1C2/PWM1EVEN/ODDEVEN/ODD OUT for non-interlacing
in TTX mode
13
CAT24C08P (E2PROM)
Vcc
Vgg
SDA
TEST
SEL
A0
A1
A2
D OUT
AKC
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
XDEC
64
2
START/STOP
LOGIC
CONTROL
LOGIC
DATE IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
EXTERNAL
(1) Typical Features
•
IC Bus compatible
•
Low power CMOS Technology
•
16 Byte page write Buffer
•
Self-Timed Write cycle with Auto-Clear
•
100,000 program/Erase cycles
•
100 Year Data Retention
•
Optional High Endurance Device Available
(2) Description
The CAT24C08P is a 8K bit serial CMOS E2PROM internally organized as 1024x8bits.
The CAT 24C08P features a 16 byte page write
buffer.
(3) Block Diagram
(4) Pin Description
PINSYMBOLDESCRIPTION
1-3A0, A1, A2Device Address lnputs
4VssGround
5SDASerial Data/Address
6SCLSerial Clock
7TESTConnect to Vss
8Vcc+5V Power supply
14
TDA8374A (Single chip TV Processor for Negative modulation IF )
TDA8374 (Single chip TV Processor for Negative & positive modulation IF)
(1) General Description
The TDA8374(A) is I2C-bus controlled single chip TV processors which are intended to be applied in PAL/NTSC
television receiver.
The IC is mounted in a S-DIL 56 envelope.
(2) Feature
•
IF
- Vision IF amplifier with high sensitivity and good figures for differential phase and gain
- PLL demodulator with high linearity offering the possibility for (single standard) intercarrier stereo audio application .
- Alignment PLL via I2C
- [TDA8374] Multistandard IF with negative and positive modulation, switchable via I2C
•
AUDIO
- Alignment free multi standard PLL audio demodulator (4.5 to 6.5 MHz.)
- Mono volume control
•
Video
- Integrated luminance delay line
- Integrated chroma trap and bandpass filters (auto calibrated)
- Asymmetrical peaking circuit in the luminance channel
- Black stretching of non standard CVBS or luminance signals
•
Colour
- SECAM interface for application with SECAM add-on TDA8395.
•
RGB
- RGB control (brightness, contrast, saturation)
- Black current stabilization and white point adjustment
•
Input / Output
- Flexible video source select with CVBS input for the internal signal and two external video inputs(one switchable for
CVBS or Y/C).
- The output signal of the video source select is externally available ( also as CVBS when Y/C input is used).
- External audio input.
- Linear RGB input with fast blanking.
•
Synchronization and Deflection
- Horizontal synchronization with two control loops and alignment free horizontal oscillator.
- Slow start and slow stop of the horizontal drive output to enable low stress start-up and switch-off from the line circuit
at nominal line supply voltage.
- Vertical count-down circuit for stable behavior with provisions for non-standard signals.
- Vertical geometry control.
- Vertical drive optimized for DC coupled vertical output stages.
•
Control
- Full I2C bus control, as well for customer controls as for factory alignment.
- All automatic controls have an option for forced mode.
•
Power consumption
- Low power consumption (900 mW at 8.0 Volts).
•
Packaging
- SDIL-56 (Shrinked Dual In Line, 56 pins).
15
(3) Block Diagram
16
(4) Pin Description
NoNameDescription
1SOUND IF INPUTThe sound equivalent input impedance is 8k5 ohm // 5pF which has to be
taken into account for proper termination of the ceramic filters.
The DC impedance is very high.
The minimum input signal for catching is l mV rms.
2EXT AUDIO INPUTAn external sound signal (500mVrms) for example from SCART can be
applied to this pin via a coupling capacitor.
The input impedance is 25kohm.
3VCO REF FILTERThe IF VCO tuned circuit is applied to these pin.
4Its resonance frequency must be two times the IF-frequency and in between a
range of 64-120MHz.
This range is suitable for the IF standards as 33.4, 38.9, 45.75 and 58.75MHz.
The VCO frequency can be adjusted by I2C bus so a fixed coil can be used.
5PLL LOOP FILTERThe PLL loopfilter is a first order filter with R=390 ohm and C = 100nF in
series to ground.
The loopfilter bandwidth is 60kHz and is optimal for both fast catching and
sufficient video suppression for optimal sound performance.
Sound performance can theoretically be improved by adding a small
capacitor (approx.0- 4.7nF) between pin 5 and ground.
This however must be evaluated further because the normal video signal
response should not be effected.
6IF VIDEO OUTPUTAlthough the video output impedance is low it is recommended to avoid
high frequency current in the output due to for instance sound trap filters.
This can be achieved by means of an emitter follower at the video output with
a 1resistor in series with the base.
7BUS INPUT : SCLSerial clock line
8BUS INPUT : SDASerial data line
9BANDGAP The bandgap circuit provides a very stable and temperature independent
DECOUPLINGreference voltage.
This reference voltage (6.7V) ensures optimal performance of the TDA8374
and is used in almost all functional circuit blocks.
10CHROMA INPUTThe supplied C S-VHS input burst amplitude should be nominally 300mVpp
(assumed is a colour bar signal with 75% saturation and with chroma/burst
ratio of 2.2/1 ). The C S-VHS input is internally clamped to 4V via 50 .
The external AC coupling capacitor with 50forms a high pass filter.
A recommended coupling capacitor is 1 nF; the high pass filter cut off
frequency is then approximately 3KHz.
11Y/CVBS INPUTThe Y S-VHS signal of 1Vpp ( inclusive sync amplitude) is AC coupled to pin11.
12MAINThe TDA8374 has a main supply pin 12 and a horizontal supply pin 37. Both
37POSITIVE SUPPLYpins have to be supplied simultaneously.
Notice that the IC has not been designed to use this pin 37 as start pin.
(pin 37 supplies the horizontal oscillator, PHI-1 and PHl-2)
(pin 12 supplies the rest of the circuits in the IC)
The nominal supply voltage is 8V. With min/max values of 7.2-8.8V.
Also in stand-by condition the IC must be supplied with 8V.
17
NoNameDescription
A voltage detection circuit is connected to both pins.
- pin12 if V12 <6.8V than a power on reset, POR, is generated. The Hout
output is disabled immediate.
- pin37 if V37 <5.8V than the horizontal output is disabled immediate.
13INT CVBS INPUTIt is recommended that the CVBS1 int and CVBS2 ext input amplitudes are
17EXT CVBS INPUT1 Vpp (inclusive sync amplitude).
This, because the noise detector switches the 1 loop to slow mode
(i.e. auto 1mode when FOA, FOB = 0,0) when noise level exceeds
100mVrms (i.e. at S/N of 20dB).
14GROUNDAll internal circuits are connected to this ground pin 14.
15AUDIO OUTPUTThe output signal is volume controlled and is active for both internal and
external audio signals. The nominal gain is +9dB and -71dB, which gives
a total control range of 80dB.
The output signal range therefor is 0.14- 1400mVrms
The bandwidth is >100kHz, the DC level is 3.3V and the output impedance
is 250 .
16DECOUPLING Voltage variations at pin 16, which can be due to external leakage current or
FILTER TUNINGcrosstalk from interference sources, should be less than 50mV to ensure that
tuning of filters/delay cells remains correct.
18BLACK CURRENT For correct operation of the loop CURRENT information is supplied to the
INPUTblack current input pin.
19BLUE OUTPUT The RGB outputs are supplied to the video output stages from pins 21, 20
20GREEN OUTPUTand 19 respectively.
21RED OUTPUTFor nominal signals (i.e. CVBS/S-VHS, -(R-Y)/- (R-Y), TXT inputs) and for
nominal control settings, then the RGB output Signal amplitudes is
typically 2VBLACK_WHITE.
22V-GUARD INPUT/Vertical Guard
BEAM CURRENT With this function, the correct working of the vertical deflection can be
LIMITERmonitored. If the vertical deflection fails, the RGB outputs are blanked to
prevent damage to the picture tube.
Beam current limitinq
The beam current limiting function is realised by reducing the contrast (and
finally the brightness) when the beam current reaches s too high level. The
circuit falls apart in two functions:
- Average beam current limiting (ABL): reacting on the average content of
the picture
- Peak white limiting (PWL): reacting on high local peaks in the RGB signal.
23RED INPUTThe Rin, Gin, Bin input signals (nominal signal amplitude of 700mV) are
24GREEN INPUTAC coupled to pin 23, 24 and 25 respectively.
25BLUE INPUTClamping action occurs during burstkey period.
26RGB INSERTIONThe table below a survey is given of the three modes which can be selected
SWITCH INPUTwith a voltage on RGB insertion switch input pin ;
Vpin26 I2C function Selected RGB signal
0.9V-3V IE1=0 RGB(internal)
IE1=1 Rin,Gin,Bin
(fast insertion on pin23,24,25)
> 4V IE1=X OSD can be inserted at the RGBout pins
27LUMINANCE INPUTAn nominal input signal amplitude of 1 Vblack-white MUST be DC coupled
18
NoNameDescription
to the luminance input pin 27.
The pin is internally AC coupled to the luminance clamp via a capacitor of
50pF; clamping action occurs during burstkey period.
28LUMINANCE The luminance output signal is approximately l V black-white with typical
OUTPUToutput impedance of 25O ohm.
29B-Y OUTPUTThe maximum output impedance of pins 29 and 30 is 500when PAL/NTSC
30R-Y OUTPUTsignals are identified. When SECAM is identified by the SECAM add-on and
no PAL/NTSC is already identified by the ASM, then the ASM sets the
-(B-Y)/-(R-Y) output switch open (via DEMSW).
This enables the -(B-Y)/-(R-Y) outputs of the TDA8395 to be directly connected
to pins 29 and 3O respectively.
31B-Y INPUTThe -(B-Y),-(R-Y) output signals (supplied from baseband delay line) are AC
32R-Y INPUTcoupled, via a coupling capacitor of 10nF or greater, to the -(B-Y)/-(R-Y) inputs;
both inputs are clamped during burstkey period.
33SECAM REFThe SECAM reference output is directly connected to pin l of the TDA8395 for
OUTPUTSECAM decoding ; it also can be used as a reference for comb filter applications.
- sync calibration internal circuits,
it is only allowed to have 3.6MHz Xtals on pin34: both 4.4MHz,3.6MHz Xtals
are allowed on pin 35.
If pin 35 is not used: then it is left open in application (also XA,XB=O,1 ).
36LOOP FILTER One of the important aspects of the PLL is the 1oop filter connected to pin 36;
BURST PHASEit influences the dynamic performance of the loop.
DETECTOR
38CVBS OUTPUTThe output amplitude is 1Vpp (transfer gain ratio between CVBS1int or
CVBS2ext or CVBS3ext/Ys-vhs and CVBSout is 1).
The maximum output impedance is 250 ohm.
39BLACK PEAKFor the correct working of the black stretcher an external time constant should
HOLD CAPACITORbe added at the black peak hold capacitor input.
40HOR OUTPUTThis open collector output is meant to drive the horizontal output stage.
The output is active low, i.e. the line transistor should conduct during the low
period of the output.
41SANDCASTLE Pin 41 is a combined input/output pin.
OUTPUT/The pin provides a three level sandcastle pulse.
FLYBACK INPUTBoth burstkey pulse and vertical blanking pulse are always available, the line
blanking pulse is only present when the external flyback pulse is fed to this pin.
The line flyback pulse, fed to this pin is used for two functions:
- input signal for the PHI-2 1oop and
- RGB line blanking. (without flyback pulse blanking occurs only during the
burstkey pulse)
To ensure correct working of the delay line and SECAM add-on, the output
should not be loaded with more than:
- Sandcastle input delay line TDA 4665
- Sandcastle input SECAM add-on TDA 8395
42PHI-2 FILTER /The loopfilter is a first order filter.
FLASH PROTECTThis pin requires a capacitor (C) only.
19
NoNameDescription
A flash protection becomes active when this pin is forced >6V. The horizontal
drive is switched-off immediately.
Once the voltage is <6V the horizontal drive is switched-on again via the slow
start procedure.
43PHI-1 FILTERThe loopfilter connected to pin 43 is suitable for various signal conditions as
strong/weak and VCR signal.
This is achieved by switching of the loopfilter time constant by changing the
PHI-1 output current.
Via I2C bus FOA/B, different time constants can be chosen, including an
automatic mode which gives optimal performance under varying conditions.
44GROUNDTo this pin are connected the IC-substrate and horizontal output.
45EAST-WEST DRIVEnot used
46VERT DRIVE +The vertical drive has a current output. The output is balanced which ensures
47VERT DRIVE -a good common mode behavior with temperature and makes the output signal
less sensitive for disturbances.
48IF INPUTThe PLL frequency range is 32-60MHz with corresponding VCO frequency
4964-120MHz.
The IF input impedances is 2in parallel with 3pF and matches the required
load for commonly used SAW filters.
A DC coupling is allowed, so no series capacitors between SAW filter and IF
input are necessary.
50EHT/OVERVOLTAGEnot used
PROTECT INPUT
51VERTThis pin requires a capacitor to ground of l00nF +,- 5%.
SAWTOOTH The optimal sawtooth amplitude is 3.5V and is determined by the external
CAPACITORcapacitor and charge current.
The sawtooth bottom-level is 2V.
52REFERENCEThis pin requires a resistor to ground.
CURRENT INPUTThe optimal reference current is 100 . which is determined by this resistor.
53AGC The AGC capacitor value is 2.2and has been defined for an optimal
DECOUPLINGcompromise between AGC speed and tilt for all AGC modes
CAPACITOR(negative/positive modulation).
54TUNER AGCThis output is used to control (reduce) the tuner gain for strong RF signals.
OUTPUTThe tuner AGC is an open collector output which is acting as a variable
current source to ground.
55AUDIO Only a capacitor has to be connected to this pin that defines the deemphasis
DEEMPHASSIStime constant.
The signal is internally connected through to the Audio switch.
The deemphasis output is fixed, thus not controlled by the volume, and can be
used for SCART.
56DECOUPLINGThis pin requires a capacitor of 10connected to ground.
SOUND The pin acts as a low pass filter needed for the DC feedback loop.
DEMODULATOR
20
TDA4665(Base Band Delay Line)
(1) Features
• Two comb filters, using the switched-capacitor technique,for one line delay time (64µs)
• Adjustment free application
• No crosstalk between SECAM colour carriers
• Handles negative or positive colour-difference input signals
• Clamping of AC-coupled input signals(±(R-Y)and±(B-Y))
• VCO without external components
• 3MHz internal clock signal derived from a 6MHz VCO, line-locked by the sandcastle pulse (64µs line)
• Sample-and -hold circuits and low-pass filters to suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour
(2) General Description
The TDA4661 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders
with colour-difference signal outputs±(R-Y)and±(B-Y).
(3)Block Diagram
(4) Pin Description
SYMBOL PINDESCRIPTION
Vp21+5V supply voltage for digital part
n.c.2not connected
GND23ground for digital part (0V)
i.c.4internally connected
SAND5sandcastle pulse input
n.c.6not connected
i.c.7internally connected
i.c.8internally connected
SYMBOL PINDESCRIPTION
Vp19+5V supply voltage for analog part
GND110ground for analog part (0V)
V0 (R-Y)11±(R-Y) output signal
V0 (B-Y)12± (B-Y) output signal
n.c.13not connected
V1 (B-Y)14± (B-Y) input signal
n.c.15not connected
1 (R-Y)16±(R-Y) input signal
V
21
TDA8395 (Secam Decoder)
(1) Features
Fully integrated filters
Alignment free
For use with baseband delay
(2) Description
The TDA8395 is a self-calibrating,fully integrated SECAM decoder. The IC should preferably be used
in conjunction with the PAL/NTSC decoder TDA8362 and with the switch capacitor baseband delay
circuit TDA4665. The IC incorporates HF and LF filters, a demodulator and an identification circuit
(Iuminance is not processed in this IC).
A highly stable reference frequency is required for calibration and a two-level sandcastle pulse for
blanking and burst gating.
(3) Block Diagram
refPLLrefGND
CLOCHE
100 nF
78362
220 nF
TEST
V
p
BANDGAPTUNINGTUNING
CVBS
16
ACC
INTERFACE
115
ref/IDENT
f
CLOCHE
FILTER
CONTROL
SAND
PLL
IDENT-
IFICATION
(4) Pin Description
SYMBOLPINDESCRIPTION
fp1/IDENT1reference frequency input/identification input
TEST2test output
Vp3positive supply voltage
n.c.4not connected
n.c.5not connected
GND6ground
CLOCHEref7Cloche reference filter
PLL ref8PLL reference
The TDA6106Q is a monolithic video output amplifier (5MHz bandwidth) in a SIL 9 MPpackage, using high-voltage
DMOS technology, and is intended to drive the cathode of CRT directly .
To obtain maximum performance, the amplifier should be used with black-current control.
(2) Feature
•
Black - current measurement output for automatic black current stabilization (ABS)
•
Single supply voltage of 200V
•
Internal protection against positive appearing CRT flash-over discharge
6.8V above AV/FM B C
11ext inexternal sound input
12Vccsupply voltage (+9V)
13mean capmean capacitor
24
TDA8356 (DC-coupled vertical deflection circuit)
(1) General Description
The TDA8356 is power circuit for use in 90 and 110 color deflection systems for field frequencies of 50 to 120 Hz.
The circuit provides a DC driven vertical deflection output circuit, operating as a high efficient class G system.
(2) Feature
•
High efficient fully DC-coupled vertical output bridge circuit
•
Vertical fly-back switch
•
Guard circuit
•
Protection against : - short circuit of the output pins (7 and 4)
- short circuit of the output pins to Vp
•
Temperature (thermal) protection
•
High EMC immunity because of common mode inputs
(3) Block Diagram
(4) Pin Description
PINSYMBOLDESCRIPTION
1I drive (pos)input power stage (positive); include Ii(sb) signal bias
2I drive (neg)input power stage (negative); include Ii(sb) signal bias
3V poperating supply voltage
4V o(b)output voltage B
5GNDground
6V fbinput fly-back supply voltage
7V o(a)output voltage A
8V o(guard)guard output voltage
9V I(fb)input feedback voltage
25
TDA7056 (BTL AUDIO OUTPUT AMPLIFIER)
(1) Features
• No external components
• No switch-on/off clicks
• Good overall stability
• Low power consumption
• Short circuit proof
• ESD protected on all pins
(2) General Description
The TDA7056 is a mono output amplifier contained in a 9 pin medium power package.
The device is designed for batteryfed portable mono recorders, radios and television.
The STR-S5707 is a Hybrid IC with a built in power transistor and a separate excitation control IC,
designed for converter type switching mode power supply applications.
The IC is capable of quasi-resonant mode and requires small number of external component.
(2) Feature
•
Small SIP isolated package : Resin sealed type (transfer mold)
•
Lower power dissipation at a lighter load
•
Many protection function : - Pulse-by-pulse over current protection
- Over-voltage protection with a latch
- Thermal protection with a latch
•
These protection functions are incorporated and can be latched with an external signal.
(3) Block Diagram
(4) Pin Description
PINNAMESYMBOLDESCRIPTION
1CollectorCCollector of power Tr
2GroundGNDground (Emitter of power Tr)
3BaseBBase of power Tr
4SinkSINKBase current (IS) input
5Over-current OCPover-current sensing signal input
protection
6InhibitINHinput for synchronizing OFF time
Latchand latch circuit operation
7SensingSENSconstant voltage control signal input
8DriveDRIVEBase drive current (ID) output
9VinVINsupply voltage for control circuit
27
Electrical Characteristics of Control Part (Ta=25 )
DescriptionTerminalSymbolRatingUnit
MINTYPMAX
On-state Voltage9-2V
Off-state Voltage9-2V
Operating Circuit Current9-2I
Stand-by Circuit Current9-2I
On TimeT
Off TimeT
OCP terminal Threshold Voltage6-2V
INH terminal Threshold Voltage 18-2V
INH terminal Threshold Voltage 2 8-2V
INH terminal Threshold Voltage 38-2V
OVP Operating Voltage9-2V
Latch Circuit Sustaining Current9-2I
Latch Circuit Cancellation Voltage9-2V
MIC Thermal ShutdownTj
IN(ON)
IN(OFF)
IN(ON)
IN(OFF)
ON
OFF
OCP
INH-1
INH-2
Latch
IN(OVP)
H
IN(La.OFF)
(TSD)
7.6 88.4V
4.64.95.2V
1528mA
200A
3341
4555
-1.12-1-0.88V
0.650.750.85V
1.42..0V
3.25.15.8V
9.210.7V
500A
2.53.1V
125150
Starting Temp
Fixed Reference Voltage7-2V
S
32.0V
Temperature Coefficient of7-2+2.5mV/
Reference Voltage
Electrical Characteristics of Power Transistor Part(Trl) (Ta=25 )
DescriptionTerminalSymbolRatingUnit
MINTYPMAX
Collector Saturation Voltage1-2V
Collector Cutoff Current1-2I
Base-Emitter saturation voltage3-2V
DC Current Gainh
TDA8138 (5.1V+12V regulator with Disable and Reset)
(1) General Description
The TDA8138 is a monolithic dual positive voltage regulator designed to provide fixed precision output voltages of
5.1V and 12V at currents up to 1A.
A internal reset cuicuit generates a reset pulse when the output 1 decrease below the regulated voltage value.
Output 2 can be disabled by TTL input.
Shot circuit and themal protections are included.
(2) Feature
•
output currents up to 1A
• f
ixed precision Output 1 voltage 5.1V 2%
•
fixed precision Output 2 voltage 12V 2%
•
output 1 with Reset facility
•
output 2 with Disable by TTL input
•
short circuit protection at both outputs
•
thermal protection
•
low drop output voltage
(3) Block Diagram (4) Pin Description
PINSYMBOLDESCRIPTION
1V in 1input 1
2V in 2input 2
3C eDelay capacitor
4V disdisable
5GNDground
6RSTreset
7n.c
8V out 2output 2 (12V)
9V out 1output 1 (5.1V)
29
GMS301 12-R098 (4-bit Single Chip Microcomputer for Remote control)
(1) General Description
The GMS30112-R098 is 4-bit single chip CMOS microcomputer.
(2) Feature
•
program memory : 1024 bytes
•
data memory : 32 x 4 bits
•
43 types of instruction set
•
3 levels of subroutine nesting
•
1 bit output port for a large current (REMOUT signal)
•
operating frequency : 300kHz - 1 MHz
•
instruction cycle : 12.5 usec @ 480kHz
•
CMOS process ( single 3.0 V power supply )
•
stop mode (through internal instruction)
•
released stop mode by key input (masked option)
•
built in capacitor for ceramic oscillation circuit (masked option)
•
built in a watch dog timer(WDT)
•
low operating voltage (2.0 V to 4.0 V)
(3) Block Diagram
30
(4) Pin Description
PINSYMBOLDESCRIPTION
1,2,3,4K0,K1,K2,K34 bit input port with built in pull up resistor
5,6,7,8,9,10D0,D1,D2,D3,D4,D510 bit output port which can be set or reset pin
by pin independently.
The output structure is N-channel open drain.
11REMOUTremote control signal output port which has
high current driving capability
12OSC 2oscillator output
13OSC 1oscillator input
14Vdd2-4V power supply
15RESETreset signal input which is a low active
16GNDground
17,18,19,20R0,R1,R2,R34 bit programmable I/O port
31
Circuit Description
Vision IF amplifier, AFC, video demodulator
The IF signal from the tuner is fed through a SAW filter to the differential IF input (pin 48 and 49).
The first IF stage consists of 3 AC-coupled amplifiers with a total gain control range of over 66 dB.
The reference carrier for the video demodulator is obtained by a PLL carrier regenerator
(eliminating notch filter compromises, as in reference tuned circuits for passive carrier regeneration).
Only an oscillator coil is needed( pin 3 and 4) that can be aligned via l2C-bus to the double IF frequency.
The AFC information is derived from the VCO control voltage of the IF-PLL
and can be read via I2C-bus.
Bit AFB toggles when the picture carrier is exactly at the desired IF frequency (= half the aligned IF-PLL frequency).
AFA is active in a window around this point.
For fast search-tuning applications this window can be increased by a factor 3 (AFW bit).
Tuner A.G.C.
The automatic gain control (A.G.C.) circuit operates on top sync level at negative modulated signals
or on peak white level at positive modulation, selected by MOD bit.
The tuner A.G.C. is controlled via pin 54.
The tuner A.G.C. take over point (T.O.P.) can be set over a wide range: 0.8 mVrms .. 80 mVrms
IF input signal amplitude.
The tuner AGC output may have to operate above Vcc of TDA8374.
Therefore pin 54 is an open collector output, that can operate from 0.3 up to Vcc+ 1 Volt
(at > 2 mA sink current)
PLL sound demodulator
The IF-video output at pin 6 (2Vpp) is fed through a sound bandpass filter and connected to the intercarrier sound IF
input pin 1.
An alignment free PLL tunes itself to the sound carrier and demodulates it.
The non volume-controlled front-end audio signal can be obtained from the deemphasis pin 55 (amplitude 300 mVeff).
Source select switch
TDA8374 input switch can select one of the following sources ;
pin 13 front-end : CVBS l int
pin17 : CVBS 2 ext
pin 11.pinlO : Y s-vhs, C s-vhs
Selected signal is available at the CVBS output pin 38, in case of Y/C input Y+C are added.
It drive teletext and the TDA8395 SECAM add-on.
For S-VHS applications, the Y,C input can be selected, independent of the CVBS source switch.
TDA8374 Y,C inputs are selected, while the source switch outputs CVBS l int or CVBS 2 ext on CVBS out.
Horizontal synchronization and protection
The synchronization separator adapts its slicing level in the middle between top-sync and black level of the CVBS signal.
The separated synchronization pulses are fed to the first phase detector and to the coincidence detector.
The -1 loop gain is determined by the components at pin 43 (C+RC).
The coincidence detector detects whether the horizontal line oscillator is synchronized to the incoming video.
The line oscillator is a VCO-type, running at twice the line frequency.
It is calibrated with the X-tal oscillator frequency of the colour decoder and has a maximum deviation of 2% of the
nominal frequency, so no alignment is-needed.
Calibration is done at start up( the TDA8374 must first know what colour X-tals are connected, bits XA and XB) and
after synchronization loss ( -1 coincidence detector “Sync Locked” bit SL).
The second phase detector -2 locks the phase of the horizontal driver pulses at output pin 40 to the horizontal
flyback pulse at input pin 41 .
32
This compensates for the storage time of the horizontal deflection transistor.
The - 2 loop filter (C) is externally connected to pin 42.
The horizontal phase can be given a static off set via I2C-but (HSH “horizontal shift”)
A dynamic correction is possible by current feedback into the - 2 loop filter capacitor.
To protect the horizontal deflection transistor, the ho rizontal drive is switched off immediately when a power
failure ( “ Power-On Reset “ bit POR ) is detected.
The power failure may have corrupted the contents of the internal data registers, so the TDA8374 should be
started up again.
The TDA8374 has a separate supply input (pin 37) that only used as a clean supply voltage for the horizontal
oscillator circuits.
V ertical synchronization
The vertical sawtooth generator drives the vertical output.
It uses an external capacitor at pin 51 and a current reference resistor at pin 52.
The TDA8374 vertical drive has differential current outputs for DC-coupled vertical output stage, like the TDA8356 .
At TDA8356 input pins l and 2 this current is converted into a drive voltage via a resistor.
Geometry processing
With the TDA8374 is possible to implement automatic geometry alignment, because all parameters are adjusted
via the I2C bus.
The deflection processor of the TDA8374 offers the fo11owing five controls;
- Horizontal shift
- Vertical slope.
- Vertical amplitude
- Vertical S-correction
- vertical shift
Colour decoder
The colour decoder contains an alignment-free X-tal oscillator, a dual killer circuit and colour difference demodulators.
Together with the TDA8395 SECAM add-on a multi standard PAL/SECAM/NTSC decoder can be built with
automatic recognition.
Which standard can be decoded depends on the external Xtals used.
Two Xtal pins (34and 36) are present so normally no external switching is required.
The I.C. must be told which X-tals are connected (bits XA and XB).
This is important, because the X-tal frequency of the colour decoder is also used to calibrate many internal circuit.
The burst phase detector locks the Xtal oscillator with the chroma burst signal.
The phase detector operates during the burst key period only, to prevent disturbance of the PLL by the chroma signal.
Two gain modes provide:
- Good catching range when the PLL is not Locked.
- Low ripple voltage and good noise immunity once the PLL has locked
The killer circuit switches-off the R-Y and B-Y demodulators at very low input signal conditions (chroma burst amplitude).
A hysteresis prevents on/off switching at low, noisy signals.
Color standardpin34pin35XAXB
PAL4.43/SECAM + NTSC-4.43none4.4310
PAL4.43/SECAM + NTSC-M3.584.4311
33
Integrated video filters
The TDA8374 has alignment-free internal luminance delay, chroma bandpass and chroma trap.
They are implemented as gyrator circuits tuned by tracking to the frequency of the chroma Xtal oscillator.
The chroma trap in the Y signal path is by-passed when Y/C input is selected (S-VHS ).
For SECAM an extra luminance delay is build-in, for correct delay of the luminance signal.
RGB output and black current stabilization
The colour difference signals (R-Y, B-Y) are matrixed with the luminance signal (Y) to obtain the RGBout output
signals (pins 21,20,29).
In the TDA8374 the matrix type automatically adapts to the decoded standard (NTSC,PAL) .
Linear amplifiers are used to interface external RGBrn signals (pins 24,25,26) from the SCART connector.
These signals overrule the internal RGB signals when the data insertion pin 26 (FBI) is switched to a level between
1.0V and 3.0V.
The contrast and brightness control and the peak white limiter operate on both internal and external RGB signals
R,G and B each have their own, independent gain control to compensate for the difference in phosphor efficiencies
of the picture tube: so called “white point” adjustment.
The nominal amplitude is about 2V black to white, at nominal input signals and control settings.
TDA8374 has a black current stabilization loop, that automatically adjust the black level to the cut-off voltage of the
picture tubes three gun cathodes.
Since no current is flowing when the voltage the cathode is equal to the cut-off voltage of the tube, the loop stabilizes
at a very small gun current.
This “black current” of the three guns is measured internally and compared with a reference current, to adjust the
black level of RGBout.
The black level loop is active during 4 lines at the end of the vertical blanking.
In the first line the leakage current is measured (max. acceptable 100 A).
In the next three lines the black levels of the three guns are adjusted.
The nominal value of the ‘black current is 10 A.
The ratio of the ‘black currents’ for the 3 guns tracks automatically with the white point adjustment, so the
back-ground colour is the same as the adjusted white point.
At switch-on of the TV receiver the black current stabilization circuit is not yet active and RGBout are blanked.
Before the first measurement pulses appear, O.5 sec delay ensures that the vertical deflection is active, so the pulses
will not be visible on the screen.
During the measuring lines RGBout will supply 4V pulses to the video output stages.
The TDA8374 waits until the black current feedback input (pin 18) exceeds 200 A, which indicates that the picture tube
is warm-up.
Then the black current stabilization circuit is active.
After a waiting time of about 1.0 sec, the blanking of RGBout is released.
Tuning
The AFC information of the TDA8374 is not available as an analogue voltage.
Automatic following (=frequency tracking, AFC) can be done via the I2C-bus by software.
The TDA8374 AFC window is typically 80 kHz wide.
This value is made higher than the 62.5 kHz tuning step, to prevent an automatic following loop from continuously
adapting the tuning frequency..
With this AFC window ( 40 kHz) the maximum tuning error is less than 62.5 kHz.
For high speed search-tuning-algorithms, the AFC window can be widened to 240 kHz via bit AFW.
34
TDA8395 SECAM decoder
The TDA8395 is an alignment-free SECAM colour decoder, including a Cloche filter, demodulator and line
identification circuit.
The Cloche filter is a gyrator-capacitor type.
Its frequency is calibrated in the vertical retrace period.
The calibration reference( pin 1 ) is obtained from the TDA8374 color X-tal oscillator (pin 33).
Pin 7 is a decoupling for the Cloche reference.
The voltage change at this pin due to leakage currents should be lower than 10 mV, during field scan, resulting in a
capacitor of minimal 100 nF.
Pin 8 is the reference capacitor for the PLL.
The voltage variation during field scan at this pin should be lower than 2 mV , resulting in a capacitor of 220 nF.
The sandcastle input (pin 15) is connected to TDA8374 pin 41 and is used for generation of the blanking periods and
provides clock information for the identification circuit.
The CVBS source select output (TDA8374 pin 38) supplies SECAM chroma to pin 16 of the TDA8395.
This is demodulated by a PLL demodulator, that uses the reference frequency at pin l and a bandgap reference to
obtain the desired demodulation characteristic.
If the digital line identification in theTDA8395 detects SECAM, pin 1 will sink a current of 150 (A out of TDA8374
SECAMref pin 33.
When the TDA8374 has not detected PAL or NTSC, it will respond by increasing the voltage at pin 33 from 1.5V to 5V.
Now the TDA8374 color difference outputs pin 30 and 29 are made high-ohmic and the TDA8395 output pin 9 and 10
are switched on.
These outputs will be disconnected and high-ohmic when no SECAM is detected for two frame periods, the decoder
will be initialized before trying again.
SECAM-L and -L ’ application
For SECAM-L and L’ the TDA8374 has to be switched to positive modulation via I2C-bus bit MOD.
SECAM-L’ signals only occur in VHF band l and have their picture and sound carrier interchanged, compared to
SECAM-L/PAL channels.
For SECAM-L’ the IF picture carrier is situated at 34.2 MHz and the AM-sound carrier at 40.7MHz.
Therefore the IF-PLL reference has to be tuned away from 38.9 to 34.2 MHz.
This can be done via I2C-bus sub-address 15hex (IF-PLL).
The AM sound output is inserted at TDA8374 external audio input pin via the SCART plug.
When bit MOD selects positive modulation for SECAM-L/L’, the TDA8374 automatically switches to external audio.
Base band delay line TDA4665
TDA4665 is an integrated double baseband delay line of 64 S.
It couples to the TDA8374 and TDA8395 without any switches or alignments.
The TDA4665 consist of two main blocks:
- Two delay lines of 64 sec in switched capacitor technique
- Internal clock generation of 3 MHz, line locked to the sandcastle pulse
The TDA4665 operates according to the mode demanded by the colour transmission standard:
- For PAL it operates as geometric adder to satisfy the PAL demodulation requirements
- In NTSC mode it reduces cross-colour interference (comb-filtering)
- For SECAM it repeats the colour difference signal on consecutive horizontal scan lines.
A sandcastle pulse is connected to pin 5.
The top pulse voltage (should not exceed 5 V) can be directly coupled to the 5 V sandcastle output of the TDA8374.
35
The R-Y and B-Y colour difference signals (from TDA8374 pins 30 and 29) are AC-coupled and clamped by the
input stages at pins 16 and 14.
An internal 6 MHz Current controlled oscillator is line locked via a PLL to the sandcastle pulse at pin 5.
This clock drives the delay lines to obtain the required 64 sec.
Sample and hold low pass filters supress the clock signal.
The original and the delayed signals are added, buffered and fed to the output pins 11 and 12.
These are AC-coupled to the R-Y and B-Y colour difference input pin 32 and 31 of TDA8374.
The TDA4665 needs a 5 V supply voltage on pin l for the digital part and on pin 9 for the analog part.
TDA8356 vertical deflection.
The TDA8356 is a vertical deflection circuit.
It can be used in 90 deflection systems with frame frequencies from 50 up to 120 Hz
With its bridge configuration the deflection output can be DC coupled with few external components.
Only a supply voltage for the scan and a second supply for the flyback are needed.
The TDA8356 can drive max.2A.
The vertical drive currents of TDA8374 pins 47 and 46 are connected to input pins l and 2 of the TDA8356.
The currents are converted into a voltage by a resistor between pins 1 and 2.
Pin2 is on a fixed DC level (internal bias voltage) and on pin l the drive voltage can be measured (typical 1.8 Vpp).
The drive voltage is amplified by ‘A’ and fed to two amplifiers ‘B’ and ‘C’, one is inverting and the other is a non
inverting amplifier.
The outputs (pins 4 and 7) are connected to the series connection of the vertical deflection coil and feedback resistor .
The voltage across feed back resistor is fed via pin 9 to correction amplifier ‘D’, to obtain a deflection current which is
proportional to the drive voltage.
The supply voltage for the TDA8356 is 16V at pin 3.
The flyback generator has a separate supply voltage of 45V on pin 6.
The guard pulse is useful to synchronize OSD.
Horizontal deflection
The circuit contains horizontal drive, line output transformer.
The horizontal driver pulses from the TDA8374 are amplified in the horizontal drive circuit, to get sufficient base-drive
current for the high voltage switching transistor Q401.
During the horizontal scan period( =52 s) Q401 will conduct, and a sawtooth current flows from +110/123V through the
primary winding of the FBT to ground.
After this time Q401 is switched off and the energy stored in the FBT during the scan period will be transformed to the
flyback capacitor C410.
This energy transfer will take place in a cosine shape because the primary of the FBT and C410 from a resonant circuit.
The time the energy is transferred from FBT to C410 and back to the FBT, is called the flyback time and will take place
in about 12 s.
The flyback peak voltage is about 8 times the scan voltage.
In series with the horizontal deflection coil there is a (damped) linearity corrector coi1.
During the scan there is some loss in the resistance of the deflection coi1.
In the first part of a line the linearity corrector stores some energy in a permanent magnet until it is saturated.
This improves the linearity of the horizontal scan speed.
The required S correction for the picture tube can be adjusted with the value of C411.
The beam current limiting information (BeamCurr) is derived from the foot of the H.V winding of the FBT.
36
This is connected via resistor to +8V.
As the beam current increase, the voltage on line BeamCurr decreases.
BeamCurr is damped by a integration filter before it is fed back to TDA8374 pin 22.
The TDA8374 will decrease the contrast (and eventually the brightness) to limit the average beam current.
Video amplifiers
Three TDA6106Q integrated video amplifiers drive cathode of the picture tube directly.
They are protected against CRT flashover discharges and ESD (electro static discharge).
The three video amplifiers, have a beam current output I black, used by the TDA8374 black current loop to control
the black level on the cathodes.
The outputs can be connected together because the black current 1oop sequentially controls the black level for each
cathode.
The amplification of the TDA6106Q is set by the resistors between pin 3 and 9 and between pin 3 (negative-input) and
the TDA8374 output.
There are no alignment any more on the CPT panel, because of the automatic black current stabilization and because
the white point adjustment can be done in the TDA8374 via I2C bus.
Power Supply STR-S5707
(1) VIN terminal, start-up circuit
A start-up circuit is to start and stop a operation of a control IC by detecting a voltage appearing at a VIN terminal
(pin-9).
At start up of a power supply, when a voltage at the VIN terminal reaches to 8V (typical) by charging up C807 by
the function of a start-up resistor, R803, a control circuit starts operating by the function of the start-up circuit.
After the control circuit starts its operation, power source is obtained by smoothing voltage appearing at winding of
pin6-7 of T801.
(2) Oscillator, F/B terminal voltage (Pin 7)
A oscillator generates pulse signals which turns a power transistor on and off by making use of charge and discharge
of C1 and C2 incorporated in the Hybrid IC.
Constant voltage control of a switch-mode power supply is performed by changing both ON-time and OFF-time except
when the load is light (ex. remote control stand-by mode of TVs).
The ON-time is controlled by changing a current charged by C1, which is as the result of that the detection winding of
pin5-7 of T801, which detects a change of voltage in a secondary side, connected to the sensing terminal (Pin 7) has the
current in accordance with an output signal from an output voltage detection circuit (an error amplifier) built in.
As an AC input voltage to the power supply gets the higher and a load current the smaller, the current flowing to the
SENS terminal gets the larger, and the ON-time gets the shorter.
(3) Function of INH terminal (Pin 6), control of OFF-time
Signal to the INH terminal is used as inputs to COMP.1 and COMP.2 inside of the control IC.
A threshold voltage of COMP.1, VTH1 is set at 0.75V (Ta=25°) and an input signal to a drive circuit becomes almost
0V (the power transistor is in OFF mode) when a voltage at the INH terminal reaches the VTH1.
A threshold voltage of COMP.2, VTH2, is set at 1.5V (Ta=25°).
When the INH terminal voltage reaches VTH2, an output from COMP.2 reverses (the power transistor is in on mode).
Quasi-resonant operation
By inputting the voltage of winding of pin6-7 of T801 which is synchronized with the energy discharge time of a
secondary winding, pin14(or 15)-16 of T801, to the INH terminal through D805 and R809, quasi-resonant operation
can be achieved.
37
When the power transistor turns off and a voltage higher than VTH2 is applied to the INH terminal, C3 immediately
discharges and then starts charging again.
Even after the discharge of energy of a secondary winding is completed, VINH does not immediately increases.
When it gets lower than VTH1, the transistor turns on.
Stand-By Mode
While being in remote control stand-by mode, the output voltage is kept on providing to the secondary side and
the power transistor operates at A class mode.
By connecting INH terminal (Pin 6) to the GND, the OFF-time of the power transistor is fixed at set time
( T OFF = 50usec at Ta = 25 ) of the built-in oscillator, and only ON-time changes depending on input and output
conditions of the power supply.
Therefore, it enables to hold an oscillation frequency in light mode below 20KHz (typical).
(4) Drive circuit
The STR-S5707 applies the proportional drive system in order to minimize turn-on and saturation loss, and storage time.
(5) OCP (over-current protection) function
Over-current protection is performed pulse by pulse by directly detecting collector current of the power transistor.
Detecting voltage is set to -1V below a reference point of GND (ground).
(6) Latch circuit
It is a circuit which sustains an output from the oscillator low and stops operation of the power supply when over-voltage
protection (OVP) circuit and thermal shutdown (TSD) circuit are in operation.
As the sustaining current of the latch circuit is 500 A maximum when VIN terminal voltage is 4V, the power supply
circuit sustains the off state as long as current of 500 A minimum flows to VIN terminal from a start-up resistor.
In order to prevent a malfunction to be caused by a noise and so on, delay time is provided by C1 incorporated in the
IC and, therefore, the latch circuit operates when the OVP or TSD circuit is in operation, or an external signal input is
provided for about 10 sec or longer.
In addition, even after the latch circuit start operating, the constant voltage regulator (Reg) circuit is in operation and the
circuit current is at high level.
As a result, VIN terminal voltage rapidly decreases.
When VIN terminal voltage becomes lower than the shutdown voltage, VIN(OFF) (4.9V typical), it starts increasing as the
circuit current is below 500 A.
When it reaches the ON-state voltage, VIN (ON) (8V typical), VIN terminal voltage starts decreasing because the circuit
current increases again.
When the latch circuit is on, VIN terminal voltage increases and decreases within the range from 4.9V typical to
8V typical and is prevented from abnormally rising.
Cancellation of the latch is done by decreasing VIN terminal voltage below 3.3V.
The power supply can be restarted after disconnecting an AC input to the power supply once.
(7) Thermal shutdown circuit
It is a circuit to trigger the latch circuit when the frame temperature of the IC exceeds 150 (typical).
Although the temperature is actually sensed at the control chip, it works against overheating of the power transistor
as the power transistor and the control IC are mounted on the same lead frame.
(8) Over-voltage protection circuit
It is a circuit to trigger the latch circuit when VIN terminal voltage exceeds 11V (typical).
38
Although it basically functions as protection of VIN terminal against over-voltage, since VIN terminal is usually supplied
from the drive winding of the transformer and the voltage is proportional to the output voltage, it also functions against
the over-voltage of secondary output which causes when the control circuit opens or in some other events.
39
Electrical Parts List
Components marked with this symbol must only be replaced by a component having
identical physical characteristics.
MODEL : C14M7E
LOC.PART-CODEPART-NAMEPART -DESCRIPTIONREMARK
ZZ10048BRM01A01
0003047P7500001BATTERYAAM 1.5V
ZZ13158G0000084COIL DEGAUSSINGDC-1450
ZZ13248519A4610CRT GROUND AS1401H-1015-1P
V9014859606240CRTA34EAC01X-AT1625/31
A0014859801493PCB MAIN330X246 D1B
SP014858306810SPEAKER3W 16 OHM F2035C03-3
C102CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C103CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C104CEXF1H479VC ELECTRO50V RSS 4.7MF (5X11) TP
C105CEXF1H479VC ELECTRO50V RSS 4.7MF (5X11) TP
C106CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C107CEXF1H479VC ELECTRO50V RSS 4.7MF (5X11) TP
C108CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C109CEXF1H479VC ELECTRO50V RSS 4.7MF (5X11) TP
C110CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C111CMXM2A104JC MYLAR100V 0.1MF J (TP)
C115CEXF1H109VC ELECTRO50V RSS 1MF (5X11) TP
C116CCZF1E223ZC CERA25V F 0.022MF Z (AXIAL)
C117CMXM2A473JC MYLAR100V 0.047MF J (TP)
C118CZCH1H100JC CERA50V CH 10PF J (AXIAL)
C120CEXD1H109FC ELECTRO50V RND 1MF (5X11) TP
C301CMXB2A104JC MYLAR100V EU 0.1MF J (TP)
C302CCZB1H181KC CERA50V B 180PF K (AXIAL)
C303CCZB1H181KC CERA50V B 180PF K (AXIAL)
C304CMXM2A104JC MYLAR100V 0.1MF J (TP)
C306CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C308CEXF1E471VC ELECTRO25V RSS 470MF (10X16) TP
C309CEXF2A470VC ELECTRO100V RSS 47MF (10X16) TP
C311CMXM2A103JC MYLAR100V 0.01MF J (TP)
C312CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C401CBZR1C472MC CERA16V Y5R 4700PF M (AXIAL)
C402CEXF1H109VC ELECTRO50V RSS 1MF (5X11) TP
C403CBZR1C222MC CERA16V Y5R 2200PF M (AXIAL)
C404CCZB1H181KC CERA50V B 180PF K (AXIAL)
C406CCXB1H222KC CERA50V B 2200PF K (TAPPING)
C409CCXB3D471KC CERA2KV B 470PF K (TAPPING)
C410CMYH3C622JC MYLAR1.6KV BUP 6200PF J
C411CMYE2D514JC MYLAR200V PU 0.51MF J
TRANSMITTER REMOCON
RM-01A01
43
LOC.PART-CODEP ART-NAMEPART -DESCRIPTIONREMARK
C412CEXF2C339VC ELECTRO160V RSS 3.3MF (8X16) TP
C414CCXB2H471KC CERA500V B 470PF K (TAPPING)
C415CMXM2A104JC MYLAR100V 0.1MF J (TP)
C416CCXB2H471KC CERA500V B 470PF K (TAPPING)
C417CEXF2E330VC ELECTRO250V RSS 33MF (13X25) TP
C418CCZF1E223ZC CERA25V F 0.022MF Z (AXIAL)
C419CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C420CXSL2H470JC CERA500V SL 47PF J (TAPPING)
C421CEXF2C101VC ELECTRO160V RSS 100MF (16X25) TP
C422CCXB2H471KC CERA500V B 470PF K (TAPPING)
C423CEXF1E101VC ELECTRO25V RSS 100MF (6.3X11) TP
C424CEXF1H478VC ELECTRO50V RSS 0.47MF (5X11) TP
C425CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C501CBZF1H104ZC CERA SEMI50V F 0.1MF Z (AXIAL)
C502CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C503CCZF1E223ZC CERA25V F 0.022MF Z (AXIAL)
C504CCZF1E223ZC CERA25V F 0.022MF Z (AXIAL)
C505CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C506CCZF1H473ZC CERA50V F 0.047MF Z (AXIAL)
C507CBZF1H104ZC CERA SEMI50V F 0.1MF Z (AXIAL)
C508CCZF1H473ZC CERA50V F 0.047MF Z (AXIAL)
C509CMXM2A104JC MYLAR100V 0.1MF J (TP)
C510CMXM2A104JC MYLAR100V 0.1MF J (TP)
C511CMXM2A104JC MYLAR100V 0.1MF J (TP)
C512CEXF1H109VC ELECTRO50V RSS 1MF (5X11) TP
C514CCZB1H151KC CERA50V B 150PF K (AXIAL)
C516CEXF1H478VC ELECTRO50V RSS 0.47MF (5X11) TP
C517CBZR1C472MC CERA16V Y5R 4700PF M (AXIAL)
C518CZCH1H180JC CERA50V CH 18PF J (AXIAL)
C519CBZF1H104ZC CERA SEMI50V F 0.1MF Z (AXIAL)
C520CBZF1H104ZC CERA SEMI50V F 0.1MF Z (AXIAL)
C521CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C522CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C523CCZF1E223ZC CERA25V F 0.022MF Z (AXIAL)
C524CBZF1H104ZC CERA SEMI50V F 0.1MF Z (AXIAL)
C525CEXF1C470VC ELECTRO16V RSS 47MF (5X11) TP
C526CMXM2A104JC MYLAR100V 0.1MF J (TP)
C527CMXB1H224JC MYLAR50V EU 0.22MF J (TP)
C528CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C529CEXF1C470VC ELECTRO16V RSS 47MF (5X11) TP
C530CEXF1H109VC ELECTRO50V RSS 1MF (5X11) TP
C531CCZF1H473ZC CERA50V F 0.047MF Z (AXIAL)
C532CCZB1H102KC CERA50V B 1000PF K (AXIAL)
44
LOC.PART-CODEP ART-NAMEPART -DESCRIPTIONREMARK
C533CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C604CCZB1H221KC CERA50V B 220PF K (AXIAL)
C605CZSL1H560JC CERA50V SL 56PF J (AXIAL)
C606CZSL1H680JC CERA50V SL 68PF J (AXIAL)
C607CEXD1H100FC ELECTRO50V RND 10MF (8X11.5) TP
C609CCZB1H181KC CERA50V B 180PF K (AXIAL)
C610CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C611CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C612CBZR1C392MC CERA16V Y5R 3900PF M (AXIAL)
C613CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C614CCZF1E223ZC CERA25V F 0.022MF Z (AXIAL)
C615CEXF1E471VC ELECTRO25V RSS 470MF (10X16) TP
C616CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C617CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C618CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C619CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C620CEXD1H229FC ELECTRO50V RND 2.2MF (5X11) TP
C621CEXD1H229FC ELECTRO50V RND 2.2MF (5X11) TP
C622CEXD1H229FC ELECTRO50V RND 2.2MF (5X11) TP
C623CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C624CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C625CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C626CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C631CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C632CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C633CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C634CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C635CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C636CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C637CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C638CEXD1H229FC ELECTRO50V RND 2.2MF (5X11) TP
C639CCZB1H101KC CERA50V B 100PF K (AXIAL)
C640CCZB1H101KC CERA50V B 100PF K (AXIAL)
C641CCZB1H101KC CERA50V B 100PF K (AXIAL)
C642CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C702CEXF1C470VC ELECTRO16V RSS 47MF (5X11) TP
C703CZSL1H240JC CERA50V SL 24PF J (AXIAL)
C704CZSL1H240JC CERA50V SL 24PF J (AXIAL)
C705CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C706CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C709CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C710CMXM2A104JC MYLAR100V 0.1MF J (TP)
C711CMXM2A104JC MYLAR100V 0.1MF J (TP)
45
LOC.PART-CODEP ART-NAMEPART -DESCRIPTIONREMARK
C712CEXF1H470VC ELECTRO50V RSS 47MF (6.3X11) TP
C713CCXF1H103ZC CERA50V F 0.01MF Z (TAPPING)
C714CMXB1H333JC MYLAR50V EU 0.033MF J (TP)
C715CMXB1H224JC MYLAR50V EU 0.22MF J (TP)
C716CMXB1H333JC MYLAR50V EU 0.033MF J (TP)
C717CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C718CEXF1C470VC ELECTRO16V RSS 47MF (5X11) TP
C720CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C721CEXF1C470VC ELECTRO16V RSS 47MF (5X11) TP
C722CXCH1H390JC CERA50V CH 39PF J (TAPPING)
C723CXCH1H360JC CERA50V CH 36PF J (TAPPING)
C724CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C725CEXF1C470VC ELECTRO16V RSS 47MF (5X11) TP
C726CEXF1C471VC ELECTRO16V RSS 470MF (10X12.5)TP
C727CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C801CL1JB3474KC LINE ACROSSAC250V 0.47MF U/C/SNDF/SV
C803CCXE2H472PC CERA500V E 4700PF P (TAPPING)
C804CCXE2H472PC CERA500V E 4700PF P (TAPPING)
C805CEYM2G121TC ELECTRO400V LWF 120MF (25X50)
C806CCYR3D471KC CERAHIKR 2KV 470PF K 125C
C807CEXF1E221VC ELECTRO25V RSS 220MF (8X11.5) TP
C808CEXF2A100VC ELECTRO100V RSS 10MF (6.3X11) TP
C809CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C810CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C811CEXF1E221VC ELECTRO25V RSS 220MF (8X11.5) TP
C812CH1FFE472MC CERA AC4.0KV 4700PF M KD AC250V
C817CCYB3D561KC CERA2KV B 560PF K
C818CEXF2C101VC ELECTRO160V RSS 100MF (16X25) TP
C821CEXF1E471VC ELECTRO25V RSS 470MF (10X16) TP
C823CEXF1E102CC ELECTRO25V RUS 1000MF (13X20) TP
C824CEXF1E101CC ELECTRO25V RUS 100MF (6.3X11) TP
C825CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C826CEXF1C470CC ELECTRO16V RUS 47MF (5X11) TP
C827CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C829CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C830CEXF1C101CC ELECTRO16V RUS 100MF (6.3X11) TP
C831CCXF1H103ZC CERA50V F 0.01MF Z (TAPPING)
C832CCZF1E103ZC CERA25V F 0.01MF Z (AXIAL)
C835CBZF1H104ZC CERA SEMI50V F 0.1MF Z (AXIAL)
C904CMXL2E104KC MYLAR250V MEU 0.1MF K
C905CMXL2E104KC MYLAR250V MEU 0.1MF K
C906CMXL2E104KC MYLAR250V MEU 0.1MF K
C907CCXB1H561KC CERA50V B 560PF K (TAPPING)
J02285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J02385801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J02485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J02585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J02785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J02885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03385801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J03985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J04985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05385801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J05985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J06985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J07085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J07285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
49
LOC.PART-CODEP ART-NAMEPART -DESCRIPTIONREMARK
J07485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J07585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J07685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J07785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08385801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J08985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09385801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J09985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J10085801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J10185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J10285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J10685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J10985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11385801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J11985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J12385801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J12485801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J12585801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J12685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J12785801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J12885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
J12985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
50
LOC.PART-CODEP ART-NAMEPART -DESCRIPTIONREMARK
J13185801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
JH014859102130JACK EARPHONEYSC-1537
JP0685801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
JP0885801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
JP0985801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
JS014859200401SOCKET RGBSR-21A1 (ANGLE TYPE)
JS024859108350JACK PIN BOARDYSC02P-4100-14A
L10158C9780027COIL CHOKETRF-1201B (0.97 UH)
L1035CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
L10458E0000S37COIL AFTTRF-A001
L3015CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
L3025CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
L4015CPZ109M02COIL PEAKING1UH M (AXIAL 3.5MM)
L40285801065GYWIRE COPPERAWG22 1/0.65 TIN COATING
L40558H0000016COIL H-LINEARITYL-102 (102UH)
L40658C9430599COIL CHOKEAZ-9004Y(94MH)
L5015CPZ569K02COIL PEAKING5.6UH K (AXIAL 3.5MM)
L6015MC0000100COIL BEADMD-5 (HC-3550)
L6025MC0000100COIL BEADMD-5 (HC-3550)
L6045CPZ829K02COIL PEAKING8.2UH K (AXIAL 3.5MM)
L6055CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
L6065CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
L6075CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
L60858C6R8J067COIL CHOKETRF-1015C (6.8UH J)
L6095CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
L61058C6R8J067COIL CHOKETRF-1015C (6.8UH J)
L7015CPZ689K02COIL PEAKING6.8UH K (AXIAL 3.5MM)
L8015PLF24A1—FILTER LINELF-24A1
L8045MC0000100COIL BEADMD-5 (HC-3550)
L8055CPZ100K04COIL PEAKING10UH 10.5MM K (LAL04TB)
LP025MC0000100COIL BEADMD-5 (HC-3550)
LP045MC0000100COIL BEADMD-5 (HC-3550)
M35197P2316600HOLDER AC CORDNYLON66 UL/CSA
M3524853530901HOLDER LEDHIPS BK
M7214857235802SHIELD CASE“SPTH-C (“”B+C””) HOLE”
P101485923162SCONN WAFERYW025-03 (STICK)
P4014859240120CONN WAFERYFW500-06
P401A4850706S20CONN AS35135-0620+35719+ULW=350
P501485923522SCONN WAFERYW025-09 (STICK)
P501A4850709S02CONN ASYH025-09+YST025+ULW=300
P601485923162SCONN WAFERYW025-03 (STICK)
P8014859242220CONN WAFERYFW800-02
P8024859242220CONN WAFERYFW800-02