Cypress Semiconductor STK15C88 Specification Sheet

STK15C88

256 Kbit (32K x 8) PowerStore nvSRAM

Features

Logic Block Diagram

■

25 ns and 45 ns access times

■

Pin compatible with industry standard SRAMs

■

Automatic nonvolatile STORE on power loss

■

Nonvolatile STORE under Software control

■

Automatic RECALL to SRAM on power up

■

Unlimited Read/Write endurance

■

Unlimited RECALL cycles

■

1,000,000 STORE cycles

■

100 year data retention

■

Single 5V+10% power supply

■

Commercial and Industrial Temperatures

■

28-pin (300 mil and 330 mil) SOIC packages

■

RoHS compliance

Functional Description

The Cypress STK15C88 is a 256Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations are also
available under software control.

PowerStore nvSRAM products depend on the intrinsic system
capacitance to maintain system power long enough for an
automatic store on power loss. If the power ramp from 5 volts
to 3.6 volts is faster than 10 ms, consider our 14C88 or 16C88
for more reliable operation.

™

technology

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-50593 Rev. ** Revised January 29, 2009

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STK15C88

Pin Configurations

Figure 1. Pin Diagram - 28-Pin SOIC

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Table 1. Pin Definitions - 28-Pin SOIC

Pin Name Alt IO Type Description

A

0–A14

DQ

-DQ

0

7

WE W

CE

OE

V

SS

V

CC

E

G

Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

Input or

Bidirectional Data IO lines. Used as input or output lines depending on operation.

Output

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the

IO pins is written to the specific address location.

Input Chip Enable Input, Active LOW. W hen LOW, selects the chi p. When HIGH, deselect s the

chip.

Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers

during read cycles. Deasserting OE

HIGH causes the IO pins to tri-state.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Document Number: 001-50593 Rev. ** Page 2 of 15

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STK15C88

Device Operation

Software STORE

The STK15C88 is a versatile memory chip that provides several
modes of operation. The STK15C88 can operate as a standard
32K x 8 SRAM. It has a 32K x 8 nonvolatile element shadow to
which the SRAM information can be copied, or from wh ich the
SRAM can be updated in nonvolatile mode.

SRAM Read

The STK15C88 performs a READ cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins A
determines the 32,768 data bytes accessed. When the READ is

0–14

initiated by an address transition, the outputs are valid after a
delay of t
the outputs are valid at t
cycle 2). The data outputs repeatedly respond to address
changes within the t
tions on any control input pins, and remains valid until a nother
address change or until CE

(READ cycle 1). If the READ is initiated by CE or OE,

AA

or at t

ACE

access time without the need for transi-

AA

, whichever is later (READ

DOE

or OE is brought HIGH.

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE
at the end of the cycle. The data on the common IO pins DQ
are written into the memory if it has valid tSD, before the end of
a WE

controlled WRITE or before the end of an CE controlled

WRITE. Keep OE

HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE
internal circuitry turns off the ou tput buff ers t
LOW.

or WE goes HIGH

is left LOW,

after WE goes

HZWE

0–7

AutoStore Operation

The STK15C88 uses the intrinsic system capacitance to perform
an automatic STORE on power down. As long as the system
power supply takes at least t
to 3.6V, the STK15C88 will safely and automatically store the

to decay from V

STORE

SWITCH

down

SRAM data in nonvolatile elements on power down.
In order to prevent unneeded STORE operations, automatic

STOREs will be ignored unless at least one WRITE operation
has taken place since the most recent STORE or RECALL cycle.
Software initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC <
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t

If the STK15C88 is in a WRITE
RECALL, the SRAM
situation, a 10 Kohm resistor is connected either between W E
and system VCC or between CE and system VCC.

), an internal RECALL request is latched. When V

RESET

SWITCH

HRECALL

state at the end of power up

data is corrupted. To help avoid this

, a RECALL

to complete.

CC

Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK15C88 software STORE
cycle is initiated by executing sequential CE

controlled READ
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ
sequence is performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE

controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the seque nce.
It is not necessary that OE
t

cycle time is fulfilled, the SRAM is again activated for

STORE

READ and WRITE operation.

is LOW for a valid sequence. After the

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE
performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.

controlled READ operations is

cycle time, the SRAM is once

RECALL

Document Number: 001-50593 Rev. ** Page 3 of 15

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STK15C88

Hardware Protect

The STK15C88 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage
conditions. When V
STORE operations and SRAM WRITEs are inhibited.

CAP<VSWITCH

, all externally initiated

Noise Considerations

The STK15C88 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF
connected between VCC and V
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals reduce circuit
noise.

using leads and traces that

SS,

Low Average Active Power

CMOS technology provides the STK15C88 the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns. Figure 2 and Figure 3 show the relationship
between I
current consumption is shown for both CMOS and TTL input
levels (commercial temperature range, VCC = 5.5V, 100%
duty cycle on chip enable). Only standby current is drawn
when the chip is disabled. The overall average current drawn
by the STK15C88 depends on the following items:

1. The duty cycle of chip enable

2. The overall cycle rate for accesses

3. The ratio of READs to WRITEs

4. CMOS versus TTL input levels

5. The operating temperature

6. The V

7. IO loading

Figure 2. Current Versus Cycle Time (WRITE)

and READ or WRITE cycle time. Worst case

CC

level

CC

Figure 3. Current Versus Cycle Time (READ)

Best Practices

nvSRAM products have been used effectively for over 15
years. While ease-of-use is one of the product’s main system
values, experience gained working with hundreds of applica­tions has resulted in the following suggestions as best
practices:

■

The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites, sometimes, reprogram these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF , A5, or 5A.
End product’s firmware should not assume a NV array is in
a set programmed state. Routines that check memory
content values to determine first time system configuration
and cold or warm boot status should always program a
unique NV pattern (for example, complex 4-byte pattern of
46 E6 49 53 hex or more random bytes) as part of the final
system manufacturing test to ensure these system routines
work consistently.

■

Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the nvSRAM
into the desired state as a safeguard against events that
might flip the bit inadvertently (program bugs and incoming
inspection routines).

Document Number: 001-50593 Rev. ** Page 4 of 15

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STK15C88

Table 2. Software STORE/RECALL Mode Selection

Notes

1. The six consecutive addresses must be in the order listed. WE

must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

2. While there are 15 addresses on the STK15C88, only the lower 14 are used to control software modes.

CE WE

A13 – A

L H 0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0FC0

L H 0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0C63

0

Mode IO Notes

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile STORE

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile RECALL

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

[1, 2]

[1, 2]

Document Number: 001-50593 Rev. ** Page 5 of 15

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STK15C88

Maximum Ratings

Note

3. CE

> VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Temperature under bias..............................–55°C to +125°C

Supply Voltage on VCC Relative to GND..........–0.5V to 7.0V

Voltage on Input Relative to Vss............–0.6V to V

+ 0.5V

CC

Voltage on DQ

Power Dissipation .........................................................1.0W

DC output Current (1 output at a time, 1s duration) ....15 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 4.5V to 5.5V
Industrial -40°C to +85°C 4.5V to 5.5V

...................................–0.5V to Vcc + 0.5V

0-7

CC

DC Electrical Characteristics

Over the operating range (VCC = 4.5V to 5.5V)

Parameter Description Test Conditions Min Max Unit

I

CC1

I

CC2

I

CC3

I

CC4

I

SB1

[3]

Average VCC Current tRC = 25 ns

Average VCC Current
during STORE

Average VCC Current
at t

= 200 ns, 5V,

RC

25°C Typical
Average Current

during AutoStore
Cycle

Average VCC Current
(Standby, Cycling
TTL Input Levels)

= 45 ns

t

RC

Dependent on output loading and cycle rate. Values
obtained without output loads.
I

= 0 mA.

OUT

Industrial 10070mA

All Inputs Do Not Care, VCC = Max

Commercial 9770mA

Average current for duration t

> (VCC – 0.2V). All other inputs cycling.

WE

STORE

Dependent on output loading and cycle rate. Values obtained
without output loads.

All Inputs Do Not Care, V
Average current for duration t

tRC=25ns, CE > V
tRC=45ns, CE > V

IH
IH

CC

= Max

STORE

Commercial 3022mA

Industrial 3123mA

mA

mA

3mA

10 mA

2mA

I

SB2

I

IX

I

OZ

V

V

V
V

IH

IL

OH
OL

[3]

VCC Standby Current
(Standby, Stable

CE > (VCC – 0.2V). All others V

< 0.2V or > (VCC – 0.2V). 1.5 mA

IN

CMOS Input Levels)
Input Leakage

Current
Off State Output

Leakage Current
Input HIGH Volt age 2.2 VCC +

VCC = Max, VSS < V

VCC = Max, VSS < V

< V

IN

CC

< VCC, CE or OE > V

IN

or WE < V

IH

-1 +1 μA

IL

-5 +5 μA

V

0.5

Input LOW Voltage VSS –

0.8 V

0.5
Output HIGH Voltage I
Output LOW Voltage I

= –4 mA 2.4 V

OUT

= 8 mA 0.4 V

OUT

Document Number: 001-50593 Rev. ** Page 6 of 15

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STK15C88

Data Retention and Endurance

5.0V

Output

30 pF

R1 480Ω

R2

255Ω

Input Pulse Levels..................................................0 V to 3 V

Input Rise and Fall Times (10% - 90%)........................ <

5 ns

Input and Output Timing Reference Levels................... 1.5 V

Note

4. These parameters are guaranteed by design and are not tested.

Parameter Description Min Unit

DATA
NV

C

R

Data Retention 100 Years
Nonvolatile STORE Operations 1,000 K

Capacitance

In the following table, the capacitance parameters are listed.

Parameter Description Test Conditions Max Unit

C
C

IN
OUT

Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 7 pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

Parameter Description Test Conditions

Θ

Θ

JA

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

T est conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA / JESD51.

Figure 4. AC Test Loads

[4]

V

= 0 to 3.0 V

CC

5pF

[4]

28-SOIC

(300 mil)

TBD TBD °C/W

TBD TBD °C/W

28-SOIC

(330 mil)

Unit

AC Test Conditions

Document Number: 001-50593 Rev. ** Page 7 of 15

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STK15C88

AC Switching Characteristics

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Notes

5. WE

must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.

6. I/O state assumes CE

and OE < VIL and WE > VIH; device is continuously selected.

7. Measured ±200 mV from steady state output voltage.

SRAM Read Cycle

Parameter

Cypress

Parameter

t

ACE

[5]

t

RC

[6]

t

AA

t

DOE

[6]

t

OHA

[7]

t

LZCE

[7]

t

HZCE

[7]

t

LZOE

[7]

t

HZOE

[4]

t

PU

[4]

t

PD

t
t
t
t
t
t
t
t
t
t
t

Alt

ELQV
AVAV, tELEH
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL

Chip Enable Access Time 25 45 ns
Read Cycle Time 25 45 ns
Address Access Time 25 45 ns
Output Enable to Data Valid 10 20 ns
Output Hold After Address Change 5 5 ns
Chip Enable to Output Active 5 5 ns
Chip Disable to Output Inactive 10 15 ns
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 10 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 25 45 ns

Switching Waveforms

Figure 5. SRAM Read Cycle 1: Address Controlled

Description

25 ns 45 ns

Min Max Min Max

[5, 7]

Unit

Figure 6. SRAM Read Cycle 2: CE and OE Controlled

Document Number: 001-50593 Rev. ** Page 8 of 15

[5]

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STK15C88

Table 3. SRAM Write Cycle

t

WC

t

SCE

t

HA

t

AW

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

t

WC

ADDRESS

t

SA

t

SCE

t

HA

t

AW

t

PWE

t

SD

t

HD

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

8. If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

9.

CE

or WE must be greater than VIH during address transitions.

Parameter

Cypress

Parameter

t

WC

t

PWE

t

SCE

t

SD

t

HD

t

AW

t

SA

t

HA

[7,8]

t

HZWE

[7]

t

LZWE

t

AVAV

t

WLWH, tWLEH

t

ELWH, tELEH

t

DVWH, tDVEH

t

WHDX, tEHDX

t

AVWH, tAVEH

t

AVWL, tAVEL

t

WHAX, tEHAX

t

WLQZ

t

WHQX

Alt

Switching Waveforms

25 ns 45 ns

Description

Min Max Min Max

Write Cycle Time 25 45 ns
Write Pulse Width 20 30 ns
Chip Enable To End of Write 20 30 ns
Data Setup to End of Write 10 15 ns
Data Hold After End of Write 0 0 ns
Address Setup to End of Write 20 30 ns
Address Setup to Start of Write 0 0 ns
Address Hold After End of Write 0 0 ns
Write Enable to Output Disable 10 15 ns
Output Active After End of Write 5 5 ns

Figure 7. SRAM Write Cycle 1: WE Controlled

[8]

Unit

Document Number: 001-50593 Rev. ** Page 9 of 15

Figure 8. SRAM Write Cycle 2: CE Controlled

[8]

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STK15C88

AutoStore or Power Up RECALL

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Notes

10.t

HRECALL

starts from the time VCC rises above V

SWITCH

.

Parameter Alt Description

t

HRECALL

t

STORE

V

RESET

V

SWITCH

[10]

[6]

t

RESTORE

t

HLHZ

Power up RECALL Duration 550 μs
STORE Cycle Duration 10 ms
Low Voltage Reset Level 3.6 V
Low Voltage Trigger Level 4.0 4.5 V

Switching Waveforms

Figure 9. AutoStore/Power Up RECALL

STK15C88

Min Max

Unit

Document Number: 001-50593 Rev. ** Page 10 of 15

[+] Feedback

STK15C88

Software Controlled STORE/RECALL Cycle

t

RC

t

RC

t

SA

t

SCE

t

HACE

t

STORE

/ t

RECALL

DATA VALID

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

CE

OE

DQ (DATA)

Notes

11.The software sequence is clocked on the falling edge of CE

without involving OE (double clocking will abort the sequence).

12.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE

must be HIGH during all six consecutive cycles.

The software controlled STORE/RECALL cycle follows.

Parameter Alt Description

t

RC

[11]

t

SA

[11]

t

CW

t

HACE

t

RECALL

[7, 11]

t

AVAV

t

AVEL

t

ELEH

t

ELAX

STORE/RECALL Initiation Cycle Time 25 45 ns
Address Setup Time 0 0 ns
Clock Pulse Width 20 30 ns
Address Hold Time 20 20 ns
RECALL Duration 20 20 μs

[11, 12 ]

25 ns 45 ns

Min Max Min Max

Unit

Switching Waveforms

Figure 10. CE Controlled Software STORE/RECALL Cycle

[12]

Document Number: 001-50593 Rev. ** Page 11 of 15

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STK15C88

Ordering Information

Speed:
25 - 25 ns
45 - 45 ns

Package:

S = Plastic 28-pin 330 mil SOIC

Part Numbering Nomenclature
STK15C88 - N F 45 I TR

Temperature Range:
Blank - Commercial (0 to 70°C)

Lead Finish
F = 100% Sn (Matte Tin)

I - Industrial (-40 to 85°C)

Packaging Option:
TR = Tape and Reel
Blank = Tube

N = Plastic 28-pin 300 mil SOIC

Speed

(ns)

25 STK15C88-NF25TR 51-85026 28-Pin SOIC (300 mil) Commercial

45 STK15C88-NF45TR 51-85026 28-Pin SOIC (300 mil) Commercial

All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts

Ordering Code Package Diagram Package Type

STK15C88-NF25 51-85026 28-Pin SOIC (300 mil)
STK15C88-SF25TR 51-85058 28-Pin SOIC (330 mil)
STK15C88-SF25 51-8 5058 28-Pin SOIC (330 mil)
STK15C88-NF25ITR 51-85026 28-Pin SOIC (300 mil) Industrial
STK15C88-NF25I 51-85026 28-Pin SOIC (300 mil)
STK15C88-SF25ITR 51-85058 28-Pin SOIC (330 mil)
STK15C88-SF25I 51-85058 28-Pin SOIC (330 mil)

STK15C88-NF45 51-85026 28-Pin SOIC (300 mil)
STK15C88-SF45TR 51-85058 28-Pin SOIC (330 mil)
STK15C88-SF45 51-8 5058 28-Pin SOIC (330 mil)
STK15C88-NF45ITR 51-85026 28-Pin SOIC (300 mil) Industrial
STK15C88-NF45I 51-85026 28-Pin SOIC (300 mil)
STK15C88-SF45ITR 51-85058 28-Pin SOIC (330 mil)
STK15C88-SF45I 51-85058 28-Pin SOIC (330 mil)

Operating

Range

Document Number: 001-50593 Rev. ** Page 12 of 15

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STK15C88

Package Diagrams

PIN 1 ID

0.291[7.39]

0.300[7.62]

0.394[10.01]

0.419[10.64]

0.050[1.27]

TYP.

0.092[2.33]

0.105[2.67]

0.004[0.10]

0.0118[0.30]

SEATING PLANE

0.0091[0.23]

0.0125[3.17]

0.015[0.38]

0.050[1.27]

0.013[0.33]

0.019[0.48]

0.026[0.66]

0.032[0.81]

0.697[17.70]

0.713[18.11]

0.004[0.10]

114

15 28

*

*

*

PART #

S28.3 STANDARD PKG.

SZ28.3 LEAD FREE PKG.

MIN.
MAX.

NOTE :

1. JEDEC STD REF MO-119

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE

3. DIMENSIONS IN INCHES

4. PACKAGE WEIGHT 0.85gms

DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.

51-85026-*D

Figure 11. 28-Pin (300 mil) SOIC (51-85026)

Document Number: 001-50593 Rev. ** Page 13 of 15

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STK15C88

Package Diagrams

51-85058-*A

(continued)

Figure 12. 28-Pin (330 mil) SOIC (51-85058)

Document Number: 001-50593 Rev. ** Page 14 of 15

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STK15C88

Document History Page

Document Title: STK15C88 256 Kbit (32K x 8) PowerStore nvSRAM
Document Number: 001-50593

Rev. ECN No.

Orig. of

Change

Submission

Date

Description of Change

** 2625096 GVCH/PYRS 12/19/08 New data sheet

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Document Number: 001-50593 Rev. ** Revised January 29, 2009 Page 15 of 15

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