Cypress Semiconductor STK14C88-3 Specification Sheet

STK14C88-3

256 Kbit (32K x 8) AutoStore nvSRAM

Features

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

Quantum Trap

512 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

OE

CE

WE

HSB

V

CC

V

CAP

A

13

- A

0

A

0

A

1

A

2

A

3

A

4

A

10

A

5

A

6

A

7

A

8

A

9

A

11

A

12

A

13

A

14

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Logic Block Diagram

■

35 ns and 45 ns access times

■

Automatic nonvolatile STORE on power loss

■

Nonvolatile STORE under Hardware or Software control

■

Automatic RECALL to SRAM on power up

■

Unlimited Read/Write endurance

■

Unlimited RECALL cycles

■

1,000,000 STORE cycles

■

100 year data retention

■

Single 3.3V+0.3V power supply

■

Commercial and Industrial Temperatures

■

32-pin (300mil) SOIC and 32-pin (600 mil) PDIP packages

■

RoHS compliance

Functional Description

The Cypress STK14C88-3 is a 256 Kb fast static RAM with
a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
technology producing the world’s most reliable nonvolatile
memory. The SRAM provides unlimited read and write
cycles, while independent, nonvolatile data resides in the
highly reliable QuantumTrap cell. Data transfers from the
SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power down. On power up, data
is restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL opera­tions are also available under software control.

™

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-50592 Rev. ** Revised January 29, 2009

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STK14C88-3

Pin Configurations

Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP

Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP

Pin Name Alt IO Type Description

A

0–A14

DQ

-DQ

0

7

WE W

CE

OE

V

SS

V

CC

HSB

V

CAP

E

G

Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

Input or

Bidirectional Data IO lines. Used as input or output lines depending on operation.

Output

Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the

IO pins is written to the specific address location.

Input Chip Enable Input, Active LOW. W hen LOW, selects the chi p. When HIGH, deselect s the

chip.

Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers

during read cycles. Deasserting OE

HIGH causes the IO pins to tri-state.

Ground Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or

Output

Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from

SRAM to nonvolatile elements.

Document Number: 001-50592 Rev. ** Page 2 of 17

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STK14C88-3

Device Operation

The STK14C88-3 nvSRAM is made up of two functional compo­nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The STK14C88-3 supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera­tions from the nonvolatile cells and up to one million STORE
operations.

SRAM Read

The STK14C88-3 performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the READ is initiated by an address transition, the outputs are
valid after a delay of t
by CE
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until

determines the 32,768 data bytes accessed. When

0–14

(READ cycle 1). If the READ is initiated

or OE, the outputs are valid at t

AA

or at t

ACE

access time without the need for

AA

, whichever

DOE

another address change or until CE or OE is brought HIGH, or
WE

or HSB is brought LOW.

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and

is HIGH. The address inputs must be stable prior to entering

HSB
the WRITE cycle and must remain stable until either CE

or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
the end of a WE

are written into the memory if it has valid tSD, before

0–7

controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE
LOW, inte rnal circuitry turns off the output buffers t
goes LOW.

HZWE

is left

after WE

AutoStore® Operation

The STK14C88-3 can be powered in one of three storage opera­tions:

During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V

pin drops below V

CC

pin from VCC. A STORE

CAP

pin. This stored

CAP

SWITCH

CAP

Figure 2 shows the proper connection of the storage capacitor

(V

) for automatic store operation. A charge storage capacitor

CAP

having a capacity of between 68 uF and 220 uF (+

20%) rated at

4.7V should be provided.
To reduce unnecessary nonvolatile stores, AutoStore and

Hardware Store operations are ignored, unless at least one

to

CC

, the part

capacitor.

Figure 2. AutoStore Mode

WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
The HSB

signal is monitored by the system to detect if an

AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc

reaches V
between V
of current between V

, then a 1 ohm resistor should be connected

SWITCH

and the system supply to avoid momentary excess

CC

CC

and V

CAP

.

AutoStore Inhibit Mode

If an automatic STORE on power loss is not required, then V
is tied to ground and +3.3V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is

(Figure 3). This is

CAP

disabled. If the STK14C88-3 is operated in this configuration,
references to V
sheet. In this mode, STORE

are changed to V

CC

operations are triggered through

throughout this data

CAP

software control. It is not permissible to change between these
options “On the fly”.

CC

.

Document Number: 001-50592 Rev. ** Page 3 of 17

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STK14C88-3

Figure 3. AutoStore Inhibit Mode

Hardware STORE (HSB) Operation

The STK14C88-3 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB
to request a hardware STORE cycle. When the HSB
driven LOW, the STK14C88-3 conditionally initiates a STORE
operation after t
WRITE to the SRAM takes place since the last STORE or
RECALL cycle. The HSB

. An actual STORE cycle only begins if a

DELAY

pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress. Pull up this
pin with an external 10K ohm resistor to V
as a driver.

SRAM READ and WRITE operations, that are in progress
when HSB

is driven LOW by any means, are given time to
complete before the STORE operation is initiated. After HSB
goes LOW, the STK14C88-3 continues SRAM operations for

. During t

t

DELAY

place. If a WRITE is in progress when HSB
allows a time, t
WRITE cycles requested after HSB
until HSB

The HSB

returns HIGH.
pin is used to synchronize multiple STK14C88-3

, multiple SRAM READ operations take

DELAY

to complete. However, any SRAM

DELAY

goes LOW are inhibited

while using a single larger capacitor. To operate in this mode,
the HSB

pin is connected together to the HSB pins from the
other STK14C88-3. An external pull up resistor to V
required, since HSB
V

pins from the other STK14C88-3 parts are tied together

CAP

acts as an open drain pull down. The

pin is used

pin is

if HSB is used

CAP

is pulled LOW, it

CAP

and share a single capacitor. The capacitor size is scaled by
the number of devices connected to it. When any one of the
STK14C88-3 detects a power loss and asserts HSB, the
common HSB
(A STORE

pin causes all parts to request a STORE cycle.

takes place in those STK14C88-3 that are written

since the last nonvolatile cycle.)
During any STORE operation, regardless of how it is initiated,

the STK14C88-3 continues to drive the HSB pin LOW,
releasing it only when the STORE is complete. After
completing the STORE operation, the STK14C88-3 remains
disabled until the HSB

pin returns HIGH.

If HSB is not used, it is left unconnected.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC <

), an internal RECALL request is latched. When V

V

RESET

once again exceeds the sense voltage of V
cycle is automatically initiated and takes t

If the STK14C88-3 is in a WRITE
RECALL, the SRAM

data is corrupted. To help avoid this

state at the end of power up

SWITCH

HRECALL

situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory
by a software address sequence. The STK14C88-3 software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact
order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed followed by a program of the
nonvolatile elements. When a STORE cycle is initiated, input
and output are disabled until the cycle is completed.

Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If they
intervene, the sequence is aborted and no STORE or RECALL
takes place.

To initiate the software STORE cycle, the following READ
sequence is performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE
When the sixth address in the sequence is entered, the
STORE cycle commences and the chip is disabled. It is
important that READ cycles and not WRITE cycles are used
in the sequence. It is not necessary that OE

is

sequence. After the t
again activated for READ and WRITE operation.

cycle time is fulfilled, the SRAM is

STORE

controlled READs.

is LOW for a valid

, a RECALL

CC

to complete.

Document Number: 001-50592 Rev. ** Page 4 of 17

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STK14C88-3

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE

controlled READ operations is

performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL

cycle time, the SRAM is once

RECALL

operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.

Preventing STORE

The STORE function can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a VOH of at least

2.2V , because it has to overpower the internal pull down device.
This device drives HSB LOW for 20 μs at the onset of a STORE.
When the STK14C88-3 is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on V
and V
attempts to pull HSB
V
attempt.

crosses V

CC

, the part stops trying to pull HSB LOW and aborts the STORE

IL

on the way down, the STK14C88-3

SWITCH

LOW. If HSB does not actually get below

CAP

Hardware Protect

The STK14C88-3 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage condi­tions. When V
operations and SRAM WRITEs are inhibited.

CAP<VSWITCH

, all externally initiated STORE

Noise Considerations

The STK14C88-3 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.

CC

and V

using leads and traces that are as short

SS,

Low Average Active Power

CMOS technology provides the STK14C88-3 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 and Figure 5 show the relationship between
I

and READ or WRITE cycle time. Worst case current

CC

consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 3.6V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK14C88-3
depends on the following items:

1. The duty cycle of chip enable

2. The overall cycle rate for accesses

3. The ratio of READs to WRITEs

4. CMOS versus TTL input levels

5. The operating temperature

6. The V

7. IO loading

Figure 4. Current Versus Cycle Time (READ)

)

Figure 5. Current Versus Cycle Time (WRITE)

CC

level

Document Number: 001-50592 Rev. ** Page 5 of 17

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STK14C88-3

Best Practices

Notes

1. I/O state assumes OE

< VIL. Activation of nonvolatile cycles does not depend on state of OE.

2. HSB

STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go

into standby mode, inhibiting all operations until HSB

rises.

3. CE

and OE LOW and WE HIGH for output behavior.

4. The six consecutive addresses must be in the order listed. WE

must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

5. While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.

nvSRAM products have been used effectively for over 15
years. While ease-of-use is one of the product’s main system
values, experience gained working with hundreds of applica­tions has resulted in the following suggestions as best
practices:

■

The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer ’s
sites, sometimes, reprogram these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in
a set programmed state. Routines that check memory
content values to determine first time system configuration
and cold or warm boot status, should always program a
unique NV pattern (for example, a complex 4-byte pattern of
46 E6 49 53 hex or more random bytes) as part of the final

Table 2. Hardware Mode Selection

system manufacturing test to ensure these system routines
work consistently. Power up boot firmware routines should
rewrite the nvSRAM into the desired state. While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs or incoming inspection routines).

■

The V
minimum and a maximum value size. Best practice is to meet
this requirement and not exceed the max V
because the higher inrush currents may reduce the reliability

value specified in this data sheet includes a

CAP

CAP

value

of the internal pass transistor. Customers who want to use a
larger V
should discuss their V
understand any impact on the V
of a t

value to ensure there is extra store charge

CAP

RECALL

period.

size selection with Cypress to

CAP

voltage level at the end

CAP

CE WE HSB

A13 – A

0

Mode IO Power

H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active
L L H X Write SRAM Input Data Active
X X L X Nonvolatile Store Output High Z I
LHH0x0E38

0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0

LHH0x0E38

0x31C7
0x03E0
0x3C1F
0x303F
0x0C63

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile STORE

Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM

Nonvolatile RECALL

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

Output Data
Output Data
Output Data
Output Data
Output Data
Output Data

Active

Active

CC2

[1, 3, 4, 5]

[1, 3, 4, 5]

[1]

[2]

Document Number: 001-50592 Rev. ** Page 6 of 17

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STK14C88-3

Maximum Ratings

Notes

6. V

CC

reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or V

CAP

if VCC is connected to ground.

7. CE

> VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Temperature under bias..............................–55°C to +125°C

Supply Voltage on VCC Relative to GND..........–0.5V to 7.0V

Voltage on Input Relative to Vss............–0.6V to V

CC

+ 0.5V

Voltage on DQ

or HSB ................ .......–0.5V to Vcc + 0.5V

0-7

Power Dissipation .........................................................1.0W

DC output Current (1 output at a time, 1s duration) ....15 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 3.0V to 3.6V
Industrial -40°C to +85°C 3.0V to 3.6V

CC

DC Electrical Characteristics

Over the operating range (VCC = 3.0V to 3.6V)

[6]

Parameter Description Test Conditions Min Max Unit

I

CC1

I

CC2

I

CC3

I

CC4

I

SB1

I

SB2

[7]

[7]

Average VCC Current tRC = 35 ns

= 45 ns

t

RC

Dependent on output loading and cycle rate. Values
obtained without output loads.
I

= 0 mA.

OUT

Average VCC Current
during STORE

Average VCC Current
at t

= 200 ns, 5V,

RC

25°C Typical
Average V

during AutoStore

CAP

Current

All Inputs Do Not Care, VCC = Max
Average current for duration t

> (VCC – 0.2V). All other inputs cycling.

WE
Dependent on output loading and cycle rate. Values obtained without
output loads.

All Inputs Do Not Care, V
Average current for duration t

Cycle
Average VCC Current

(Standby , Cycling TTL

tRC=35ns, CE > V
tRC=45ns, CE > V

Input Levels)

VCC Standby Current

CE > (VCC – 0.2V). All others V

(Standby, Stable

Commercial 5042mA

Industrial 5244mA

3mA

STORE

9mA

= Max

CC

STORE

IH
IH

Commercial 1816mA

2mA

Industrial 1917mA

< 0.2V or > (VCC – 0.2V). 1 mA

IN

CMOS Input Levels)
I
I

V

V

V
V
V

V

IX
OZ

IH

IL

OH
OL
BL

CAP

Input Leakage Current VCC = Max, VSS < V

Off State Output

VCC = Max, VSS < V

Leakage Current

< V

IN

CC

< VCC, CE or OE > V

IN

or WE < V

IH

-1 +1 μA

IL

-1 +1 μA

Input HIGH Volt age 2.2 VCC +

0.5

Input LOW Voltage VSS –

0.8 V

0.5
Output HIGH Voltage I
Output LOW Voltage I
Logic ‘0’ Voltage on

HSB

output

Storage Capacitor Between V

= –4 mA except HSB 2.4 V

OUT

= 8 mA except HSB 0.4 V

OUT

= 3 mA 0.4 V

I

OUT

pin and Vss, 68 to 220uF +20%, 4.7V rated. 54 264 uF

CAP

mA

mA

V

Document Number: 001-50592 Rev. ** Page 7 of 17

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STK14C88-3

Data Retention and Endurance

3.3V

Output

30 pF

R1 317Ω

R2

351Ω

Input Pulse Levels..................................................0 V to 3 V

Input Rise and Fall Times (10% - 90%)........................ <

5 ns

Input and Output Timing Reference Levels................... 1.5 V

Note

8. These parameters are guaranteed by design and are not tested.

Parameter Description Min Unit

DATA
NV

C

R

Data Retention 100 Years
Nonvolatile STORE Operations 1,000 K

Capacitance

In the following table, the capacitance parameters are listed.

Parameter Description Test Conditions Max Unit

C
C

IN
OUT

Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 7 pF

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

Parameter Description Test Conditions 32-SOIC 32-PDIP Unit

Θ

Θ

JA

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.

Figure 6. AC Test Loads

[8]

V

= 0 to 3.0 V

CC

5pF

[8]

TBD TBD °C/W

TBD TBD °C/W

AC Test Conditions

Document Number: 001-50592 Rev. ** Page 8 of 17

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STK14C88-3

AC Switching Characteristics

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Notes

9. WE

and HSB must be HIGH during SRAM Read Cycles.

10.I/O state assumes CE

and OE < VIL and WE > VIH; device is continuously selected.

11.Measured ±200 mV from steady state output voltage.

SRAM Read Cycle

Parameter

Cypress

Parameter

t

ACE

[9]

t

RC

[10]

t

AA

t

DOE

[10]

t

OHA

[11]

t

LZCE

[11]

t

HZCE

[11]

t

LZOE

[11]

t

HZOE

[8]

t

PU

[8]

t

PD

t
t
t
t
t
t
t
t
t
t
t

Alt

ELQV
AVAV, tELEH
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL

Chip Enable Access Time 35 45 ns
Read Cycle Time 35 45 ns
Address Access Time 35 45 ns
Output Enable to Data Valid 15 20 ns
Output Hold After Address Change 5 5 ns
Chip Enable to Output Active 5 5 ns
Chip Disable to Output Inactive 13 15 ns
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 13 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 35 45 ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled

Description

35 ns 45 ns

Min Max Min Max

[9, 10]

Unit

Figure 8. SRAM Read Cycle 2: CE and OE Controlled

Document Number: 001-50592 Rev. ** Page 9 of 17

[9]

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STK14C88-3

Table 3. SRAM Write Cycle

t

WC

t

SCE

t

HA

t

AW

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

t

WC

ADDRESS

t

SA

t

SCE

t

HA

t

AW

t

PWE

t

SD

t

HD

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

12.If WE

is Low when CE goes Low, the outputs remain in the high impedance state.

13.

CE

or WE must be greater than VIH during address transitions.

14.HSB

must be HIGH during SRAM WRITE cycles.

Parameter

Cypress

Parameter

t

WC

t

PWE

t

SCE

t

SD

t

HD

t

AW

t

SA

t

HA

t

HZWE

[11]

t

LZWE

[11,12]

t

AVAV

t

WLWH, tWLEH

t

ELWH, tELEH

t

DVWH, tDVEH

t

WHDX, tEHDX

t

AVWH, tAVEH

t

AVWL, tAVEL

t

WHAX, tEHAX

t

WLQZ

t

WHQX

Alt

Switching Waveforms

35 ns 45 ns

Description

Min Max Min Max

Write Cycle Time 35 45 ns
Write Pulse Width 25 30 ns
Chip Enable To End of Write 25 30 ns
Data Setup to End of Write 12 15 ns
Data Hold After End of Write 0 0 ns
Address Setup to End of Write 25 30 ns
Address Setup to Start of Write 0 0 ns
Address Hold After End of Write 0 0 ns
Write Enable to Output Disable 13 15 ns
Output Active After End of Write 5 5 ns

Figure 9. SRAM Write Cycle 1: WE Controlled

[13, 14]

Unit

Figure 10. SRAM Write Cycle 2: CE Controlled

Document Number: 001-50592 Rev. ** Page 10 of 17

[13, 14]

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STK14C88-3

AutoStore or Power Up RECALL

WE

Notes

15.t

HRECALL

starts from the time VCC rises above V

SWITCH

.

16.CE

and OE low and WE high for output behavior.

17.HSB

is asserted low for 1us when V

CAP

drops through V

SWITCH

. If an SRAM WRITE has not taken place sin ce the last nonvolatile cycle, HSB wil l be released a nd no

store will take place.

Parameter Alt Description

[16, 17]

[16]

[16]

[15]

t

RESTORE

t

HLHZ

t

BLQZ

Power up RECALL Duration 550 μs
STORE Cycle Duration 10 ms
Low Voltage Trigger (V
Low Voltage Reset Level 2.4 V
Low Voltage Trigger Level 2.7 2.95 V
Time Allowed to Complete SRAM Cycle 1 μs

t

HRECALL

t

STORE

t

VSBL

V

RESET

V

SWITCH

t

DELAY

Switching Waveforms

Figure 11. AutoStore/Power Up RECALL

STK14C88-3

Min Max

) to HSB low 300 ns

SWITCH

Unit

Document Number: 001-50592 Rev. ** Page 11 of 17

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STK14C88-3

Software Controlled STORE/RECALL Cycle

t

RC

t

RC

t

SA

t

SCE

t

HACE

t

STORE

/ t

RECALL

DATA VALID

DATA VALID

6#SSERDDA1#SSERDDA

HIGH IMPEDANCE

ADDRESS

CE

OE

DQ (DATA)

Notes

18.The software sequence is clocked on the falling edge of CE

without involving OE (double clocking will abort the sequence).

19.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE

must be HIGH during all six consecutive cycles.

The software controlled STORE/RECALL cycle follows.

Parameter Alt Description

[16]

t

RC

[18, 19]

t

SA

[18, 19]

t

CW

t

HACE

t

RECALL

[18, 19]

t

AVAV

t

AVEL

t

ELEH

t

ELAX

STORE/RECALL Initiation Cycle Time 35 45 ns
Address Setup Time 0 0 ns
Clock Pulse Width 25 30 ns
Address Hold Time 20 20 ns
RECALL Duration 20 20 μs

[18, 19]

Switching Waveforms

Figure 12. CE Controlled Software STORE/RECALL Cycle

35 ns 45 ns

Min Max Min Max

[19]

Unit

Document Number: 001-50592 Rev. ** Page 12 of 17

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STK14C88-3

Hardware STORE Cycle

3+6%

Note

20.t

DHSB

is only applicable after t

STORE

is complete.

Parameter Alt Description

t

PHSB

t

DHSB

t

HLBL

[16, 20]

t

HLHX

t

RECOVER, tHHQX

Hardware STORE Pulse Width 15 ns
Hardware STORE High to Inhibit Off 700 ns
Hardware STORE Low to STORE Busy 300 ns

Switching Waveforms

Figure 13. Hardware STORE Cycle

STK14C88-3

Min Max

Unit

Document Number: 001-50592 Rev. ** Page 13 of 17

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STK14C88-3

Ordering Information

Packaging Option:
TR = Tape and Reel
Blank = Tube

Speed:
35 - 35 ns
45 - 45 ns

Package:
N = Plastic 32-pin 300 mil SOIC

Part Numbering Nomenclature
STK14C88- 3N F 45 I TR

Temperature Range:
Blank - Commercial (0 to 70°C)

W

= Plastic 32-pin 600 mil DIP

Lead Finish
F = 100% Sn (Matte Tin)

I - Industrial (-40 to 85°C)

Speed

(ns)

35 STK14C88-3NF35TR 51-85127 32-pin SOIC Commercial

45 STK14C88-3NF45TR 51-85127 32-pin SOIC Commercial

All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts

Ordering Code Package Diagram Package Type

STK14C88-3NF35 51-85127 32-pin SOIC
STK14C88-3WF35 51-85018 32-pin PDIP
STK14C88-3NF35ITR 51-85127 32-pin SOIC Industrial
STK14C88-3NF35I 51-85127 32-pin SOIC
STK14C88-3WF35I 51-85018 32-pin PDIP

STK14C88-3NF45 51-85127 32-pin SOIC
STK14C88-3WF45 51-85018 32-pin PDIP
STK14C88-3NF45ITR 51-85127 32-pin SOIC Industrial
STK14C88-3NF45I 51-85127 32-pin SOIC
STK14C88-3WF45I 51-85018 32-pin PDIP

Operating

Range

Document Number: 001-50592 Rev. ** Page 14 of 17

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STK14C88-3

Package Diagrams

51-85058 *A

PIN 1 ID

SEATING PLANE

116

17 32

DIMENSIONS IN INCHES[MM]

MIN.
MAX.

0.292[7.416]

0.299[7.594]

0.405[10.287]

0.419[10.642]

0.050[1.270]
TYP.

0.090[2.286]

0.100[2.540]

0.004[0.101]

0.0100[0.254]

0.006[0.152]

0.012[0.304]

0.021[0.533]

0.041[1.041]

0.026[0.660]

0.032[0.812]

0.004[0.101]

REFERENCE JEDEC MO-119

PART #

S32.3 STANDARD PKG.

SZ32.3 LEAD FREE PKG.

0.014[0.355]

0.020[0.508]

0.810[20.574]

0.822[20.878]

51-85127-*A

Figure 14. 32-Pin (300 Mil) SOIC (51-85127)

Document Number: 001-50592 Rev. ** Page 15 of 17

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STK14C88-3

Package Diagrams






































²-).







3%!4).'0,!.%

$)-%.3)/.3).).#(%3

-).

-!8



 



51-85018-*A

(continued)

Figure 15. 32-Pin (600 Mil) PDIP (51-85018)

Document Number: 001-50592 Rev. ** Page 16 of 17

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STK14C88-3

Document History Page

Document Title: STK14C88-3 256 Kbit (32K x 8) AutoStore nvSRAM
Document Number: 001-50592

Rev. ECN No.

Orig. of

Change

Submission

Date

Description of Change

** 2625096 GVCH/PYRS 12/19/08 New data sheet

Sales, Solutions and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales.

Products

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USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2008- 2009. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warran ted no r inte nd ed to be used fo r
medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express written ag re em en t wi t h C ypr ess. Fu rth er mor e, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress
integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spec ified above is p rohibited with out
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-50592 Rev. ** Revised January 29, 2009 Page 17 of 17

AutoStore and Quant umTrap ar e registered tradem arks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be the trademarks of their respective
holders.

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