The Cypress STK11C88 is a 256 Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers under Software control from
SRAM to the nonvolatile elements (the STORE operation). On
power up, data is automatically restored to the SRAM (the
RECALL operation) from the nonvolatile memory. RECALL
operations are also available under software control.
InputAddress Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input or
Bidirectional Data IO lines. Used as input or output lines depending on operation.
Output
InputWrite Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
IO pins is written to the specific address location.
InputChip Enable Input, Active LOW. W hen LOW, selects th e chip. When H IGH, desel ects the
chip.
InputOutput Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE
HIGH causes the IO pins to tri-state.
GroundGround for the Device. The device is connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 001-50591 Rev. **Page 2 of 15
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STK11C88
Device Operation
The STK11C88 is a versatile memory chip that provides several
modes of operation. The STK11C88 can operate as a standard
32K x 8 SRAM. A32K x 8 array of nonvolatile storage elements
shadow the SRAM. SRAM data can be copied from nonvolatile
memory or nonvolatile data can be recalled to the SRAM.
SRAM Read
The STK11C88 performs a READ cycle whenever CE and OE
are LOW, while WE is HIGH. The address specified on pins
A
determines the 32,768 data bytes accessed. When the
0–14
READ is initiated by an address transition, the outputs are valid
after a delay of t
CE
or OE, the outputs are valid at t
later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remain valid until
another address change or until CE
(READ cycle 1). If the READ is initiated by
AA
access time without the need for
AA
ACE
or at t
, whichever is
DOE
or OE is brought HIGH.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common IO pins DQ
are written into the memory if it has valid tSD, before the end of
controlled WRITE or before the end of an CE controlled
a WE
WRITE. Keep OE
data bus contention on common IO lines. If OE
internal circuitry turns off the ou tput buff ers t
LOW.
HIGH during the entire WRITE cycle to avoid
is left LOW,
after WE goes
HZWE
0–7
Software ST ORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C88 software ST ORE
cycle is initiated by executing sequential CE
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
controlled READ
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE
controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the seque nce.
It is not necessary that OE is LOW for a valid sequence. After the
t
cycle time is fulfilled, the SRAM is again activated for
STORE
READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
cycle time, the SRAM is once
RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC<V
an internal RECALL request is latched. When V
exceeds the sense voltage of V
automatically initiated and takes t
If the STK11C88 is in a WRITE
RECALL, the SRAM
data is corrupted. To help avoid this
HRECALL
state at the end of power up
, a RECALL cycle is
SWITCH
to complete.
situation, a 10 Kohm resistor is connected either be tween WE
and system VCC or between CE and system VCC.
RESET
once again
CC
),
Document Number: 001-50591 Rev. **Page 3 of 15
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STK11C88
Hardware Protect
The STK11C88 of fers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage
conditions. When VCC<V
STORE operations and SRAM WRITEs are inhibited.
, all externally initiated
SWITCH
Noise Considerations
The STK11C88 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF
connected between VCC and V
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals help prevent
noise problems.
using leads and traces that
SS,
Low Average Active Power
CMOS technology provides the STK11C88 the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns. Figure 2 and Figure 3 show the relationship
between I
current consumption is shown for both CMOS and TTL input
levels (commercial temperature range, VCC = 5.5V, 100
percent duty cycle on chip enable). Only standby current is
drawn when the chip is disabled. The overall average current
drawn by the STK11C88 depends on the following items:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The V
7. IO loading
Figure 2. Icc (max) Reads
and READ or WRITE cycle time. Worst case
CC
level
CC
Figure 3. Icc (max) Writes
Best Practices
nvSRAM products have been used effectively for over 15
years. While ease-of-use is one of the product’s main system
values, the experience gained working with hundreds of applications has resulted in the following suggestions as best
practices:
■
The nonvolatile cells in a nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites, sometimes, reprogram these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that a NV
array is in a set programmed state. Routines that check
memory content values to determine first time system configuration and cold or warm boot status, should always program
a unique NV pattern (for example, a complex 4-byte pattern
of 46 E6 49 53 hex or more random bytes) as part of the final
system manufacturing test to ensure these system routines
work consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the nvSRAM
into the desired state as a safeguard against events that
might flip the bit inadvertently (program bugs or incoming
inspection routines).
Document Number: 001-50591 Rev. **Page 4 of 15
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STK11C88
Table 2. Software STORE/RECALL Mode Selection
Notes
1. The six consecutive addresses must be in the order listed. WE
must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
2. While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
CEWE
A13 – A
LH0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
LH0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
0
ModeIONotes
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
[1, 2]
[1, 2]
Document Number: 001-50591 Rev. **Page 5 of 15
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STK11C88
Maximum Ratings
Note
3. CE
> VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Tem perature .................................–65°C to +150°C
Temperature under bias..............................–55°C to +125°C
Supply Voltage on VCC Relative to GND..........–0.5V to 7.0V
Voltage on Input Relative to Vss............–0.6V to V
+ 0.5V
CC
Voltage on DQ
Power Dissipation .........................................................1.0W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Operating Range
RangeAmbient TemperatureV
Commercial0°C to +70°C4.5V to 5.5V
Industrial-40°C to +85°C4.5V to 5.5V
...................................–0.5V to Vcc + 0.5V
0-7
CC
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V)
ParameterDescriptionTest ConditionsMinMaxUnit
I
CC1
I
CC2
I
CC3
I
SB1
Average VCC Current tRC = 25 ns
t
= 45 ns
RC
Dependent on output loading and cycle rate.
Values obtained without output loads.
I
= 0 mA.
OUT
Average VCC Current
during STORE
Average VCC Current
= 200 ns, 5V,
at t
RC
25°C Typical
[3]
Average VCC Current
(Standby, Cycling
TTL Input Levels)
All Inputs Do Not Care, VCC = Max
Average current for duration t
WE
> (VCC – 0.2V). All other inputs cycling.
STORE
Dependent on output loading and cycle rate. Values obtained
without output loads.
tRC=25ns, CE > V
tRC=45ns, CE > V
IH
IH
Commercial9770mA
Industrial10070mA
3mA
10mA
Commercial3022mA
Industrial3123mA
mA
mA
I
SB2
[3]
VCC Standby Current
(Standby, Stable
CE
> (VCC – 0.2V). All others V
< 0.2V or > (VCC – 0.2V). 750μA
IN
CMOS Input Levels)
I
IX
I
OZ
V
IH
V
IL
V
OH
V
OL
Input Leakage
Current
Off State Output
Leakage Current
VCC = Max, VSS < V
VCC = Max, VSS < V
< V
IN
CC
< VCC, CE or OE > V
IN
or WE < V
IH
IL
Input HIGH Voltage2.2VCC +
Input LOW VoltageVSS –
Output HIGH Voltage I
Output LOW Voltage I
= –4 mA 2.4V
OUT
= 8 mA 0.4V
OUT
Data Retention and Endurance
ParameterDescriptionMinUnit
DATA
NV
C
R
Data Retention100Years
Nonvolatile STORE Operations1,000K
-1+1μA
-5+5μA
V
0.5
0.8V
0.5
Document Number: 001-50591 Rev. **Page 6 of 15
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STK11C88
Capacitance
5.0V
Output
30 pF
R1 480Ω
R2
255Ω
Input Pulse Levels..................................................0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................ <
5 ns
Input and Output Timing Reference Levels................... 1.5 V
Note
4. These parameters are guaranteed by design and are not tested.
In the following table, the capacitance parameters are listed.
ParameterDescriptionTest ConditionsMaxUnit
C
C
IN
OUT
Input CapacitanceTA = 25°C, f = 1 MHz,
Output Capacitance7pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
ParameterDescriptionTest Conditions
Θ
Θ
JA
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
T est conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA / JESD51.
Figure 4. AC Test Loads
[4]
V
= 0 to 3.0 V
CC
5pF
[4]
28-SOIC
(300 mil)
TBDTBD°C/W
TBDTBD°C/W
28-SOIC
(330 mil)
Unit
AC Test Conditions
Document Number: 001-50591 Rev. **Page 7 of 15
[+] Feedback
STK11C88
AC Switching Characteristics
W
5&
W
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W
2+$
$''5(66
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W
5&
&(
W
$&(
W
/=&(
W
3'
W
+=&(
2(
W
'2(
W
/=2(
W
+=2(
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W
38
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,&&
Notes
5. WE
must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE
and OE < VIL and WE > VIH; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
Chip Enable Access Time2545ns
Read Cycle Time2545ns
Address Access Time2545ns
Output Enable to Data Valid1020ns
Output Hold After Address Change55ns
Chip Enable to Output Active55ns
Chip Disable to Output Inactive1015ns
Output Enable to Output Active00ns
Output Disable to Output Inactive1015ns
Chip Enable to Power Active00ns
Chip Disable to Power Standby2545ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled
Description
25 ns 45 ns
MinMaxMinMax
[5, 6]
Unit
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
Document Number: 001-50591 Rev. **Page 8 of 15
[5]
[+] Feedback
STK11C88
SRAM Write Cycle
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
8. If WE
is Low when CE goes Low, the outputs remain in the high impedance state.
9.
CE
or WE must be greater than VIH during address transitions.
Parameter
Cypress
Parameter
t
WC
t
PWE
t
SCE
t
SD
t
HD
t
AW
t
SA
t
HA
[7,8]
t
HZWE
[7]
t
LZWE
t
AVAV
t
WLWH, tWLEH
t
ELWH, tELEH
t
DVWH, tDVEH
t
WHDX, tEHDX
t
AVWH, tAVEH
t
AVWL, tAVEL
t
WHAX, tEHAX
t
WLQZ
t
WHQX
Alt
Switching Waveforms
25 ns 45 ns
Description
MinMaxMinMax
Write Cycle Time2545ns
Write Pulse Width2030ns
Chip Enable To End of Write2030ns
Data Setup to End of Write1015ns
Data Hold After End of Write00ns
Address Setup to End of Write2030ns
Address Setup to Start of Write00ns
Address Hold After End of Write00ns
Write Enable to Output Disable101 5ns
Output Active After End of Write55ns
Figure 7. SRAM Write Cycle 1: WE Controlled
[9]
Unit
Document Number: 001-50591 Rev. **Page 9 of 15
Figure 8. SRAM Write Cycle 2: CE Controlled
[9]
[+] Feedback
STK11C88
STORE INHIBIT or Power Up RECALL
V
CC
V
SWITCH
V
RESET
POWER-UP RECALL
DQ (DATA OUT)
STORE INHIBIT
5V
t
HRECALL
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE INHIBIT
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE INHIBIT
RECALL WHEN
V
CC
RETURNS
ABOVE V
SWITCH
Notes
10.t
HRECALL
starts from the time VCC rises above V
SWITCH
.
ParameterAltDescription
t
HRECALL
t
STORE
V
RESET
V
SWITCH
[10]
[6]
t
RESTORE
t
HLHZ
Power up RECALL Duration550μs
STORE Cycle Duration10ms
Low Voltage Reset Level3.6V
Low Voltage Trigger Level4.04.5V
Switching Waveforms
Figure 9. STORE INHIBIT/Power Up RECALL
STK11C88
MinMax
Unit
Document Number: 001-50591 Rev. **Page 10 of 15
[+] Feedback
STK11C88
Software Controlled STORE/RECALL Cycle
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
11.The software sequence is clocked on the falling edge of CE
without involving OE (double clocking abort the sequence).
12.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE
must be HIGH during all six consecutive cycles.
The software controlled STORE/RECALL cycle follows.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress
integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spec ified above is p rohibited with out
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-50591 Rev. **Revised January 29, 2009Page 15 of 15
AutoStore and Quant umTrap ar e registered tradem arks of Cypress Semico nductor Corporat ion. All product s and company n ames mentioned in this document may be the trademarks of their respective
holders.
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