Cypress Semiconductor S29JL064J User Manual

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S29JL064J

64 Mbit (8 M x 8-Bit/4 M x 16-Bit), 3 V

Simultaneous Read/Write Flash

Distinctive Characteristics

Architectural Advantages

 Simultaneous Read/Write operations

– Data can be continuously read from one bank while executing

erase/program functions in another bank

– Zero latency between read and write operations

 Flexible bank architecture

– Read may occur in any of the three banks not being programmed

or erased

– Four banks may be grouped by customer to achieve desired bank

divisions

 Boot sectors

– Top and bottom boot sectors in the same device – Any combination of sectors can be erased

 Manufactured on 0.11 µm Process Technology  Secured Silicon Region: Extra 256-byte sector

– Factory locked and identifiable: 16 bytes available for secure,

random factory Electronic Serial Number; verifiable as factory locked through autoselect function

– Customer lockable: One-time programmable only. Once locked,

data cannot be changed

 Zero power operation

– Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero

 Compatible with JEDEC standards

– Pinout and software compatible with single-power-supply flash

standard

Package Options

 48-ball Fine-pitch BGA

 48-pin TSOP

Performance Characteristics

 High performance

– Access time as fast as 55 ns – Program time: 7 µs/word typical using accelerated programming

function

 Ultra low power consumption (typical values)

– 2 mA active read current at 1 MHz – 10 mA active read current at 5 MHz – 200 nA in standby or automatic sleep mode

 Cycling endurance: 1 million cycles per sector typical

 Data retention: 20 years typical

Software Features

 Supports Common Flash Memory Interface (CFI)

 Erase suspend/erase resume

– Suspends erase operations to read data from, or program data to,

a sector that is not being erased, then resumes the erase operation

 Data# polling and toggle bits

– Provides a software method of detecting the status of program or

erase operations

 Unlock bypass program command

– Reduces overall programming time when issuing multiple program

command sequences

Hardware Features

 Ready/Busy# output (RY/BY#)

– Hardware method for detecting program or erase cycle

completion

 Hardware reset pin (RESET#)

– Hardware method of resetting the internal state machine to the

read mode

 WP#/ACC input pin

– Write protect (WP#) function protects sectors 0, 1, 140, and 141,

regardless of sector protect status

– Acceleration (ACC) function accelerates program timing

 Sector Protection

– Hardware method to prevent any program or erase operation

within a sector

– Temporary Sector Unprotect allows changing data in protected

sectors in-system

General Description

The S29JL064J is a 64 Mbit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt V

supply, and can also be programmed in standard EPROM programmers. The

device is available with an access time of 55, 60, 70 ns and is offered in a 48-ball FBGA or 48-pin TSOP package. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus

contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 002-00856 Rev. *E Revised December 08, 2015

S29JL064J

1. Simultaneous Read/Write Operations with Zero

Latency ......................................................................... 3

1.1 S29JL064J Features...................................................... 3

2. Product Selector Guide............................................... 4

3. Block Diagram.............................................................. 4

4. Connection Diagrams.................................................. 5

4.1 48-pin TSOP Package ................................................... 5

4.2 48-ball FBGA Package .................................................. 6

5. Pin Description............................................................. 6

6. Logic Symbol ............................................................... 7

7. Ordering Information................................................... 8

8. Device Bus Operations................................................ 9

8.1 Word/Byte Configuration................................................ 9

8.2 Requirements for Reading Array Data......................... 10

8.3 Writing Commands/Command Sequences.................. 10

8.4 Simultaneous Read/Write Operations with

Zero Latency ................................................................ 10

8.5 Standby Mode.............................................................. 11

8.6 Automatic Sleep Mode................................................. 11

8.7 RESET#: Hardware Reset Pin..................................... 11

8.8 Output Disable Mode ................................................... 12

8.9 Autoselect Mode .......................................................... 16

8.10 Boot Sector/Sector Block Protection and Unprotection 17

8.11 Write Protect (WP#)..................................................... 18

8.12 Temporary Sector Unprotect........................................ 19

8.13 Secured Silicon Region................................................ 21

8.14 Hardware Data Protection............................................ 22

9. Common Flash Memory Interface (CFI) ................... 23

10. Command Definitions................................................ 26

10.1 Reading Array Data ..................................................... 26

10.2 Reset Command.......................................................... 26

10.3 Autoselect Command Sequence ................................. 27

10.4 Enter Secured Silicon Region/Exit Secured

Silicon Region Command Sequence ........................... 27

10.5 Byte/Word Program Command Sequence................... 27

10.6 Chip Erase Command Sequence ................................ 29

10.7 Sector Erase Command Sequence ............................. 29

10.8 Erase Suspend/Erase Resume Commands ................ 30

11. Write Operation Status.............................................. 32

11.1 DQ7: Data# Polling ...................................................... 32

11.2 RY/BY#: Ready/Busy#................................................. 33

11.3 DQ6: Toggle Bit I ......................................................... 34

11.4 DQ2: Toggle Bit II ........................................................ 35

11.5 Reading Toggle Bits DQ6/DQ2.................................... 36

11.6 DQ5: Exceeded Timing Limits ..................................... 36

11.7 DQ3: Sector Erase Timer............................................. 36

12. Absolute Maximum Ratings...................................... 37

13. Operating Ranges...................................................... 38

14. DC Characteristics..................................................... 38

14.1 CMOS Compatible........................................................ 38

14.2 Zero-Power Flash ......................................................... 39

15. Test Conditions........................................................... 40

16. Key To Switching Waveforms.................................... 41

17. AC Characteristics...................................................... 42

17.1 Read-Only Operations .................................................. 42

17.2 Hardware Reset (RESET#)........................................... 43

17.3 Word/Byte Configuration (BYTE#)................................ 44

17.4 Erase and Program Operations .................................... 45

17.5 Temporary Sector Unprotect......................................... 49

17.6 Alternate CE# Controlled Erase and Program

Operations .................................................................... 50

18. Erase and Programming Performance ..................... 52

19. Pin Capacitance.......................................................... 52

20. Physical Dimensions.................................................. 53

20.1 TS 048—48-Pin Standard TSOP.................................. 53

20.2 VBK048—48-Pin FBGA................................................ 54

21. Revision History.......................................................... 55

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S29JL064J

1. Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two

8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups.

During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

The S29JL064J is organized as a dual boot device with both top and bottom boot sectors.

Bank Mbits Sector Sizes

Bank 1 8 Mb

Bank 2 24 Mb Forty-eight 64 kbyte/32 kword

Bank 3 24 Mb Forty-eight 64 kbyte/32 kword

Bank 4 8 Mb

1.1 S29JL064J Features

The Secured Silicon Region is an extra 256 byte sector capable of being permanently locked by Spansion or customers. The

Secured Silicon Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been customer locked, and permanently set to 0 if the part has been factory locked. This way, customer lockable parts can never be used to replace a factory locked part.

Factory locked parts provide several options. The Secured Silicon Region may store a secure, random 16 byte ESN (Electronic

Serial Number), customer code (programmed through Spansion programming services), or both. Customer Lockable parts may utilize the Secured Silicon Region as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there.

The device offers complete compatibility with the JEDEC 42.4 single-power-supply Flash comma nd set standard. Commands

are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7

(Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other

sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors

of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or

program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Region (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters

the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in

both modes.

detector that automatically inhibits write operations during power

Eight 8 kbyte/4 kword,

Fifteen 64 kbyte/32 kword

Eight 8 kbyte/4 kword,

Fifteen 64 kbyte/32 kword

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S29JL064J

2. Product Selector Guide

Bank 1 Address

Bank 2 Address

A21–A0

RESET#

WE#

CE#

BYTE#

DQ0–DQ15

WP#/ACC

STATE

CONTROL

COMMAND

RY/BY#

Bank 1

X-Decoder

OE# BYTE#

DQ15–DQ0

Status

Control

A21–A0

A21–A0A21–A0

DQ15–DQ0

Mux

Bank 2

X-Decoder

Y-gate

Bank 3

X-Decoder

Bank 4

X-Decoder

Y-gate

Bank 3 Address

Bank 4 Address

Part Number S29JL064J

Speed Option Standard Voltage Range: VCC = 2.7–3.6V 55 60 70

Max Access Time (ns), t

CE# Access (ns), t

OE# Access (ns), t

ACC

55 60 70

25 25 30

3. Block Diagram

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S29JL064J

4. Connection Diagrams

2 3 4 5 6 7 8

17 18 19 20 21 22 23 24

9 10 11 12 13 14 15

47 46 45 44 43 42 41 40 39 38 37 36 35 34

32 31 30 29 28 27 26

A15

A18

A14 A13 A12 A11 A10

A8 A19 A20

WE#

RESET#

A21

WP#/ACC

RY/BY#

A17

A16

DQ2

BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13

DQ9 DQ1 DQ8 DQ0 OE#

CE# A0

DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10

4.1 48-pin TSOP Package

Figure 4.1 48-Pin Standard TSOP

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S29JL064J

4.2 48-ball FBGA Package

Figure 4.2 48-ball FBGA

5. Pin Description

A21–A0

DQ14–DQ0

DQ15/A-1

CE#

OE#

WE#

WP#/ACC

RESET#

BYTE#

RY/BY#

VCC

DNU

RFU

22 Address pins

15 Data Inputs/Outputs (x16-only devices)

DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode)

Chip Enable, Active Low

Output Enable, Active Low

Write Enable, Active Low

Hardware Write Protect/Acceleration Pin

Hardware Reset Pin, Active Low

Selects 8-bit or 16-bit mode, Active Low

Ready/Busy Output, Active Low

3.0 volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage

supply tolerances)

Device Ground

Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).

Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal is at V unconnected in the host system or may be tied to V Do not connect any host system signal to these connections.

Reserved for Future Use. No device internal signal is currently connected to the package connector but there is potential future use for the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices.

A13

WE#

RY/BY#

B6 C6 D6 E6 F6 G6 H6

DQ6DQ13DQ14DQ7A11A10A8

DQ4V

DQ3DQ11DQ10DQ2A20A18WP#/ACC

DQ1DQ9DQ8DQ0A5A6A17

DQ15/A-1BYTE#A16A15A14A12

B5 C5 D5 E5 F5 G5 H5

B4 C4 D4 E4 F4 G4 H4

DQ12DQ5A19A21RESET#

B3 C3 D3 E3 F3 G3 H3

B2 C2 D2 E2 F2 G2 H2

B1 C1 D1 E1 F1 G1 H1

OE#CE#A0A1A2A4

. The signal has an internal pull-down resistor and may be left

. Do not use these connections for PCB signal routing channels.

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S29JL064J

6. Logic Symbol

16 or 8

DQ15–DQ0

(A-1)

A21–A0

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

WP#/ACC

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S29JL064J

7. Ordering Information

The order number is formed by a valid combination of the following:

S29JL064J 55 T F I 00 0

Packing Type

0=Tray 3 = 13-inch Tape and Reel

Model Number (Additional Ordering Options)

00 = Standard Configuration

Temperature Range

I = Industrial (–40°C to +85°C)

Package Material Set

F = Pb-free H = Low-halogen, Pb-free

Package Type

B = Fine-pitch Ball Grid Array (FBGA) Package T = Thin Small Outline Package (TSOP) Standard Pinout

Speed Option

55 = 55 ns 60 = 60 ns 70 = 70 ns

Product Family

S29JL064J: 3.0 Volt-only, 64 Mbit (4 M x 16-bit/8 M x 8-bit) Simultaneous Read/ Write Flash Memory Manufactured on 110 nm process technology

S29JL064J Valid Combinations

Device Number/

Description Speed (ns)

S29JL064J 55, 60, 70

Note:

1. Packing type 0 is standard. Specify other options as required.

Package Type

& Material Temperature Range Model Number Packing Type Package Description

BH VBK048 FBGA

I000, 3 (1)

TS048 TSOP

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S29JL064J

8. Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

S29JL064J Device Bus Operations

DQ15–DQ8

Operation CE# OE# WE# RESET#

Read L L H H L/H A

Write L H L H (Note 3) A



Standby

Output Disable L H H H L/H X High-Z High-Z High-Z

Reset X X X L L/H X High-Z High-Z High-Z

Sector Protect (Note 2) LHL V

Sector Unprotect

(Note 2)

Temporary Sector Unprotect

Legend

L = Logic Low = V H = Logic High = V VID = 11.5–12.5V

= 9.0 ± 0.5V

X = Don’t Care SA = Sector Address

= Address In

= Data In

= Data Out

OUT

0.3V

LHL V

XXX V

VCC 

0.3V

WP#/

ACC

L/H X High-Z High-Z High-Z

L/H

(Note 3)

(Note 3) A

Addresses

(Note 1)

SA, A6 = L,

A1 = H, A0 = L

SA, A6 = H,

A1 = H, A0 = L

BYTE#

= V

OUT

XXD

BYTE# = V

DQ14–DQ8 = High-Z,

DQ15 = A-1

High-Z D

DQ7–

DQ0

OUT

Notes:

1. Addresses are A21:A0 in word mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Boot Sector/Sector Block Protection and Unprotection

on page 17.

3. If WP#/ACC = V protected or unprotected using the method described in Boot Sector/ Sector Block Protection and Unprotection on page 17. If WP#/ACC = V unprotected.

, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141 depends on whether they were last

), A21:A-1 in byte mode (BYTE# = VIL).

, all sectors will be

8.1 Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

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S29JL064J

8.2 Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered.

Refer to Read-Only Operations on page 42 for timing specifications and to Figure 17.1 on page 42 for the timing diagram. I

Characteristics on page 38 represents the active current specification for reading array data.

CC1

in DC

8.3 Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte

Configuration on page 9 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Byte/Word Program Command Sequence on page 27 has

details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 15 indicates the address space that

each sector occupies. Similarly, a sector address is the address bits required to uniquely select a sector. Command Definitions

on page 26 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

The device address space is divided into four banks. A bank address is the address bits required to uniquely select a bank.

in the DC Characteristics on page 38 represents the active current specification for the write mode. AC Characteristics

CC2

on page 42 contains timing specification tables and timing diagrams for write operations.

8.3.1 Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result. See Write Protect (WP#) on page 18 for related information.

from the WP#/

8.3.2 Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings

apply in this mode. Refer to Autoselect Mode on page 16 and Autoselect Command Sequence on page 27 for more information.

8.4 Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 17.8 on page 47 shows how read and write cycles may be initiated for simultaneous operation with zero latency.

and I

CC6

erase, respectively.

in the DC Characteristics on page 38 represent the current specifications for read-while-program and read-while-

CC7

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S29JL064J

8.5 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3V. (Note that this is a more restricted voltage range than V

.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3V, the device will be in the standby

mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

in DC Characteristics on page 38 represents the standby current specification.

CC3

8.6 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

+ 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.

ACC

Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in DC Characteristics on page 38 represents the automatic sleep mode current specification.

CC5

8.7 RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V current (I

). If RESET# is held at VIL but not within V

CC4

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t the RESET# pin returns to V

Refer to Hardware Reset (RESET#) on page 43 for RESET# parameters and to Figure 17.2 on page 43 for the timing diagram.

, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/

±0.3V, the device draws CMOS standby

±0.3V, the standby current will be greater.

(during Embedded Algorithms). The system can thus monitor RY/BY# to determine

READY

(not during Embedded Algorithms). The system can read data tRH after

READY

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S29JL064J

8.8 Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

S29JL064J Sector Architecture (Sheet 1 of 4)

Bank Sector

SA0 0000000000 8/4 000000h–001FFFh 00000h–00FFFh

SA1 0000000001 8/4 002000h–003FFFh 01000h–01FFFh

SA2 0000000010 8/4 004000h–005FFFh 02000h–02FFFh

SA3 0000000011 8/4 006000h–007FFFh 03000h–03FFFh

SA4 0000000100 8/4 008000h–009FFFh 04000h–04FFFh

SA5 0000000101 8/4 00A000h–00BFFFh 05000h–05FFFh

SA6 0000000110 8/4 00C000h–00DFFFh 06000h–06FFFh

SA7 0000000111 8/4 00E000h–00FFFFh 07000h–07FFFh

SA8 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh

SA9 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh

SA10 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh

Bank 1

SA11 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh

SA12 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh

SA13 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh

SA14 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh

SA15 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh

SA16 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh

SA17 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh

SA18 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh

SA19 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh

SA20 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh

SA21 0001110xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh

SA 22 00 01111x xx 64 /32 0 F0000h–0FFFFFh 78000h–7FFFFh

Sector Address

A21–A12

Sector Size

(kbytes/kwords)

(x8)

Address Range

(x16)

Address Range

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S29JL064J

S29JL064J Sector Architecture (Sheet 2 of 4)

Bank Sector

SA23 0010000xxx 64/32 100000h–10FFFFh 80000h–87FFFh

SA24 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh

SA25 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh

SA26 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh

SA27 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh

SA28 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh

SA29 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh

SA30 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh

SA31 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh

SA32 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh

SA33 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh

SA34 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh

SA35 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh

SA36 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh

SA37 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh

SA38 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh

SA39 0100000xxx 64/32 200000h–20FFFFh 100000h–107FFFh

SA40 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh

SA41 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh

SA42 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh

SA43 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh

SA44 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh

SA45 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh

Bank 2

SA46 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh

SA47 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh

SA48 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh

SA49 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh

SA50 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

SA51 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh

SA52 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh

SA53 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh

SA 54 0 101111 xx x 64 /32 2 F0000h–2FFFFFh 178000h–17FFFFh

SA55 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh

SA56 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh

SA57 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh

SA58 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh

SA59 0110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh

SA60 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh

SA61 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh

SA62 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh

SA63 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh

SA64 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh

SA65 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh

SA66 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh

SA67 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh

SA68 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

Sector Address

A21–A12

Sector Size

(kbytes/kwords)

(x8)

Address Range

(x16)

Address Range

Document Number: 002-00856 Rev. *E Page 13 of 59

S29JL064J

S29JL064J Sector Architecture (Sheet 3 of 4)

Bank Sector

SA71 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh

SA72 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh

SA73 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh

SA74 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh

SA75 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh

SA76 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh

SA77 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh

SA78 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh

SA79 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh

SA80 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh

SA81 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh

SA82 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh

SA83 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh

SA84 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh

SA85 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh

SA 86 1 001111 xx x 64 /32 4 F0000h–4FFFFFh 278000h–27FFFFh

SA87 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh

SA88 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh

SA89 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh

SA90 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh

SA91 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh

SA92 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh

SA93 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh

Bank 3

SA94 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh

SA95 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh

SA96 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh

SA97 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh

SA98 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh

SA99 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh

SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh

SA101 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh

SA102 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh

SA103 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh

SA104 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh

SA105 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh

SA106 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh

SA107 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh

SA108 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh

SA109 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh

SA110 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh

SA111 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh

SA112 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh

SA113 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh

SA114 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh

SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh

SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh

Sector Address

A21–A12

Sector Size

(kbytes/kwords)

(x8)

Address Range

(x16)

Address Range

Document Number: 002-00856 Rev. *E Page 14 of 59

S29JL064J

S29JL064J Sector Architecture (Sheet 4 of 4)

Bank Sector

SA119 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh

SA120 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh

SA121 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh

SA122 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh

SA123 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh

SA124 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh

SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh

SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh

SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh

SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh

SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh

Bank 4

Note:

The address range is A21:A-1 in byte mode (BYTE# = V

SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh

SA 131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh

SA 132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh

SA 133 1111110xx x 64 /32 7 E0000h–7EFFFFh 3F0000h–3F7FFFh

SA 134 1111111000 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh

SA 135 1111111001 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh

SA 136 1111111010 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh

SA 137 1111111011 8/4 7 F6000h–7F7FFFh 3FB000h–3FBFFFh

SA 138 1111111100 8/4 7 F8000h–7F9FFFh 3FC000h–3FCFFFh

SA 139 1111111101 8/4 7FA 000 h–7FBFFFh 3FD000h–3FDFFFh

SA 140 1111111110 8/4 7F C000 h–7FDFFFh 3FE000h–3FEFFFh

SA 141 1111111111 8/4 7 FE000h–7FFFFFh 3FF000h–3FFFFFh

Sector Address

A21–A12

(kbytes/kwords)

Sector Size

) or A21:A0 in word mode (BYTE# = VIH).

(x8)

Address Range

(x16)

Address Range

Bank Address

Bank A21–A19

1 000

2 001, 010, 011

3 100, 101, 110

4 111

Secured Silicon Region Addresses

Device Sector Size

S29JL064J 256 bytes 000000h–0000FFh 000000h–00007Fh

(x8)

Address Range

(x16)

Address Range

Document Number: 002-00856 Rev. *E Page 15 of 59

S29JL064J

8.9 Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V

Table . In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits

(see Table on page 15). Table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the S29JL064J is erased or programmed

in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table on page 31. Note that if a

Bank Address (BA) on address bits A21, A20, and A19 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data from that bank and then immediately read array data from another bank, without exiting the autoselect mode.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table on page 31. This method does not require V

. Refer to Autoselect Command Sequence on page 27 for more information.

S29JL064J Autoselect Codes, (High Voltage Method)

on address pin A9. Address pins must be as shown in

A11

A21

A12

Description CE# OE# WE#

Manufacturer ID:

Spansion Products

Read Cycle 1

Read Cycle 2 L H H H L 22h 02h

Device ID

Read Cycle 3 L H H H H 22h 01h

Sector Protection

Verif ic atio n

Secured Silicon

Indicator Bit (DQ6,

DQ7)

Legend

L = Logic Low = V H = Logic High = V BA = Bank Address SA = Sector Address X = Don’t care.

LLHBAXV

LLHSAXV

LLHBAXV

A10 A9

A7 A6

XLXLLLL X X 01h

XLXLLHL X X

XLXLLHH X X

A5 to A4 A3 A2 A1 A0

LLLH 22h

DQ15 to DQ8

BYTE#

= V

BYTE#

= V

01h (protected),

00h (unprotected)

81h (Factory Locked),

41h (Customer

01h (Not Locked)

DQ7

DQ0

7Eh

Locked),

Document Number: 002-00856 Rev. *E Page 16 of 59

S29JL064J

8.10 Boot Sector/Sector Block Protection and Unprotection

Note: For the following discussion, the term sector applies to both boot sectors and sector blocks. A sector block consists of two or

more adjacent sectors that are protected or unprotected at the same time (see Table ).

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods.

S29JL064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 1 of 2)

Sector A21–A12 Sector/Sector Block Size

SA0 0000000000 8 kbytes

SA1 0000000001 8 kbytes

SA2 0000000010 8 kbytes

SA3 0000000011 8 kbytes

SA4 0000000100 8 kbytes

SA5 0000000101 8 kbytes

SA6 0000000110 8 kbytes

SA7 0000000111 8 kbytes

SA8–SA10

SA11–SA14 00001XXXXX 256 (4x64) kbytes

SA15–SA18 00010XXXXX 256 (4x64) kbytes

SA19–SA22 00011XXXXX 256 (4x64) kbytes

SA23–SA26 00100XXXXX 256 (4x64) kbytes

SA27-SA30 00101XXXXX 256 (4x64) kbytes

SA31-SA34 00110XXXXX 256 (4x64) kbytes

SA35-SA38 00111XXXXX 256 (4x64) kbytes

SA39-SA42 01000XXXXX 256 (4x64) kbytes

SA43-SA46 01001XXXXX 256 (4x64) kbytes

SA47-SA50 01010XXXXX 256 (4x64) kbytes

SA51-SA54 01011XXXXX 256 (4x64) kbytes

SA55–SA58 01100XXXXX 256 (4x64) kbytes

SA59–SA62 01101XXXXX 256 (4x64) kbytes

SA63–SA66 01110XXXXX 256 (4x64) kbytes

SA67–SA70 01111X XXXX 256 (4x64) kbytes

SA71–SA74 10000XXXXX 256 (4x64) kbytes

SA75–SA78 10001XXXXX 256 (4x64) kbytes

SA79–SA82 10010XXXXX 256 (4x64) kbytes

SA83–SA86 10011XXXXX 256 (4x64) kbytes

SA87–SA90 10100XXXXX 256 (4x64) kbytes

SA91–SA94 10101XXXXX 256 (4x64) kbytes

SA95–SA98 10110XXXXX 256 (4x64) kbytes

SA99–SA102 10111XXXXX 256 (4x64) kbytes

SA103–SA106 11000XXXXX 256 (4x64) kbytes

SA107–SA110 11001XXXXX 256 (4x64) kbytes

SA111–SA114 11010XXXXX 256 (4x64) kbytes

SA115–SA118 11011XXXXX 256 (4x64) kbytes

SA119–SA122 11100XXXXX 256 (4x64) kbytes

SA123–SA126 11101XXXXX 256 (4x64) kbytes

0000001XXX, 0000010XXX,

0000011XXX,

192 (3x64) kbytes

Document Number: 002-00856 Rev. *E Page 17 of 59

S29JL064J

S29JL064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 2 of 2)

Sector A21–A12 Sector/Sector Block Size

SA127–SA130 11110XXXXX 256 (4x64) kbytes

SA131–SA133

SA 1 34 11111110 0 0 8 k b yt e s

SA 1 35 11111110 0 1 8 k b yt e s

SA 1 36 11111110 1 0 8 k b yt e s

SA 1 37 1111111 011 8 k b yt e s

SA 1 38 11111111 00 8 k b yt e s

SA 1 39 11111111 01 8 k b yt e s

SA 1 40 111111111 0 8 k b yt e s

SA 1 41 1111111111 8 k byt e s

1111100XXX, 1111101XXX,

1111110 XXX

192 (3x64) kbytes

Sector Protect/Sector Unprotect requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 8.2 on page 20 shows the algorithms and Figure 17.13 on page 50 shows the timing diagram. For sector

unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See Temporary Sector Unprotect on page 19.

The device is shipped with all sectors unprotected. Optional Spansion programming service enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 16 for details.

8.11 Write Protect (WP#)

The Write Protect function provides a hardware method of protecting without using VID. This function is one of two provided by the WP#/ACC pin.

If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in sectors 0, 1, 140, and 141,

independently of whether those sectors were protected or unprotected using the method described in Boot Sector/Sector Block

Protection and Unprotection on page 17.

If the system asserts V or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or

unprotected using the method described in Boot Sector/Sector Block Protection and Unprotection on page 17.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

WP#/ACC Modes

WP# Input Voltage Device Mode

on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 140, and 141 were last set to be protected

Disables programming and erasing in SA0, SA1, SA140, and SA141

Enables programming and erasing in SA0, SA1, SA140, and SA141, dependent on whether they were last protected or unprotected.

Enables accelerated programming (ACC). See Accelerated Program Operation on page 10.

Document Number: 002-00856 Rev. *E Page 18 of 59

S29JL064J

8.12 Temporary Sector Unprotect

START

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = V

(Note 1)

Note: For the following discussion, the term sector applies to both sectors and sector blocks. A sector block consists of two or more

adjacent sectors that are protected or unprotected at the same time (see Table on page 17).

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Temporary Sector Unprotect mode is activated by setting the RESET# pin to V erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 8.1 shows the algorithm, and Figure 17.12 on page 49 shows the timing diagrams, for this feature. If the WP#/ACC pin is at V

, sectors 0, 1, 140, and 141 will remain protected during the Temporary sector Unprotect mode.

Figure 8.1 Temporary Sector Unprotect Operation

. During this mode, formerly protected sectors can be programmed or

Notes:

1. All protected sectors unprotected (If WP#/ACC = V

2. All previously protected sectors are protected once again.

, sectors 0, 1, 140, and 141 will remain protected).

Document Number: 002-00856 Rev. *E Page 19 of 59

S29JL064J

Figure 8.2 In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = V

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

All sectors protected?

Yes

Protect all sectors: The indicated portion of the sector protect

algorithm must be

performed for all unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm

Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

Document Number: 002-00856 Rev. *E Page 20 of 59

S29JL064J

8.13 Secured Silicon Region

The Secured Silicon Region feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Region is 256 bytes in length, and may shipped unprotected, allowing customers to utilize that sector in any manner they choose, or may shipped locked at the factory (upon customer request). The Secured Silicon Indicator Bit data will be 81h if factory locked, 41h if customer locked, or 01h if neither. Refer to Table on page 16 for more details.

The system accesses the Secured Silicon Region through a command sequence (see Enter Secured Silicon Region/Exit Secured

Silicon Region Command Sequence on page 27). After the system has written the Enter Secured Silicon Region command

sequence, it may read the Secured Silicon Region by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Region command sequence, or until power is removed from the

device. On power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Note

that the ACC function and unlock bypass modes are not available when the Secured Sili con Region is enabled.

8.13.1 Factory Locked: Secured Silicon Region Programmed and Protected At the Factory

In a factory locked device, the Secured Silicon Region is protected when the device is shipped from the factory. The Secured Silicon Region cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number is at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The secure ESN is programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–00001Fh in byte mode). The device is available preprogrammed with one of the following:

 A random, secure ESN only

 Customer code through Spansion programming services

 Both a random, secure ESN and customer code through Spansion programming services

Contact an your local sales office for details on using Spansion programming services.

8.13.2 Customer Lockable: Secured Silicon Region NOT Programmed or Protected At the Factory

If the security feature is not required, the Secured Silicon Region can be treated as an additional Flash memory space. The Secured Silicon Region can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Region.

 Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system sector protect algorithm as

or V

shown in Figure 8.2 on page 20, except that RESET# may be at either V

Silicon Region without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Region.

 To verify the protect/unprotect status of the Secured Silicon Region, follow the algorithm shown in Figure 8.3 on page 22.

Once the Secured Silicon Region is locked and verified, the system must write the Exit Secured Silicon Region command sequence to return to reading and writing the remainder of the array.

The Secured Silicon Region lock must be used with caution since, once locked, there is no procedure available for unlocking the Secured Silicon Region and none of the bits in the Secured Silicon Region memory space can be modified in any way.

. This allows in-system protection of the Secured

Document Number: 002-00856 Rev. *E Page 21 of 59

S29JL064J

Figure 8.3 Secured Silicon Region Protect Verify

START

RESET# =

or V

Wait 1 ms

Write 60h to

any address

Write 40h to Secure

Silicon Region address

with A6 = 0,

A1 = 1, A0 = 0

Read from Secure

Silicon Region address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

Secure Silicon Region

is unprotected.

If data = 01h,

Secure Silicon Region

is protected.

Remove VIH or VID

from RESET#

Secured Silicon Region

exit command

Secure Silicon Region

Protect Verify

complete

8.14 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table on page 31 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V power-down transitions, or from system noise.

power-up and

8.14.1 Low VCC Write Inhibit

When VCC is less than V The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than V unintentional writes when V

, the device does not accept any write cycles. This protects data during VCC power-up and power-down.

LKO

. The system must provide the proper signals to the control pins to prevent

is greater than V

LKO

8.14.2 Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

8.14.3 Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

8.14.4 Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

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S29JL064J

9. Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Table on page 23 to Table on page 25. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the autoselect mode via the command register only (high voltage method does not apply). The device enters the CFI query mode, and the system can read CFI data at the addresses given in

Table on page 23 to Table on page 25. The system must write the reset command to return to reading array data.

For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of these documents.

CFI Query Identification String

Addresses

(Word Mode)

10h 11h 12h

13h 14h

15h 16h

17h 18h

19h 1Ah

Addresses

(Byte Mode) Data Description

20h 22h 24h

26h 28h

2Ah 2Ch

2Eh 30h

32h 34h

0051h 0052h 0059h

0002h 0000h

0040h 0000h

0000h 0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

System Interface String

Addresses

(Word Mode)

1Bh 36h 0027h

1Ch 38h 0036h

1Dh 3Ah 0000h V

1Eh 3Ch 0000h V

1Fh 3Eh 0003h Typical timeout per single byte/word write 2

20h 40h 0000h Typical timeout for Min. size buffer write 2

21h 42h 0009h Typical timeout per individual block erase 2

22h 44h 000Fh Typical timeout for full chip erase 2

23h 46h 0004h Max. timeout for byte/word write 2

24h 48h 0000h Max. timeout for buffer write 2

25h 4Ah 0004h Max. timeout per individual block erase 2

26h 4Ch 0000h Max. timeout for full chip erase 2

Addresses

(Byte Mode) Data Description

Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

Min. voltage (00h = no VPP pin present)

Max. voltage (00h = no VPP pin present)

µs

µs (00h = not supported)

ms (00h = not supported)

times typical

times typical (00h = not supported)

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Device Geometry Definition

Addresses

(Word

Mode)

27h 4Eh 0017h Device Size = 2

28h 29h

2Ah 2Bh

2Ch 58h 0003h Number of Erase Block Regions within device

2Dh 2Eh 2Fh

30h

31h 32h 33h 34h

35h 36h 37h 38h

39h 3Ah 3Bh 3Ch

Addresses

(Byte Mode) Data Description

byte

50h 52h

54h 56h

5Ah 5Ch 5Eh

60h

62h 64h 66h 68h

6Ah 6Ch 6Eh

70h

72h 74h 76h 78h

0002h 0000h

0000h 0000h

0007h 0000h 0020h 0000h

007Dh 0000h 0000h 0001h

0007h 0000h 0020h 0000h

0000h 0000h 0000h 0000h

Flash Device Interface description (refer to the CFI publication 100)

Max. number of byte in multi-byte write = 2 (00h = not supported)

Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)

Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100)

Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)

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Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

40h 41h 42h

43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon)

44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table)

45h 8Ah 000Ch

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

4Ah 94h 0077h

4Bh 96h 0000h

4Ch 98h 0000h

4Dh 9Ah 0085h

4Eh 9Ch 0095h

4Fh 9Eh 0001h

50h A0h 0000h

57h AEh 0004h

58h B0h 0017h

59h B2h 0030h

Addresses

(Byte Mode) Data Description

80h 82h 84h

0050h 0052h 0049h

Query-unique ASCII string “PRI”

Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0011 = 0.11 µm Floating Gate

Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect 0 = Not Supported, X = Number of sectors per group

Sector Temporary Unprotect 00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode

Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1)

Burst Mode Type 00 = Not Supported, 01 = Supported

Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = 8 x 8 kbyte Sectors, Top And Bottom Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h= Both Top and Bottom

Program Suspend

0 = Not supported, 1 = Supported

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

Bank 1 Region Information

X = Number of Sectors in Bank 1

Bank 2 Region Information

X = Number of Sectors in Bank 2

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Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

5Ah B4h 0030h

5Bh B6h 0017h

Addresses

(Byte Mode) Data Description

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

10. Command Definitions

Writing specific address and data sequences into the command register initiates device operations. Table on page 31 defines the

valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place

the device in an unknown state. A reset command is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#

or CE#, whichever happens first. Refer to AC Characteristics on page 42 for timing diagrams.

10.1 Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same

exception. See Erase Suspend/Erase Resume Commands on page 30 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an

active program or erase operation, or if the bank is in the autoselect mode. See Reset Command on page 26 for more information. See Requirements for Reading Array Data on page 10 for more information. Read-Only Operations on page 42 provides the read

parameters, and Figure 17.1 on page 42 shows the timing diagram.

10.2 Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the bank to the read mode (or erasesuspend-read mode if that bank was in Erase Suspend). Please note that the RY/BY# signal remains low until this reset is issued.

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10.3 Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in another bank.

The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without re-initiating the command sequence.

Table on page 31 shows the address and data requirements. To determine sector protection information, the system must write to

the appropriate bank address (BA) and sector address (SA). Table on page 15 shows the address range and bank number associated with each sector.

The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).

10.4 Enter Secured Silicon Region/Exit Secured Silicon Region Command Sequence

The system can access the Secured Silicon Region by issuing the three-cycle Enter Secured Silicon Region command sequence. The device continues to access the Secured Silicon Region until the system issues the four-cycle Exit Secured Silicon Region command sequence. The Exit Secured Silicon Region command sequence returns the device to normal operation. The Secured Silicon Region is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table

on page 31 shows the address and data requirements for both command sequences. See also Secured Silicon Region on page 21 for

further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Region is

enabled.

10.5 Byte/Word Program Command Sequence

The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is

not required to provide further controls or timings. The device automatically provides internally generated program pulses and

verifies the programmed cell margin. Table on page 31 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched.

The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to Write Oper ation Status

on page 32 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately

terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read

mode, to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable when a program

operation is in progress.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be progra mmed from 0 back to a 1.

Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was

successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.

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10.5.1 Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table on page 31 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table on page 31).

The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V

for any operation other than accelerated programming, or device damage may result. In addition, the WP#/

ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Figure 10.1 on page 28 illustrates the algorithm for the program operation. Refer to Erase and Program Operations on page 45 for

parameters, and Figure 17.5 on page 46 for timing diagrams.

Figure 10.1 Program Operation

START

on the WP#/ACC pin,

Increment Address

Note:

1. See Table on page 31 for program command sequence.

Embedded

Program

algorithm

in progress

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Last Address?

Programming

Completed

Yes

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10.6 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the

Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table on page 31 shows the address and data requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The

system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status

on page 32 for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates

the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable when an

erase operation is in progress.

Figure 10.2 on page 30 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 45 for

parameters, and Figure 17.7 on page 47 for timing diagrams.

10.7 Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table on page 31 shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and

verifies the entire sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. However, these additional erase commands are only one bus cycle long and should be identical to the sixth cycle of the standard erase command explained above. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input during the time-out period, the normal operation will not be guaranteed. The system must rewrite the command

sequence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# or CE# pulse (first rising edge) in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can

determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to Write Operation

Status on page 32 for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However,

note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured Silicon Region,

autoselect, and CFI functions are unavailable when an erase operation is in progress.

Figure 10.2 on page 30 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 45 for

parameters, and Figure 17.7 on page 47 for timing diagrams.

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Notes:

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded Erase algorithm in progress

1. See Table on page 31 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

10.8 Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. The bank address must contain one of the sectors currently selected for erase.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.

After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or

program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) It is not

recommended to program the Secured Silicon Region after an erase suspend, as proper device functionality cannot be guaranteed. Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or

DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Write Operation Status

on page 32 for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation.

Refer to Write Operation Status on page 32 for more information.

In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to

Autoselect Mode on page 16 and Autoselect Command Sequence on page 27 for details.

To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erasesuspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Figure 10.2 Erase Operation

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S29JL064J Command Definitions

Command Sequence

(Note 1)

Read (Note 6) 1RA RD

Reset (Note 7) 1XXX F0

Manufacturer ID

Device ID (Note 9)

Secured Silicon Region Factory Protect (Note 10)

Autoselect (Note 8)

Boot Sector/Sector Block Protect Verify

(Note 11)

Enter Secured Silicon Region

Exit Secured Silicon Region

Program

Unlock Bypass

Unlock Bypass Program (Note 12) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 13) 2 XXX 90 XXX 00

Chip Erase

Sector Erase (Note 17)

Erase Suspend (Note 14) 1BA B0

Erase Resume (Note 15) 1BA 30

CFI Query (Note 16)

Legend

X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Addre ss bits A21–A12 uniquely select any sector. Refer to Table on page 15 for information on

sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A21–A19 uniquely select a bank.

Notes:

1. See Table on page 9 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.

5. Unless otherwise noted, address bits A21–A11 are don’t cares for unlock and command cycles, unless SA or PA is required.

6. No unlock or command cycles required when bank is reading array data.

7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect

mode, or if DQ5 goes high (while the bank is providing status information).

Word

Byte AAA 555 (BA)AAA

Word

Byte AAA 555 (BA)AAA (BA)X02 (BA)X1C (BA)X1E

Word

Byte AAA 555 (BA)AAA (BA)X06

Word

Byte AAA 555 (BA)AAA (SA)X04

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555

Word

Byte AA

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

555

2AA

Bus Cycles (Notes 2–5)

(BA)555

555

90 (BA)X00 01

(BA)X01

(BA)X03

(SA)X02

90 XXX 00

A0 PA PD

555

81/41/

00/01

(BA)X0E

2AA

(BA)X0F

555

55 SA 30

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8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or Secur ed

Silicon Region factory protect information. Data bits DQ15–DQ8 are don’t care. While reading the autoselect addresses, the bank address must be the same until a reset command is given. See Autoselect Command Sequence on page 27 for more information.

9. The device ID must be read across the fourth, fifth, and sixth cycles.

10.The data is 81h for factory locked, 41h for customer locked, and 01h for not factory/customer locked.

11.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.

12.The Unlock Bypass command is required prior to the Unlock Bypass Program command.

13.The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode.

14.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid

only during a sector erase operation, and requires the bank address.

15.The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.

16.Command is valid when device is ready to read array data or when device is in autoselect mode.

17.Additional sector erase commands during the time-out period after an initial sector erase are one cycle long and identical to the sixth cycle of

the sector erase command sequence (SA / 30).

11. Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table

on page 37 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining

whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/ BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.

11.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of

the sectors selected for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 3 ms, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.

When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 (or DQ7–DQ0

for x8-only device) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may

change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-only device) while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on successive read cycles.

Table on page 37 shows the outputs for Data# Polling on DQ7. Figure 11.1 on page 33 shows the Data# Polling algorithm. Figure 17.9 on page 48 shows the Data# Polling timing diagram.

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Figure 11. 1 Data# Polling Algorithm

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9E S

$1åå

9E S

&!),

0!33

2EADå$1n$1

!DDRåå6!

2EADå$1n$1

!DDRåå6!

$1åå$ATA

34!24

Notes:

1. VA = Valid address for programming. During a se ctor erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

11.2 RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode.

Table on page 37 shows the outputs for RY/BY#.

When DQ5 is set to “1”, RY/BY# will be in the BUSY state, or “0”.

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11.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 3 ms, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-

suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 32).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

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Figure 11.2 Toggle Bit Algorithm

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Toggle Bit

= Toggle?

Read Byte Twice

(DQ7–DQ0)

Address = VA

Read Byte

(DQ7–DQ0)

Address =VA

Read Byte

(DQ7–DQ0)

Address =VA

Note:

The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop tog gling as DQ5 changes to 1. S ee the su bsections on DQ 6 and DQ2 for more information.

11.4 DQ2: Toggle Bit II

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded

Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table

on page 37 to compare outputs for DQ2 and DQ6.

Figure 11.2 on page 35 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 35 explains the algorithm.

See also DQ6: Toggle Bit I on page 34. Figure 17.10 on page 48 shows the toggle bit timing diagram. Figure 17.11 on page 49

shows the differences between DQ2 and DQ6 in graphical form.

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11.5 Reading Toggle Bits DQ6/DQ2

Refer to Figure 11.2 on page 35 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 11.2 on page 35).

11.6 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5

produces a 1, indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0. Only an

erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1.

Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).

11.7 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also

applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time

between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor

DQ3. See also Sector Erase Command Sequence on page 29.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure

that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device will accept

additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. The RDY/BSY# pin will be in the BUSY state under this condition.

Table on page 37 shows the status of DQ3 relative to the other status bits.

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Write Operation Status

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

Status

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Standard Mode

Erase Suspend Mode

Notes:

1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timi ng limits. Refer to the section on DQ5 for more

information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array

data if the system addresses a non-busy bank.

Embedded Erase Algorithm

Erase-Suspend-Read

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

in busy erasing sector 0 Toggle 0 1 Toggle 0

in not busy erasing sector

Erase Suspended Sector

Non-Erase Suspended Sector

DQ7

(Note 2) DQ6

0 Toggle 0 1 No toggle 0

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

12. Absolute Maximum Ratings

Storage Temperature, Plastic Packages –65°C to +150°C

Ambient Temperature with Power Applied –65°C to +125°C

Voltage with Respect to Ground

(Note 1) –0.5V to +4.0V

A9 and RESET# (Note 2) –0.5V to +12.5V

WP#/ACC –0.5V to +9.5V

All other pins (Note 1) –0.5V to V

Output Short Circuit Current (Note 3) 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5V. During voltage transitions, input or I/O pins may overshoot V

voltage on input or I/O pins is V See Figure 12.2 on page 38.

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V

2.0V for periods of up to 20 ns. See Figure 12.1 on page 37. Maximum DC input voltage on pin A9 is +12.5V which may overshoot to +14.0V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5V which may overshoot to +12.0V for periods up to 20ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operationa l sections of this dat a sheet is n ot implied. Exposur e of the device to absolute maximum rating conditions for extended periods may affect device reliability.

+0.5V. See Figure12.1 on page 37. During voltage transitions, input or I/O pins may overshoot to VCC +2.0V for periods up to 20 ns.

+0.5V

to –2.0V for periods of up to 20 ns. Maximum DC

to –

Figure 12.1 Maximum Negative Overshoot Waveform

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Figure 12.2 Maximum Positive Overshoot Waveform

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

13. Operating Ranges

Industrial (I) Devices

Ambient Temperature (TA) –40°C to +85°C

VCC Supply Voltages

VCC for standard voltage range 2.7V to 3.6V

Operating ranges define those limits between which the functionality of the device is guaranteed.

14. DC Characteristics

14.1 CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

= VSS to VCC,

= VCC

RESET# = 12.5V

OUT

CE# = V Mode

CE# = V

OE# = VIH, 1 MHz

CE# = V

OE# = V

CE# = V

max

= V

, OE# = VIH; A9 or

CC max

= VSS to VCC,

= V

, OE# = V

CC max

; RESET# = 12.5V 35 µA

CC max

OE# = VIH, Byte

IL,

5 MHz 10 16

1MHz 2 4

OE# = VIH, Word

IL,

5 MHz 10 16

1MHz 2 4

OE# = VIH, WE# = V

IL,

= V

 0.3V;

= V

0.3V

IL,

0.3V 0.2 5 µA

Byte 21 45

15 30 mA

0.2 5 µA

Word 21 45

, 1 MHz

, OE# = V

Byte 21 45

Word 21 45

17 35 mA

= 3.0V ± 10% 8.5 9.5 V

1.0 µA

35 µA

1.0 µA

VCC + 0.3 V

CC1

CC2

CC3

CC4

CC5

CC6

CC7

CC8

Input Load Current

A9 and RESET# Input Load Current

LIT

Output Leakage Current

Reset Leakage Current VCC = V

VCC Active Read Current (Notes 1, 2)

VCC Active Write Current (Notes 2, 3)CE# = V

VCC Standby Current (Note 2) CE#, RESET# = VCC 0.3V 0.2 5 µA

VCC Reset Current (Note 2) RESET# = V

Automatic Sleep Mode (Notes 2, 4)

VCC Active Read-While-Program Current (2)

VCC Active Read-While-Erase Current (2)

VCC Active Program-While-Erase-Suspended Current (Notes 2, 5)

Input Low Voltage –0.5 0.8 V

Input High Voltage 0.7 x V

Voltage for WP#/ACC Sector Protect/Unprotect and

Program Acceleration

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Parameter

0 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

Symbol Parameter Description Test Conditions Min Typ Max Unit

Notes:

1. The I

2. Maximum I

3. I

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

5. Not 100% tested.

Voltage for Autoselect and Temporary Sector

Unprotect

Output Low Voltage IOL = 2.0 mA, VCC = V

OH1

Output High Voltage

OH2

Low VCC Lock-Out Voltage (Note 5) 1.8 2.0 2.5 V

LKO

current listed is typically less than 2 mA/MHz, with OE# at VIH.

specifications are tested with VCC = VCCmax.

active while Embedded Erase or Embedded Program is in progress.

= 3.0V  10% 8.5 12.5 V

0.45 V

CC min

= –2.0 mA, VCC = V

IOH = –100 µA, VCC = V

ACC

0.85 V

CC min

+ 30 ns. Typical sleep mode current is 200 nA.

–0.4

14.2 Zero-Power Flash

Note:

Addresses are switching at 1 MHz

Figure 14.1 I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

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Figure 14.2 Typical I

12345

Frequency in MHz

Supply Current in mA

2.7V

3.6V

Device

Under

Te st

vs. Frequency

CC1

Note:

T = 25°C

15. Test Conditions

Test Specifications

Test Condition 55, 60 70 Unit

Output Load Capacitance, C

Input Rise and Fall Times (Note 1) 5ns

Input Pulse Levels 0.0 or V

Input timing measurement reference levels 0.5 V

Output timing measurement reference levels 0.5 V

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Figure 15.1 Test Setup

30 100 pF

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Note:

1. Input rise and fall times are 0-100%.

16. Key To Switching Waveforms

Waveform Inputs Outputs

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High-Z)

Figure 16.1 Input Waveforms and Measurement Levels

Steady

Changing from H to L

Changing from L to H

3.0V

0.0V

1.5V 1.5V

OutputMeasurement LevelInput

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17. AC Characteristics

Outputs

WE#

Addresses

CE#

OE#

High-Z

Output Valid

High-Z

Addresses Stable

ACC

OEH

0 V

RY/BY#

RESET#

17.1 Read-Only Operations

Parameter

JEDEC Std. 55 60 70 Unit

AVAVtRC

AVQ VtACC

ELQVtCE

GLQVtOE

EHQZtDF

GHQZtDF

AXQXtOH

Notes:

1. Not 100% tested.

2. See Figure 15.1 on page 40 and Table on page 40 for test specifications

3. Measurements performed by placing a 50 ohm termination on the dat a pin with a bias of V

Read Cycle Time (Note 1) Min556070ns

Address to Output Delay

Chip Enable to Output Delay OE# = VILMax556070ns

Output Enable to Output Delay Max 25 30 ns

Chip Enable to Output High-Z (Notes 1, 3) Max 16 ns

Output Enable to Output High-Z (Notes 1, 3) Max 16 ns

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First

Output Enable Hold Time

OEH

(Note 1)

Description Test Setup

CE#,

OE# = V

Read Min 0 ns

Toggle and Data# Polling

Max556070ns

Min 0 ns

Min 5 10 ns

Speed Options

/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF.

Figure 17.1 Read Operation Timings

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17.2 Hardware Reset (RESET#)

RESET#

RY/BY#

Ready

Reset Timings NOT during Embedded Algorithms

Ready

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

Parameter

Description All Speed Options UnitJEDEC Std

RESET# Pin Low (During Embedded Algorithms) to Read

Ready

Mode (See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to

Ready

Read Mode (See Note)

RESET# Pulse Width Min 500 ns

Reset High Time Before Read (See Note) Min 50 ns

RESET# Low to Standby Mode Min 35 µs

RPD

RY/BY# Recovery Time Min 0 ns

Note:

Not 100% tested.

Max 35 µs

Max 500 ns

Figure 17.2 Reset Timings

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17.3 Word/Byte Configuration (BYTE#)

DQ15

Output

Data Output (DQ7–DQ0)

CE#

OE#

BYTE#

ELFL

DQ14–DQ0

Data Output

(DQ14–DQ0)

DQ15/A-1

Address

Input

FLQZ

BYTE# Switching from word

to byte

DQ15

Output

Data

BYTE#

ELFH

DQ14–DQ0

Data Output

(DQ14–DQ0)

DQ15/A-1

Address

Input

FHQV

BYTE# Switching

from byte

to word

mode

CE#

WE#

BYTE#

The falling edge of the last WE# signal

HOLD

(tAH)

SET

(tAS)

Parameter

ELFL/tELFH

FLQZ

FHQV

Speed Options

Description

CE# to BYTE# Switching Low or High Max 5 ns

BYTE# Switching Low to Output High-Z Max 16 ns

BYTE# Switching High to Output Active Min 55 60 70 ns

UnitJEDEC Std. 556070

Figure 17.3 BYTE# Timings for Read Operations

Figure 17.4 BYTE# Timings for Write Operations

Note:

Refer to the Erase/Program Operations table for t

and tAH specifications.

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17.4 Erase and Program Operations

Parameter

Description

AVAV

AVW L

WLAX

DVWH

WHDX

GHWL

ELWL

WHEH

WLWH

WHDL

WHWH1

WHWH2

GHWL

WHWH1

WHWH2

Write Cycle Time (Note 1) Min556070ns

Address Setup Time Min 0 ns

Address Setup Time to OE# low during toggle bit polling Min 15 ns

ASO

Address Hold Time Min 30 35 40 ns

Address Hold Time From CE# or OE# high

AHT

during toggle bit polling

Data Setup Time Min 30 35 40 ns

Data Hold Time Min 0 ns

Output Enable High during toggle bit polling Min 20 ns

OEPH

Read Recovery Time Before Write (OE# High to WE# Low)

CE# Setup Time Min 0 ns

CE# Hold Time Min 0 ns

Write Pulse Width Min 25 25 30 ns

Write Pulse Width High Min 25 25 30 ns

WPH

Latency Between Read and Write Operations Min 0 ns

SR/W

Programming Operation (Note 2)

Accelerated Programming Operation, Word or Byte (Note 2)

Sector Erase Operation (Note 2) Typ 0.5 sec

VCC Setup Time (Note 1) Min 50 µs

VCS

Write Recovery Time from RY/BY# Min 0 ns

Program/Erase Valid to RY/BY# Delay Max 90 ns

BUSY

Erase Suspend Latency Max 35 µs

ESL

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance on page 52 for more information.

Speed Options

Min 0 ns

Byte Typ 6

Word Typ 6

Typ 4 µs

UnitJEDEC Std 55 60 70

µs

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Figure 17.5 Program Operation Timings

OE#

WE#

CE#

Data

Addresses

WHWH1

WPH

VCS

555h

PA PA

Read Status Data (last two cycles)

A0h

Status

OUT

Program Command Sequence (last two cycles)

RY/BY#

BUSY

WP#/ACC

VHH

or V

VIL or V

VHH

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

is the true data at the program address.

OUT

Figure 17.6 Accelerated Program Timing Diagram

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Figure 17.7 Chip/Sector Erase Operation Timings

OE#

CE#

Addresses

WE#

Data

2AAh SA

WPH

555h for chip erase

10 for Chip Erase

30h

VCS

55h

Progress

Complete

WHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

BUSY

OE#

CE#

WE#

Addresses

Data

Valid

Valid PA

Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# or CE2# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA

CPH

Read Cycle

SR/W

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 32).

2. These waveforms are for the word mode.

Figure 17.8 Back-to-back Read/Write Cycle Timings

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Figure 17.9 Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ7

DQ0–DQ6

RY/BY#

BUSY

Complement

True

Addresses

OEH

VA VA

Status Data

Complement

Status Data

True

Valid Data

ACC

Note:

VA = Valid address. Illustration shows first status cycle after command sequence, l ast status read cycle, and array data read cycle

Figure 17.10 Toggle Bit Timings (During Embedded Algorithms)

AHT

Addresses

ASO

AHT

CE#

CPH

WE#

OEH

OEPH

OE#

DQ6/DQ2 Valid Data

Valid Data

Val id

Status

Val id

Status

Val id

Status

(first read) (second read) (stops toggling)

RY/BY#

Note:

VA = Valid add ress; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

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Figure 17.11 DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read

Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

VIDR

VSS, VIL, or V

VSS, VIL,

or V

CE#

WE#

RY/BY#

VIDR

RSP

Program or Erase Command Sequence

RRB

Note:

DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

17.5 Temporary Sector Unprotect

Parameter

Description All Speed OptionsJEDEC Std Unit

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

Rise and Fall Time (See Note) Min 250 ns

RESET# Setup Time for Temporary Sector Unprotect Min 4 µs

RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect

Min 4 µs

Note:

Not 100% tested.

VHHVHH

RSP

RRB

Figure 17.12 Temporary Sector Unprotect Timing Diagram

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Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Group Protect/Unprotect Verify

Note:

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

17.6 Alternate CE# Controlled Erase and Program Operations

Parameter Speed Options

JEDEC Std. Description 55 60 70 Unit

AVAV

AVW L

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

WHWH1

WHWH2

GHEL

CPH

WHWH1

WHWH2

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance on page 52 for more information.

Write Cycle Time (Note 1) Min556070ns

Address Setup Time Min 0 ns

Address Hold Time Min 30 35 40 ns

Data Setup Time Min 30 35 40 ns

Data Hold Time Min 0 ns

Read Recovery Time Before Write (OE# High to WE# Low)

Min 0 ns

WE# Setup Time Min 0 ns

WE# Hold Time Min 0 ns

CE# Pulse Width Min 25 25 40 ns

CE# Pulse Width High Min 25 25 30 ns

Programming Operation

(Note 2)

Accelerated Programming Operation, Word or Byte (Note 2)

Sector Erase Operation (Note 2) Typ 0.5 sec

Byte Typ 6

Word Typ 6

Typ 4 µs

µs

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Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings

GHEL

OE#

CE#

WE#

RESET#

Data

Addresses

DQ7# D

OUT

CPH

Data# Polling

A0 for program 55 for erase

WHWH1 or 2

RY/BY#

PD for program 30 for sector erase 10 for chip erase

555 for program 2AA for erase

PA for program SA for sector erase 555 for chip erase

BUSY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

4. Waveforms are for the word mode.

is the data written to the device.

OUT

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18. Erase and Programming Performance

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.5 5 sec

Chip Erase Time 71 sec

Byte Program Time 6 80 µs

Word Program Time 6 80 µs

Accelerated Byte/Word Program Time 4 70 µs

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0V V

2. Under worst case conditions of 90°C, V

3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

4. System-level overhead is the time required to execute the two- or four -bus-cycle sequence for the program command. See Table on page 31 for further information on command definitions.

5. The device has a minimum program and erase cycle endurance of 100,000 cycles per sector.

= 2.7V, 1,000,000 cycles.

, 100,000 cycles; checkerboard data pattern.

Excludes 00h programming

prior to erasure (Note 3)

Excludes system level

overhead (Note 4)

19. Pin Capacitance

Parameter Symbol Parameter Description Test Setup Max Unit

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

Input Capacitance (applies to A21-A0, DQ15-DQ0) VIN = 0 8.5 pF

Output Capacitance (applies to DQ15-DQ0, RY/BY#) V

Control Pin Capacitance

(applies to CE#, WE#, OE#, WP#/ACC, RESET#, BYTE#)

= 0 5.5 pF

OUT

= 0 12 pF

Document Number: 002-00856 Rev. *E Page 52 of 59

S29JL064J

20. Physical Dimensions

3664 \ f16-038.10 \ 11.6.7

PACKAGE TS/TSR 48 JEDEC MO-142 (D) DD SYMBOL MIN NOM MAX

A --- --- 1.20 A1 0.05 --- 0.15 A2 0.95 1.00 1.05 b1 0.17 0.20 0.23

b 0.17 0.22 0.27

c1 0.10 --- 0.16

c 0.10 --- 0.21

D 19.80 20.00 20.20 D1 18.30 18.40 18.50

E 11.90 12.00 12.10

e 0.50 BASIC

L 0.50 0.60 0.70 Θ 0˚ --- 8 R 0.08 --- 0.20 N48

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1982)

2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.

4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE.

6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm (0.0028").

7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10mm (.0039") AND 0.25mm (0.0098") FROM THE LEAD TIP.

8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

20.1 TS 048—48-Pin Standard TSOP

Document Number: 002-00856 Rev. *E Page 53 of 59

S29JL064J

20.2 VBK048—48-Pin FBGA

g1001.2 \ f16-038.25 \ 07.13.10

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN  THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBK 048

JEDEC N/A

8.15 mm x 6.15 mm NOM PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.18 --- --- BALL HEIGHT

D 8.15 BSC. BODY SIZE

E 6.15 BSC. BODY SIZE

D1 5.60 BSC. BALL FOOTPRINT

E1 4.00 BSC. BALL FOOTPRINT

MD 8 ROW MATRIX SIZE D DIRECTION

ME 6 ROW MATRIX SIZE E DIRECTION

N 48 TOTAL BALL COUNT

φb 0.33 --- 0.43 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

--- DEPOPULATED SOLDER BALLS

Document Number: 002-00856 Rev. *E Page 54 of 59

S29JL064J

21. Revision History

Spansion Publication Number: S29JL064J_00

Section Description

Revision 01 (June 21, 2010)

Initial revision.

Revision 02 (September 1, 2010)

Global

Simultaneous Read/Write Operations with Zero Latency

Ordering Information Clarified that Note 1 applies to the Packing Type column.

Device Bus Operation The note for the Addresses column should be Note 1, not Note 2.

RESET#: Hardware Reset Pin

Secured Silicon Region

Common Flash Memory Interface (CFI)

Enter Secured Silicon Region/Exit Secured Silicon Region Command Sequence

Erase Suspend/Erase Resume Commands

Erase and Programming Performance Added Note 5 regarding minimum program and erase cycle endurance.

Pin Capacitance

Physical Dimensions Updated the VBK048 package outline drawing.

Revision 03 (April 7, 2011)

Global

RESET#: Hardware Reset Pin

Reset Command

Absolute Maximum Ratings Corrected the maximum value of WP#/ACC voltage with respect to ground from +10.5V to +9.5V

DC Characteristics

Test Conditions

Hardware Reset (RESET#)

Updated the data sheet designation from Advanced Information to Preliminary.

Corrected spelling, capitalization, and grammatical errors.

Added clarification that JL064J is only offered as a dual boot device with both top and bottom boot sectors.

Changed “Refer to AC Characteristics on page 46” to “Refer to Hardware Reset (RESET#) on page 47”.

Clarified the Secured Silicon Indicator Bit data based on factory and customer lock status.

Removed forward looking statements regarding factory locking features as they are supported in this device.

Clarified that once in the CFI query mode, the system must write the reset command to return to reading array data.

Removed the incorrect generalizing statement that the Secured Silicon Region always contains an ESN.

Added clarification that “It is not recommended to program the Secured Silicon Region after an erase suspend, as proper device functionality cannot be guaranteed.”

In Table 10.1, corrected the Secured Silicon Region Factory Protect fourth cycle data from 81/01 to 81/41/01.

Changed section title from “TSOP Pin Capacitance” to “Pin Capacitance”.

Updated values to reflect maximum capacitances for both TSOP and BGA.

Removed typical capacitance values.

Added specific pin clarifications to parameter descriptions.

Updated the data sheet designation from Preliminary to Full Production (no designation on document).

Added warning that keeping CE# at V erroneuous data on the first read.

Clarified that during an embedded program or erase, if DQ5 goes high then RY/BY# will remain low until a reset is issued

Corrected voltage for autoselect and temporary sector unprotect (V

8.5V

Changed the format of the input pulse levels and input and output timing measurement reference levels to match the JL032J data sheet format

Added note to “Reset Timings” figure clarifying that CE# should only go low after RESET# has gone high.

from power up through the first reset could cause

) minimum value from 11.5V to

Document Number: 002-00856 Rev. *E Page 55 of 59

S29JL064J

Section Description

Revision 04 (August 24, 2011)

RESET#: Hardware Reset Pin

Sector Erase Command Sequence Added clarification regarding additional sector erase commands during time-out period.

Command Definitions Table Added Note 17 to clarify additional sector erase commands during time-out period.

Hardware Reset (RESET#)

Erase and Programming Performance Updated Byte Program Time and Word Program Time to 80 µs.

Physical Dimensions Package drawings updated to latest version.

Revision 05 (December 16, 2011)

Global Corrected all references in the text to the sector erase time-out period from 80 µs to 50 µs.

Removed warning that keeping CE# at V erroneuous data on the first read.

Removed note to the “Reset Timings” figure clarifying that CE# should only go low after RESET# has gone high.

from power up through the first reset could cause

Document History Page

Document Title:S29JL064J 64 Mbit (8M x 8-Bit/4M x 16-Bit), 3 V , Simultaneous Read/Write Flash Document Number: 002-00856

Rev. ECN No.

Orig. of

Change

** - RYSU 06/21/2010 Initial release

Submission

Date

Description of Change

Document Number: 002-00856 Rev. *E Page 56 of 59

S29JL064J

Document History Page (Continued)

Document Title:S29JL064J 64 Mbit (8M x 8-Bit/4M x 16-Bit), 3 V , Simultaneous Read/Write Flash Document Number: 002-00856

Rev. ECN No.

*A - RYSU 09/01/2010

Orig. of

Change

Submission

Date

Description of Change

Global

Updated the data sheet designation from Advanced Information to Preliminary.Corrected spelling, capitalization, and grammatical errors.

Simultaneous Read/Write Operations with Zero Latency

Added clarification that JL064J is only offered as a dual boot device with both top and bottom boot sectors.

Ordering Information Clarified that Note 1 applies to the Packing Type

column.

Device Bus Operation The note for the Addresses column should be Note

1, not Note 2.

RESET#: Hardware Reset Pin

Changed “Refer to AC Characteristics on page 46” to “Refer to Hardware Reset (RESET#) on page 47”.

Secured Silicon Region

Clarified the Secured Silicon Indicator Bit data based on factory and customer lock status. Removed forward looking statements regarding factory locking features as they are supported in this device.

Common Flash Memory Interface (CFI)

Clarified that once in the CFI query mode, the system must write the reset command to return to reading array data.

Enter Secured Silicon Region/Exit Secured Silicon Region Command Sequence

Removed the incorrect generalizing statement that the Secured Silicon Region always contains an ESN.

Erase Suspend/Erase Resume Commands

Added clarification that “It is not recommended to program the Secured Silicon Region after an erase suspend, as proper device functionality cannot be guaranteed.” In Table 10.1, corrected the Secured Silicon Region Factory Protect fourth cycle data from 81/01 to 81/41/01.

Erase and Programming Performance Added Note 5 regarding minimum

program and erase cycle endurance.

Pin Capacitance

Changed section title from “TSOP Pin Capacitance” to “Pin Capacitance”. Updated values to reflect maximum capacitances for both TSOP and BGA. Removed typical capacitance values. Added specific pin clarifications to parameter descriptions.

Physical Dimensions Updated the VBK048 package outline drawing.

Document Number: 002-00856 Rev. *E Page 57 of 59

S29JL064J

Document History Page (Continued)

Document Title:S29JL064J 64 Mbit (8M x 8-Bit/4M x 16-Bit), 3 V , Simultaneous Read/Write Flash Document Number: 002-00856

Rev. ECN No.

*B - RYSU 04/07/2011

*C - RYSU 08/24/2011

*D - RYSU 12/16/2011 Global

*E 5038713 RYSU 12/08/2015 Updated to Cypress Template.

Orig. of

Change

Submission

Date

Description of Change

Global

Updated the data sheet designation from Preliminary to Full Production (no designation on document).

RESET#: Hardware Reset Pin

Added warning that keeping CE# at VIL from power up through the first reset could cause erroneuous data on the first read.

Reset Command

Clarified that during an embedded program or erase, if DQ5 goes high then RY/BY# will remain low until a reset is issued

Absolute Maximum Ratings Corrected the maximum value of WP#/ACC

voltage with respect to ground from +10.5V to +9.5V

DC Characteristics

Corrected voltage for autoselect and temporary sector unprotect (VID) minimum value from 11.5V to 8.5V

Test Conditions

Changed the format of the input pulse levels and input and output timing measurement reference levels to match the JL032J data sheet format

Hardware Reset (RESET#)

Added note to “Reset Timings” figure clarifying that CE# should only go low after RESET# has gone high.

RESET#: Hardware Reset Pin

Removed warning that keeping CE# at VIL from power up through the first reset could cause erroneuous data on the first read.

Sector Erase Command Sequence Added clarification regarding

additional sector erase commands during time-out period.

Command Definitions Table Added Note 17 to clarify additional sector

erase commands during time-out period.

Hardware Reset (RESET#)

Removed note to the “Reset Timings” figure clarifying that CE# should only go low after RESET# has gone high.

Erase and Programming Performance Updated Byte Program Time and

Word Program Time to 80 μs.

Physical Dimensions Package drawings updated to latest version

Corrected all references in the text to the sector erase time-out period from 80 μs to 50 μs.

Document Number: 002-00856 Rev. *E Page 58 of 59

S29JL064J

Sales, Solutions, and Legal Information

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© Cypress Semiconductor Corporation, 2010-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 002-00856 Rev. *E Revised December 08, 2015 Page 59 of 59

Cypress®, Spansion®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.

Cypress Semiconductor S29JL064J User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Distinctive Characteristics

General Description

Contents

1. Simultaneous Read/Write Operations with Zero Latency

1.1 S29JL064J Features

2. Product Selector Guide

3. Block Diagram

4. Connection Diagrams

4.1 48-pin TSOP Package

Figure 4.1 48-Pin Standard TSOP

4.2 48-ball FBGA Package

Figure 4.2 48-ball FBGA

5. Pin Description

6. Logic Symbol

7. Ordering Information

8. Device Bus Operations

S29JL064J Device Bus Operations

8.1 Word/Byte Configuration

8.2 Requirements for Reading Array Data

8.3 Writing Commands/Command Sequences

8.3.1 Accelerated Program Operation

8.3.2 Autoselect Functions

8.4 Simultaneous Read/Write Operations with Zero Latency

8.5 Standby Mode

8.6 Automatic Sleep Mode

8.7 RESET#: Hardware Reset Pin

8.8 Output Disable Mode

S29JL064J Sector Architecture (Sheet 1 of 4)

Bank Address

Secured Silicon Region Addresses

8.9 Autoselect Mode

S29JL064J Autoselect Codes, (High Voltage Method)

8.10 Boot Sector/Sector Block Protection and Unprotection

S29JL064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 1 of 2)

8.11 Write Protect (WP#)

WP#/ACC Modes

8.12 Temporary Sector Unprotect

Figure 8.1 Temporary Sector Unprotect Operation

Figure 8.2 In-System Sector Protect/Unprotect Algorithms

8.13 Secured Silicon Region

8.13.1 Factory Locked: Secured Silicon Region Programmed and Protected At the Factory

8.13.2 Customer Lockable: Secured Silicon Region NOT Programmed or Protected At the Factory

Figure 8.3 Secured Silicon Region Protect Verify

8.14 Hardware Data Protection

8.14.1 Low VCC Write Inhibit

8.14.2 Write Pulse Glitch Protection

8.14.3 Logical Inhibit

8.14.4 Power-Up Write Inhibit

9. Common Flash Memory Interface (CFI)

CFI Query Identification String

System Interface String

Device Geometry Definition

Primary Vendor-Specific Extended Query

10. Command Definitions

10.1 Reading Array Data

10.2 Reset Command

10.3 Autoselect Command Sequence

10.4 Enter Secured Silicon Region/Exit Secured Silicon Region Command Sequence

10.5 Byte/Word Program Command Sequence

10.5.1 Unlock Bypass Command Sequence

Figure 10.1 Program Operation

10.6 Chip Erase Command Sequence

10.7 Sector Erase Command Sequence

10.8 Erase Suspend/Erase Resume Commands

Figure 10.2 Erase Operation

S29JL064J Command Definitions

11. Write Operation Status

11.1 DQ7: Data# Polling

Figure 11. 1 Data# Polling Algorithm

11.2 RY/BY#: Ready/Busy#

11.3 DQ6: Toggle Bit I

Figure 11.2 Toggle Bit Algorithm

11.4 DQ2: Toggle Bit II

11.5 Reading Toggle Bits DQ6/DQ2

11.6 DQ5: Exceeded Timing Limits

11.7 DQ3: Sector Erase Timer