Cypress Semiconductor PALCE22V10-25PC, PALCE22V10-25PI, PALCE22V10-5PC, PALCE22V10-7JC, PALCE22V10-7PC Datasheet

22V10

PALCE22V10

Flash Erasable,

Reprogrammable CMOS PAL® Device

Features

• Low power

—90 mA max. commercial (10 ns)
—130 mA max. commercial (5 ns)

• CMOS Flash EPROM technology f or electrical erasabil-

ity and reprogrammability

• Variable product terms

—2 x (8 through 16) product terms

• User-programmable macrocell

—Output polarity control
—Individually selectable for registered or combinato-

rial operation

• Up to 22 input terms and 10 outputs

• DIP, LCC, and PLCC available

—5 ns commercial version

4 ns t

CO

3 ns t

S

Logic Block Diagram (PDIP/CDIP)

V

SS

IIIIIIIIIICP/I

11 10 9 8 7 6 5 4 3 2 112

5 ns t

PD

181-MHz state machine

—10 ns military and industrial versions

7 ns t

CO

6 ns t

S

10 ns t

PD

110-M Hz state machine

—15-ns commercial, industrial, and military versions
—25-ns commercial, industrial, and military versions

• High reliability

—Proven Flash EPROM technology
—100% programming and functional testing

Functional Description

The Cypress PALCE22V10 is a CMOS Flash Erasable sec­ond-generation programmable array logic device. It is imple­mented with the familiar sum-of-products (AND-OR) logic
structure and the programmable macrocell.

PROGRAMMABLE

AND ARRAY

I/O

25
24
23
22
21
20
19

I/O

(132X 44)

I/O

5

1

I/O

2

I/O

3

I/O

4

N/C
I/O

5

I/O

6

I/O

7

8

CE22V10–2

I/O

4

NC

5

I

6

I

7

I

8
9

I

10

I

11

I

I/O

3

PLCC

Top View

CC

NC

I9I

CP/IVI/O

4 3 2 2827 261

121314 1516 1718

I

I

I

SS

NC

V

I/O

I/O

2

0

1

I/O

25
24
23
22
21
20
19

8

I/O

I/O

2

I/O

3

I/O

4

N/C
I/O

5

I/O

6

I/O

7

CE22V10–3

I/O

1

I/O

0

8

Reset

Macrocell

13 14 15 16 17 18 19 20 21 22 23 24

I I/O

9

Pin Configuration

10 12 14 16 16 14 12 10 8

Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell

I/O

8

NC

I/O

I
I
I

I
I
I

7

LCC

Top View

I9I

CP/IVI/O

4 3 2 282726
5
6
7
8
9
10
11

12131415161718

I

I

SS

V

I/O

1

NC

NC

6

0

CC

I

I/O

PAL is a registered trademark of Advanced Micro Devices.

Preset

V

CE22V10–1

CC

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03027 Rev. ** Revised September 1996

PALCE22V10

Selection Guide

tPD ns tS ns tCO ns ICC mA

Generic Part Number

PALCE22V10-5 5 3 4 130
PALCE22V10-7 7.5 5 5 130
PALCE22V10-10 10 10 6 6 7 7 90 150
PALCE22V10-15 15 15 10 10 8 8 90 120
PALCE22V10-25 25 25 15 15 15 15 90 120

Com’l Mil/Ind Com’l Mil/Ind Com’l Mil/Ind Com’l Mil/Ind

Functional Description (continued)

The P ALCE22V10 is ex ecuted in a 24-pin 300 -mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadl ess ch ip car­rier, a 28-le ad sq uare pl astic lead ed chi p carri er, and provides
up to 22 inputs and 10 outputs . The P ALCE22V10 can be elec­trically erased and rep rogrammed. The pro grammable m acro­cell provides the capab ility of defini ng the architect ure of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually selected, allowing complete
flexibility of outpu t config uration . Further co nfi gurabi lity is pro­vided through “array” confi gurable “output enable” for ea ch po­tential output. This feature allows the 10 outputs to be recon­figured as inputs on an i ndivi dual ba sis, o r al ternate ly use d as
a combination I/O controlled by the programmable array.

PALCE22V10 features a variable product term architecture.
There are 5 pairs of pr oduct term sums beg inning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized t o th e confi guratio ns fou nd in a majori ty of
applications without creating devices that burden the product
term structures with unusabl e product term s and lower perfor­mance.

Additional features of the Cypress PALCE22V10 include a
synchronous prese t and a n asy nchro nous r eset p roduct term.
These product terms are common to all macrocells, eliminat­ing the need to dedicate standard product terms for initializa­tion functions. The device automatically resets upon pow­er-up.

The PALCE22V10, featuring programmable macrocells and
variable product terms , pro vid es a de vic e wi th the flexibility to
implement logic functions in the 500- to 800-gate-array com­plexity. Since each of the 10 output pins may be individually
configured as inputs on a tem porary or permanent bas is, func-

tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten­tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en­abled as an output and an input through the selective use of
individual product terms associated with each o utp ut. Ea ch of
these outputs is ac hieved through an individual pro grammable
macrocell. These macrocells are programmable to provide a
combinatorial or regis tered inverting or non-in verting output. In
a registered mode of operat ion, the output of the regis ter is fed
back into the array, providing current status information to th e
array. This information is available for establishing the next
result in applicati ons such as control state machines. In a com­binatorial configur ati on, the com bi na toria l output or, if th e ou t­put is disabled, the sign al present on the I/O pi n is made avail­able to the array. The flexibility provided by both
programmable produc t term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.

Along with this increase in functional density, the Cypress
P ALCE22V10 provide s lower-power oper ation through t he use
of CMOS technology, and increased testability with Flash re­programmability.

Configuration Table

Registered/Combinatorial

C

1

0 0 Registered/Active LOW
0 1 Registered/Active HIGH
1 0 Combinatorial/Active LOW
1 1 Combinatorial/Active HIGH

C

0

Configuration

Document #: 38-03027 Rev. ** Page 2 of 13

Macrocell

PALCE22V10

AR

OUTPUT

SELECT

QD

MUX

CP

SP

INPUT/

FEEDBACK

MUX

S

1

C

1

C

0

Maximum Ratings

(Above which the useful life may be impaired. For us er guide­lines, not tested.)

Storage Temperature .................................–65

Ambient Temperature with

Power Applied.............................................–55

Supply Voltage to Ground Potential

(Pin 24 to Pin 12)...........................................–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State...............................................–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

Output Current into Outputs (LOW).............................16 mA

Note:

is the “instant on” case temperature.

1. T

A

°C to +150°C
°C to +125°C

Q

MACROCELL

SS

10

CE22V10–4

DC Programming Voltage.............................................12.5V

Latch-Up Current.....................................................>200 mA

Static Discharge Voltage

(per MIL-STD-883, Method 3015) .............................>2001V

Operating Range

Range

Commercial 0°C to +75°C 5V ±5%
Industrial –40°C to +85°C 5V ±10%

[1]

Military

Ambient

Temperature

V

–55°C to +125°C 5V ±10%

CC

Document #: 38-03027 Rev. ** Page 3 of 13

PALCE22V10

]

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V

V

V
V
I

IX

I

OZ

I

SC

I

CC1

I

CC2

OH

OL

IH
IL

[4]

[6]

Output HIGH Voltage VCC = Min.,

VIN = VIH or V

Output LOW Voltage VCC = Min.,

= VIH or V

V

IN

Input HIGH Level Guaranteed Inp ut Logical HIGH V oltage for All Inputs
Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs
Input Leakage Current VSS < VIN < VCC, VCC = Max. –10 10 µA
Output Leakage Current VCC = Max., VSS < V
Output Short Circuit Current VCC = Max., V
Standby Power Supply

Current

VCC = Max.,

= GND,

V

IN

Outputs Open in
Unprogrammed
Device

Operating Power Supply
Current

VCC = Max., VIL =

= 3V,

0V, V

IH

Output Open, De­vice Programmed
as a 10-Bit
Counter,
f = 25 MHz

[2]

IOH = –3.2 mA Com’l 2.4 V

IL

IOH = –2 mA Mil/Ind
IOL = 16 mA Com’l 0.5 V

IL

IOL = 12 mA Mil/Ind

OUT

OUT

= 0.5V

< V

[5,6]

[3]
[3]

CC

2.0 V

–0.5 0.8 V

–40 40 µA
–30 –130 mA

10, 15, 25 ns Com’l 90 mA
5, 7.5 ns 130 mA
15, 25 ns Mil/Ind 120 mA
10 ns 120 mA
10, 15, 25 ns Com’l 110 mA
5, 7.5 ns Com’l 140 mA
15, 25 ns Mil/Ind 130 mA
10 ns Mil/Ind 130 mA

Capacitance

[6]

Parameter Description Test Conditions Min. Max. Unit

C

IN

C

OUT

]

Endurance Characteristics

Input Capacitance VIN = 2.0V @ f = 1 MHz 10 pF
Output Capacitance V

[6]

= 2.0V @ f = 1 MHz 10 pF

OUT

Parameter Description Test Conditions Min. Max. Unit

N Minimum Reprogramm ing Cycle s Normal Programming Conditions 100 Cycles

Notes:

2. See the last page of this specificat io n for Gro up A subgroup testing information.

3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
(Min.) is equal to -3.0V for pulse durations less than 20 ns.

4. V

IL

5. Not more than one output shou ld be test ed at a time. Dura tion of the short circui t should not be more than one se cond. V

caused by tester ground degrad ation.

6. Tested initially and after any design or process changes that may affect these parameters.

= 0.5V has been chosen to a void test problems

OUT

Document #: 38-03027 Rev. ** Page 4 of 13