Cypress Semiconductor PALCE22V10-25PC, PALCE22V10-25PI, PALCE22V10-5PC, PALCE22V10-7JC, PALCE22V10-7PC Datasheet
...
22V10
PALCE22V10
Flash Erasable,
Reprogrammable CMOS PAL® Device
Features
• Low power
—90 mA max. commercial (10 ns)
—130 mA max. commercial (5 ns)
• CMOS Flash EPROM technology f or electrical erasabil-
ity and reprogrammability
• Variable product terms
—2 x (8 through 16) product terms
• User-programmable macrocell
—Output polarity control
—Individually selectable for registered or combinato-
rial operation
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
—5 ns commercial version
4 ns t
CO
3 ns t
S
Logic Block Diagram (PDIP/CDIP)
V
SS
IIIIIIIIIICP/I
11 10 9 8 7 6 5 4 3 2 112
5 ns t
PD
181-MHz state machine
—10 ns military and industrial versions
7 ns t
CO
6 ns t
S
10 ns t
PD
110-M Hz state machine
—15-ns commercial, industrial, and military versions
—25-ns commercial, industrial, and military versions
• High reliability
—Proven Flash EPROM technology
—100% programming and functional testing
Functional Description
The Cypress PALCE22V10 is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic
structure and the programmable macrocell.
PROGRAMMABLE
AND ARRAY
I/O
25
24
23
22
21
20
19
I/O
(132X 44)
I/O
5
1
I/O
2
I/O
3
I/O
4
N/C
I/O
5
I/O
6
I/O
7
8
CE22V10–2
I/O
4
NC
5
I
6
I
7
I
8
9
I
10
I
11
I
I/O
3
PLCC
Top View
CC
NC
I9I
CP/IVI/O
4 3 2 2827 261
121314 1516 1718
I
I
I
SS
NC
V
I/O
I/O
2
0
1
I/O
25
24
23
22
21
20
19
8
I/O
I/O
2
I/O
3
I/O
4
N/C
I/O
5
I/O
6
I/O
7
CE22V10–3
I/O
1
I/O
0
8
Reset
Macrocell
13 14 15 16 17 18 19 20 21 22 23 24
I I/O
9
Pin Configuration
10 12 14 16 16 14 12 10 8
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
I/O
8
NC
I/O
I
I
I
I
I
I
7
LCC
Top View
I9I
CP/IVI/O
4 3 2 282726
5
6
7
8
9
10
11
12131415161718
I
I
SS
V
I/O
1
NC
NC
6
0
CC
I
I/O
PAL is a registered trademark of Advanced Micro Devices.
Preset
V
CE22V10–1
CC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03027 Rev. ** Revised September 1996
PALCE22V10
Selection Guide
tPD ns tS ns tCO ns ICC mA
Generic Part Number
PALCE22V10-5 5 3 4 130
PALCE22V10-7 7.5 5 5 130
PALCE22V10-10 10 10 6 6 7 7 90 150
PALCE22V10-15 15 15 10 10 8 8 90 120
PALCE22V10-25 25 25 15 15 15 15 90 120
Com’l Mil/Ind Com’l Mil/Ind Com’l Mil/Ind Com’l Mil/Ind
Functional Description (continued)
The P ALCE22V10 is ex ecuted in a 24-pin 300 -mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadl ess ch ip carrier, a 28-le ad sq uare pl astic lead ed chi p carri er, and provides
up to 22 inputs and 10 outputs . The P ALCE22V10 can be electrically erased and rep rogrammed. The pro grammable m acrocell provides the capab ility of defini ng the architect ure of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually selected, allowing complete
flexibility of outpu t config uration . Further co nfi gurabi lity is provided through “array” confi gurable “output enable” for ea ch potential output. This feature allows the 10 outputs to be reconfigured as inputs on an i ndivi dual ba sis, o r al ternate ly use d as
a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of pr oduct term sums beg inning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized t o th e confi guratio ns fou nd in a majori ty of
applications without creating devices that burden the product
term structures with unusabl e product term s and lower performance.
Additional features of the Cypress PALCE22V10 include a
synchronous prese t and a n asy nchro nous r eset p roduct term.
These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms , pro vid es a de vic e wi th the flexibility to
implement logic functions in the 500- to 800-gate-array complexity. Since each of the 10 output pins may be individually
configured as inputs on a tem porary or permanent bas is, func-
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 potential outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of
individual product terms associated with each o utp ut. Ea ch of
these outputs is ac hieved through an individual pro grammable
macrocell. These macrocells are programmable to provide a
combinatorial or regis tered inverting or non-in verting output. In
a registered mode of operat ion, the output of the regis ter is fed
back into the array, providing current status information to th e
array. This information is available for establishing the next
result in applicati ons such as control state machines. In a combinatorial configur ati on, the com bi na toria l output or, if th e ou tput is disabled, the sign al present on the I/O pi n is made available to the array. The flexibility provided by both
programmable produc t term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.
Along with this increase in functional density, the Cypress
P ALCE22V10 provide s lower-power oper ation through t he use
of CMOS technology, and increased testability with Flash reprogrammability.
Configuration Table
Registered/Combinatorial
C
1
0 0 Registered/Active LOW
0 1 Registered/Active HIGH
1 0 Combinatorial/Active LOW
1 1 Combinatorial/Active HIGH
C
0
Configuration
Document #: 38-03027 Rev. ** Page 2 of 13
Macrocell
PALCE22V10
AR
OUTPUT
SELECT
QD
MUX
CP
SP
INPUT/
FEEDBACK
MUX
S
1
C
1
C
0
Maximum Ratings
(Above which the useful life may be impaired. For us er guidelines, not tested.)
Storage Temperature .................................–65
Ambient Temperature with
Power Applied.............................................–55
Supply Voltage to Ground Potential
(Pin 24 to Pin 12)...........................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State...............................................–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Output Current into Outputs (LOW).............................16 mA
Note:
is the “instant on” case temperature.
1. T
A
°C to +150°C
°C to +125°C
Q
MACROCELL
SS
10
CE22V10–4
DC Programming Voltage.............................................12.5V
Latch-Up Current.....................................................>200 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............................>2001V
Operating Range
Range
Commercial 0°C to +75°C 5V ±5%
Industrial –40°C to +85°C 5V ±10%
[1]
Military
Ambient
Temperature
V
–55°C to +125°C 5V ±10%
CC
Document #: 38-03027 Rev. ** Page 3 of 13
PALCE22V10
]
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
SC
I
CC1
I
CC2
OH
OL
IH
IL
[4]
[6]
Output HIGH Voltage VCC = Min.,
VIN = VIH or V
Output LOW Voltage VCC = Min.,
= VIH or V
V
IN
Input HIGH Level Guaranteed Inp ut Logical HIGH V oltage for All Inputs
Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs
Input Leakage Current VSS < VIN < VCC, VCC = Max. –10 10 µA
Output Leakage Current VCC = Max., VSS < V
Output Short Circuit Current VCC = Max., V
Standby Power Supply
Current
VCC = Max.,
= GND,
V
IN
Outputs Open in
Unprogrammed
Device
Operating Power Supply
Current
VCC = Max., VIL =
= 3V,
0V, V
IH
Output Open, Device Programmed
as a 10-Bit
Counter,
f = 25 MHz
[2]
IOH = –3.2 mA Com’l 2.4 V
IL
IOH = –2 mA Mil/Ind
IOL = 16 mA Com’l 0.5 V
IL
IOL = 12 mA Mil/Ind
OUT
OUT
= 0.5V
< V
[5,6]
[3]
[3]
CC
2.0 V
–0.5 0.8 V
–40 40 µA
–30 –130 mA
10, 15, 25 ns Com’l 90 mA
5, 7.5 ns 130 mA
15, 25 ns Mil/Ind 120 mA
10 ns 120 mA
10, 15, 25 ns Com’l 110 mA
5, 7.5 ns Com’l 140 mA
15, 25 ns Mil/Ind 130 mA
10 ns Mil/Ind 130 mA
Capacitance
[6]
Parameter Description Test Conditions Min. Max. Unit
C
IN
C
OUT
]
Endurance Characteristics
Input Capacitance VIN = 2.0V @ f = 1 MHz 10 pF
Output Capacitance V
[6]
= 2.0V @ f = 1 MHz 10 pF
OUT
Parameter Description Test Conditions Min. Max. Unit
N Minimum Reprogramm ing Cycle s Normal Programming Conditions 100 Cycles
Notes:
2. See the last page of this specificat io n for Gro up A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
(Min.) is equal to -3.0V for pulse durations less than 20 ns.
4. V
IL
5. Not more than one output shou ld be test ed at a time. Dura tion of the short circui t should not be more than one se cond. V
caused by tester ground degrad ation.
6. Tested initially and after any design or process changes that may affect these parameters.
= 0.5V has been chosen to a void test problems
OUT
Document #: 38-03027 Rev. ** Page 4 of 13
AC Test Loads and Waveforms
PALCE22V10
R1238
Ω
(319Ω MIL)
5pF
R2170
(236Ω MIL)
90%
10%
Ω
OUTPUT
CE22V10–5
(c)
C
L
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
R1238Ω
(319Ω MIL)
C
L
Ω
R2170
(236Ω MIL)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
(a) (b)
3.0V
GND
<2ns <2ns
ALL INPUT PULSES
90%
10%
(d)
Equivalent to: THÉ VENIN EQUIVALENT (Commercial) Equivalent to: THÉ VENIN EQUIVALENT (Military)
OUTPUT
Load Speed C
99Ω 136Ω
L
2.08V=V
Package
thc
CE22V10–6
OUTPUT
2.13V=V
thm
5, 7.5, 10, 15, 25 ns50 pF PDIP, CDIP,
PLCC, LCC
Ω
750
(1.2KΩ
MIL)
CE22V10–7
Parameter V
t
ER (- )
t
ER (+)
t
EA (+)
t
EA (- )
1.5V
2.6V
0V
V
X
thc
Output Waveform Measurement Level
V
OH
0.5V
V
OL
V
V
0.5V
1.5V
X
X
0.5V
(e) Test Waveforms
V
X
V
X
V
OH
V
OL
Document #: 38-03027 Rev. ** Page 5 of 13
PALCE22V10
]
Commercial Switching Characteristics PALCE22V10
22V10-5 22V10-7 22V10-10 22V10-15 22V10-25
WH
+ tWL))
Description
[8]
[9]
[10]
[8]
3 5 3 7.5 3 10 3 15 3 25 ns
6 8 10 15 25 ns
6 8 10 15 25 ns
2 4 2 5 2 7 2 8 2 15 ns
4 6 7 10 15 ns
CO
[6, 12]
CF
[6,14]
[6]
[6]
+ tS))
+ tS))
[11]
[6,13]
2.5 3 3 6 13 ns
2.5 3 3 6 13 ns
143 100 76.9 55.5 33.3 MHz
200 166 142 83.3 35.7 MHz
181 133 111 68.9 38.5 MHz
2.5 2.5 3 4.5 13 ns
4 5 6 10 25 ns
7.5 12 13 20 25 ns
4 6 8 10 15 ns
[6,15]
.
EA(+)
must be monotoni c and the ti ming co nstrai nts depicted in Pow er-Up Reset Waveform must be s atisfi ed
CC
1 1 1 1 1 µs
OH
internal (1/f
MAX
MAX3
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
PD
t
EA
t
ER
t
CO
t
S1
t
S2
t
H
t
P
t
WH
t
WL
f
MAX1
f
MAX2
f
MAX3
t
CF
t
AW
t
AR
t
AP
t
SPR
t
PR
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except t
Loads and Wav eforms is use d for t
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. The test load of part (a) of AC T est Loads and Waveforms is used for measuring t
t
EA(+)
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5 volts below V
T est Loads and W av eforms for enabl e and disabl e tes t wavefo rms and measur ement r eference l evel s.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure
proper operation, the rise in V
Input to Output
Propagation Delay
Input to Output
Enable Delay
Input to Output
Disable Delay
Clock to Output Delay
Input or Feedback Set-Up Time 3 5 6 10 15 ns
Synchronous Preset Set-Up
Time
Input Hold Time 0 0 0 0 0 ns
External Clock Period (tCO + tS) 7 10 12 20 30 ns
Clock Width HIGH
Clock Width LOW
External Maximum
Frequency (1/(t
Data Path Maximum Frequency
(1/(t
Internal Feedback Maximum
Frequency (1/(t
Register Clock to
Feedback Input
Asynchronous Re se t Width 8 8 10 15 25 ns
Asynchronous Re set
Recovery Time
Asynchronous Re se t to
Registered Output Delay
Synchronous Preset
Recovery Time
Power-Up Reset Time
only. Pleas e see part (e ) of AC Test Loads and Wavef orms f or enab le and di sable test waveforms and me asuremen t referenc e le vels.
[2,7]
and t
ER
min. or a previous LOW level has risen to 0.5 volts abov e VOL max. Please see part (e) of A C
) as measured (s ee Note a bove) minus tS.
. Part (b) of AC T e st Loads and W aveforms is used fo r tER. Part (c) of AC T est
EA(+)
. The test load of part ( c) of AC Test Loads and Waveforms is used for me asuring
EA(-)
Document #: 38-03027 Rev. ** Page 6 of 13
PALCE22V10
Military and Industrial Switching Characteri stics PALCE22V10
[2,7]
22V10-10 22V10-15 22V10-25
Parameter Description Min. Max. Min. Max. Min. Max. Unit
t
PD
t
EA
t
ER
t
CO
t
S1
t
S2
t
H
t
P
t
WH
t
WL
f
MAX1
f
MAX2
f
MAX3
t
CF
t
AW
t
AR
t
AP
t
SPR
t
PR
Input to Output
Propagation Delay
[8]
Input to Output Enable Delay
Input to Output Disa ble De lay
Clock to Output Delay
[8]
[9]
[10]
3 10 3 15 3 25 ns
10 15 25 ns
10 15 25 ns
2 7 2 8 2 15 ns
Input or Feedback Set-Up Time 6 10 18 ns
Synchronous Preset Set-Up
7 10 18 ns
Time
Input Hold Time 0 0 0 ns
External Clock Period (tCO + tS) 12 20 33 ns
11]
[6,12 ]
CF
[6,14]
[6]
[6]
+ tS))
[6,13]
3 6 14 ns
3 6 14 ns
76.9 50.0 30.3 MHz
142 83.3 35.7 MHz
111 68.9 32.2 MHz
3 4.5 13 ns
Clock Width HIGH
Clock Width LOW
External Maximum Frequency
+ tS))
(1/(t
CO
Data Path Maxi mum Frequ ency
+ tWL))
(1/(t
WH
Internal Feedback Maximum
Frequency (1/(t
Register Clock to
Feedback Input
Asynchronous Reset Width 10 15 25 ns
Asynchronous Reset
6 12 25 ns
Recovery Time
Asynchronous Reset to
12 20 25 ns
Registered Output Del ay
Synchronous Preset
8 20 25 ns
Recovery Time
Power-Up Reset Time
[6,15]
1 1 1 µs
Document #: 38-03027 Rev. ** Page 7 of 13
Switching Waveforms
INPUTS I/O,
REGISTERED
FEEDBACK
SYNCHRONOUS
PRESET
CP
PALCE22V10
t
t
S
t
H
WH
t
WL
ASYNCHRONOUS
COMBINATORIAL
RESET
REGISTERED
OUTPUTS
OUTPUTS
Power-Up Reset Waveform
SUPPLY VOLTAGE
POWER
REGISTERED
ACTIVE LOW
OUTPUTS
[15]
10%
t
SPR
t
AW
t
CO
t
AP
t
PD
90%
t
P
t
AR
[10]
t
ER
[10]
t
ER
t
PR
t
S
[9]
t
EA
[9]
t
EA
CE22V10–8
V
CC
CLOCK
t
MAX= 1 µs
PR
t
WL
CE22V10–9
Document #: 38-03027 Rev. ** Page 8 of 13
Functional Logic Diagram for PALCE22V10
PALCE22V10
1
0
AR
OE
0
S
S
S
7
OE
0
S
S
S
OE
OE
OE
9
0
S
S
S
11
0
S
S
S
13
0
S
S
S
2
3
4
4
128
16 20 24 28
32 36 40
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
23
22
21
20
19
15
5
OE
0
S
S
S
15
6
OE
0
S
S
S
13
7
OE
0
S
S
S
11
8
OE
0
S
S
S
OE
9
0
S
S
S
7
9
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
18
17
16
15
14
10
11
SP
CE22V10–10
13
Document #: 38-03027 Rev. ** Page 9 of 13
PALCE22V10
Ordering Information
I
(mA)
(ns)
t
CC
130 5 3 4 PALCE22V10-5PC P13 24-Lead (300 MIL) Molded DIP Commercial
130 7.5 5 5 PALCE22V10-7JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
90 10 6 7 PALCE22V10-10JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
150 10 6 7 PALCE22V10-10JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
150 10 6 7 PALCE22V10-10DMB D14 24-Lead (300-Mil) CerDIP Military
90 15 7.5 10 PALCE22V10-15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
120 15 7.5 10 PALCE22V10-15JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
120 15 7.5 10 PALCE22V10-15DMB D14 24-Lead (300-Mil) CerDIP Military
90 25 15 15 PALCE22V10-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
120 25 15 15 PALCE22V10-25JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
120 25 15 15 PALCE22V10-25DMB D14 24-Lead (300-Mil) CerDIP Military
PD
t
t
S
(ns)
CO
(ns) Ordering Code
PALCE22V10-5JC J64 28-Lead Plastic Leaded Chip Carrier
PALCE22V10-7PC P13 24-Lead (300-Mil) Molded DIP
PALCE22V10-10PC P13 24-Lead (300-Mil) Molded DIP
PALCE22V10-10PI P13 24-Lead (300-Mil) Molded DIP
PALCE22V10-10KMB K73 24-Lead Rectangular Cerpack
PALCE22V10-10LMB L64 28-Square Leadless Chip Carrier
PALCE22V10-15PC P13 24-Lead (300-Mil) Molded DIP
PALCE22V10-15PI P13 24-Lead (300-Mil) Molded DIP
PALCE22V10-15KMB K73 24-Lead Rectangular Cerpack
PALCE22V10-15LMB L64 28-Square Leadless Chip Carrier
PALCE22V10-25PC P13 24-Lead (300-Mil) Molded DIP
PALCE22V10-25PI P13 24-Lead (300-Mil) Molded DIP
PALCE22V10-25KMB K73 24-Lead Rectangular Cerpack
PALCE22V10-25LMB L64 28-Square Leadless Chip Carrier
Package
Name Package Type
Operating
Range
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter Subgroups
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Document #: 38-03027 Rev. ** Page 10 of 13
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Parameter Subgroups
t
PD
t
CO
t
S
t
H
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
Package Diagrams
24–Lead (300–Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
24–Lead Rectangular Cerpack K73
MIL-STD-1835 F-6 Config.A
PALCE22V10
28–Lead Plastic Leaded Chip Carrier J64
28–Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
Document #: 38-03027 Rev. ** P age 11 of 13
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
PALCE22V10
24–Lead (300–Mil) Molded DIP
P13/P13A
Document #: 38-03027 Rev. ** Page 12 of 13
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
Document Title: PALCE22V10 Flash Erasable, Reprogrammable CMOS PAL® Device
Document Number: 38-03027
REV. ECN NO.
** 106372 07/11/01 SZV Change from Spec Number: 38-00447 to 38-03027
Issue
Date
Orig. of
Change Description of Change
PALCE22V10
Document #: 38-03027 Rev. ** Page 13 of 13
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